arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2012 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         chosen {
  10                 stdout-path = &uart4;
  11         };
  12
  13         memory@10000000 {
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         leds {
  18                 compatible = "gpio-leds";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_gpio_leds>;
  21
  22                 user {
  23                         label = "debug";
  24                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  25                 };
  26         };
  27
  28         clocks {
  29                 codec_osc: anaclk2 {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <24576000>;
  33                 };
  34         };
  35
  36         regulators {
  37                 compatible = "simple-bus";
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 reg_audio: regulator@0 {
  42                         compatible = "regulator-fixed";
  43                         reg = <0>;
  44                         regulator-name = "cs42888_supply";
  45                         regulator-min-microvolt = <3300000>;
  46                         regulator-max-microvolt = <3300000>;
  47                         regulator-always-on;
  48                 };
  49
  50                 reg_usb_h1_vbus: regulator@1 {
  51                         compatible = "regulator-fixed";
  52                         reg = <1>;
  53                         regulator-name = "usb_h1_vbus";
  54                         regulator-min-microvolt = <5000000>;
  55                         regulator-max-microvolt = <5000000>;
  56                         gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  57                         enable-active-high;
  58                 };
  59
  60                 reg_usb_otg_vbus: regulator@2 {
  61                         compatible = "regulator-fixed";
  62                         reg = <2>;
  63                         regulator-name = "usb_otg_vbus";
  64                         regulator-min-microvolt = <5000000>;
  65                         regulator-max-microvolt = <5000000>;
  66                         gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
  67                         enable-active-high;
  68                 };
  69         };
  70
  71         sound-cs42888 {
  72                 compatible = "fsl,imx6-sabreauto-cs42888",
  73                         "fsl,imx-audio-cs42888";
  74                 model = "imx-cs42888";
  75                 audio-cpu = <&esai>;
  76                 audio-asrc = <&asrc>;
  77                 audio-codec = <&codec>;
  78                 audio-routing =
  79                         "Line Out Jack", "AOUT1L",
  80                         "Line Out Jack", "AOUT1R",
  81                         "Line Out Jack", "AOUT2L",
  82                         "Line Out Jack", "AOUT2R",
  83                         "Line Out Jack", "AOUT3L",
  84                         "Line Out Jack", "AOUT3R",
  85                         "Line Out Jack", "AOUT4L",
  86                         "Line Out Jack", "AOUT4R",
  87                         "AIN1L", "Line In Jack",
  88                         "AIN1R", "Line In Jack",
  89                         "AIN2L", "Line In Jack",
  90                         "AIN2R", "Line In Jack";
  91         };
  92
  93         sound-spdif {
  94                 compatible = "fsl,imx-audio-spdif",
  95                            "fsl,imx-sabreauto-spdif";
  96                 model = "imx-spdif";
  97                 spdif-controller = <&spdif>;
  98                 spdif-in;
  99         };
 100
 101         backlight {
 102                 compatible = "pwm-backlight";
 103                 pwms = <&pwm3 0 5000000>;
 104                 brightness-levels = <0 4 8 16 32 64 128 255>;
 105                 default-brightness-level = <7>;
 106                 status = "okay";
 107         };
 108
 109         i2cmux {
 110                 compatible = "i2c-mux-gpio";
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_i2c3mux>;
 115                 mux-gpios = <&gpio5 4 0>;
 116                 i2c-parent = <&i2c3>;
 117                 idle-state = <0>;
 118
 119                 i2c@1 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         reg = <1>;
 123
 124                         adv7180: camera@21 {
 125                                 compatible = "adi,adv7180";
 126                                 reg = <0x21>;
 127                                 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
 128                                 interrupt-parent = <&gpio1>;
 129                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 130
 131                                 port {
 132                                         adv7180_to_ipu1_csi0_mux: endpoint {
 133                                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 134                                                 bus-width = <8>;
 135                                         };
 136                                 };
 137                         };
 138
 139                         max7310_a: gpio@30 {
 140                                 compatible = "maxim,max7310";
 141                                 reg = <0x30>;
 142                                 gpio-controller;
 143                                 #gpio-cells = <2>;
 144                         };
 145
 146                         max7310_b: gpio@32 {
 147                                 compatible = "maxim,max7310";
 148                                 reg = <0x32>;
 149                                 gpio-controller;
 150                                 #gpio-cells = <2>;
 151                                 pinctrl-names = "default";
 152                                 pinctrl-0 = <&pinctrl_max7310>;
 153                                 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 154                         };
 155
 156                         max7310_c: gpio@34 {
 157                                 compatible = "maxim,max7310";
 158                                 reg = <0x34>;
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                         };
 162
 163                         light-sensor@44 {
 164                                 compatible = "isil,isl29023";
 165                                 reg = <0x44>;
 166                                 interrupt-parent = <&gpio5>;
 167                                 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
 168                         };
 169
 170                         magnetometer@e {
 171                                 compatible = "fsl,mag3110";
 172                                 reg = <0x0e>;
 173                                 interrupt-parent = <&gpio2>;
 174                                 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
 175                         };
 176
 177                         accelerometer@1c {
 178                                 compatible = "fsl,mma8451";
 179                                 reg = <0x1c>;
 180                                 interrupt-parent = <&gpio6>;
 181                                 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
 182                         };
 183                 };
 184         };
 185 };
 186
 187 &ipu1_csi0_from_ipu1_csi0_mux {
 188         bus-width = <8>;
 189 };
 190
 191 &ipu1_csi0_mux_from_parallel_sensor {
 192         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 193         bus-width = <8>;
 194 };
 195
 196 &ipu1_csi0 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 199 };
 200
 201 &clks {
 202         assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 203                           <&clks IMX6QDL_PLL4_BYPASS>,
 204                           <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 205                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 206                           <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
 207         assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
 208                                  <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 209                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 210                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 211         assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
 212 };
 213
 214 &ecspi1 {
 215         cs-gpios = <&gpio3 19 0>;
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 218         status = "disabled"; /* pin conflict with WEIM NOR */
 219
 220         flash: m25p80@0 {
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 compatible = "st,m25p32", "jedec,spi-nor";
 224                 spi-max-frequency = <20000000>;
 225                 reg = <0>;
 226         };
 227 };
 228
 229 &esai {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_esai>;
 232         assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
 233                           <&clks IMX6QDL_CLK_ESAI_EXTAL>;
 234         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 235         assigned-clock-rates = <0>, <24576000>;
 236         status = "okay";
 237 };
 238
 239 &fec {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_enet>;
 242         phy-mode = "rgmii";
 243         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 244                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 245         fsl,err006687-workaround-present;
 246         status = "okay";
 247 };
 248
 249 &gpmi {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_gpmi_nand>;
 252         status = "okay";
 253 };
 254
 255 &hdmi {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_hdmi_cec>;
 258         ddc-i2c-bus = <&i2c2>;
 259         status = "okay";
 260 };
 261
 262 &i2c2 {
 263         clock-frequency = <100000>;
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_i2c2>;
 266         status = "okay";
 267
 268         pmic: pfuze100@8 {
 269                 compatible = "fsl,pfuze100";
 270                 reg = <0x08>;
 271
 272                 regulators {
 273                         sw1a_reg: sw1ab {
 274                                 regulator-min-microvolt = <300000>;
 275                                 regulator-max-microvolt = <1875000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                                 regulator-ramp-delay = <6250>;
 279                         };
 280
 281                         sw1c_reg: sw1c {
 282                                 regulator-min-microvolt = <300000>;
 283                                 regulator-max-microvolt = <1875000>;
 284                                 regulator-boot-on;
 285                                 regulator-always-on;
 286                                 regulator-ramp-delay = <6250>;
 287                         };
 288
 289                         sw2_reg: sw2 {
 290                                 regulator-min-microvolt = <800000>;
 291                                 regulator-max-microvolt = <3300000>;
 292                                 regulator-boot-on;
 293                                 regulator-always-on;
 294                         };
 295
 296                         sw3a_reg: sw3a {
 297                                 regulator-min-microvolt = <400000>;
 298                                 regulator-max-microvolt = <1975000>;
 299                                 regulator-boot-on;
 300                                 regulator-always-on;
 301                         };
 302
 303                         sw3b_reg: sw3b {
 304                                 regulator-min-microvolt = <400000>;
 305                                 regulator-max-microvolt = <1975000>;
 306                                 regulator-boot-on;
 307                                 regulator-always-on;
 308                         };
 309
 310                         sw4_reg: sw4 {
 311                                 regulator-min-microvolt = <800000>;
 312                                 regulator-max-microvolt = <3300000>;
 313                         };
 314
 315                         swbst_reg: swbst {
 316                                 regulator-min-microvolt = <5000000>;
 317                                 regulator-max-microvolt = <5150000>;
 318                         };
 319
 320                         snvs_reg: vsnvs {
 321                                 regulator-min-microvolt = <1000000>;
 322                                 regulator-max-microvolt = <3000000>;
 323                                 regulator-boot-on;
 324                                 regulator-always-on;
 325                         };
 326
 327                         vref_reg: vrefddr {
 328                                 regulator-boot-on;
 329                                 regulator-always-on;
 330                         };
 331
 332                         vgen1_reg: vgen1 {
 333                                 regulator-min-microvolt = <800000>;
 334                                 regulator-max-microvolt = <1550000>;
 335                         };
 336
 337                         vgen2_reg: vgen2 {
 338                                 regulator-min-microvolt = <800000>;
 339                                 regulator-max-microvolt = <1550000>;
 340                         };
 341
 342                         vgen3_reg: vgen3 {
 343                                 regulator-min-microvolt = <1800000>;
 344                                 regulator-max-microvolt = <3300000>;
 345                         };
 346
 347                         vgen4_reg: vgen4 {
 348                                 regulator-min-microvolt = <1800000>;
 349                                 regulator-max-microvolt = <3300000>;
 350                                 regulator-always-on;
 351                         };
 352
 353                         vgen5_reg: vgen5 {
 354                                 regulator-min-microvolt = <1800000>;
 355                                 regulator-max-microvolt = <3300000>;
 356                                 regulator-always-on;
 357                         };
 358
 359                         vgen6_reg: vgen6 {
 360                                 regulator-min-microvolt = <1800000>;
 361                                 regulator-max-microvolt = <3300000>;
 362                                 regulator-always-on;
 363                         };
 364                 };
 365         };
 366
 367         codec: cs42888@48 {
 368                 compatible = "cirrus,cs42888";
 369                 reg = <0x48>;
 370                 clocks = <&codec_osc>;
 371                 clock-names = "mclk";
 372                 VA-supply = <&reg_audio>;
 373                 VD-supply = <&reg_audio>;
 374                 VLS-supply = <&reg_audio>;
 375                 VLC-supply = <&reg_audio>;
 376         };
 377
 378 };
 379
 380 &i2c3 {
 381         pinctrl-names = "default";
 382         pinctrl-0 = <&pinctrl_i2c3>;
 383         status = "okay";
 384 };
 385
 386 &iomuxc {
 387         pinctrl-names = "default";
 388         pinctrl-0 = <&pinctrl_hog>;
 389
 390         imx6qdl-sabreauto {
 391                 pinctrl_hog: hoggrp {
 392                         fsl,pins = <
 393                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 394                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 395                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 396                         >;
 397                 };
 398
 399                 pinctrl_ecspi1: ecspi1grp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 402                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 403                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 404                         >;
 405                 };
 406
 407                 pinctrl_ecspi1_cs: ecspi1cs {
 408                         fsl,pins = <
 409                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 410                         >;
 411                 };
 412
 413                 pinctrl_enet: enetgrp {
 414                         fsl,pins = <
 415                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 416                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 417                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 418                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 419                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 420                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 421                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 422                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 423                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 424                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 425                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 426                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 427                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 428                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 429                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 430                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 431                         >;
 432                 };
 433
 434                 pinctrl_esai: esaigrp {
 435                         fsl,pins = <
 436                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 437                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 438                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 439                                 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 440                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 441                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 442                                 MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 443                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 444                                 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 445                                 MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 446                         >;
 447                 };
 448
 449                 pinctrl_gpio_leds: gpioledsgrp {
 450                         fsl,pins = <
 451                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 452                         >;
 453                 };
 454
 455                 pinctrl_gpmi_nand: gpminandgrp {
 456                         fsl,pins = <
 457                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 458                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 459                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 460                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 461                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 462                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 463                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 464                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 465                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 466                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 467                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 468                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 469                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 470                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 471                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 472                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 473                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 474                         >;
 475                 };
 476
 477                 pinctrl_hdmi_cec: hdmicecgrp {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 480                         >;
 481                 };
 482
 483                 pinctrl_i2c2: i2c2grp {
 484                         fsl,pins = <
 485                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 486                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 487                         >;
 488                 };
 489
 490                 pinctrl_i2c3: i2c3grp {
 491                         fsl,pins = <
 492                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 493                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 494                         >;
 495                 };
 496
 497                 pinctrl_i2c3mux: i2c3muxgrp {
 498                         fsl,pins = <
 499                                 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
 500                         >;
 501                 };
 502
 503                 pinctrl_ipu1_csi0: ipu1csi0grp {
 504                         fsl,pins = <
 505                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
 506                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
 507                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
 508                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
 509                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
 510                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
 511                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
 512                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
 513                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
 514                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
 515                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
 516                         >;
 517                 };
 518
 519                 pinctrl_max7310: max7310grp {
 520                         fsl,pins = <
 521                                 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
 522                         >;
 523                 };
 524
 525                 pinctrl_pwm3: pwm1grp {
 526                         fsl,pins = <
 527                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 528                         >;
 529                 };
 530
 531                 pinctrl_gpt_input_capture0: gptinputcapture0grp {
 532                         fsl,pins = <
 533                                 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1       0x1b0b0
 534                         >;
 535                 };
 536
 537                 pinctrl_gpt_input_capture1: gptinputcapture1grp {
 538                         fsl,pins = <
 539                                 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2       0x1b0b0
 540                         >;
 541                 };
 542
 543                 pinctrl_spdif: spdifgrp {
 544                         fsl,pins = <
 545                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 546                         >;
 547                 };
 548
 549                 pinctrl_uart4: uart4grp {
 550                         fsl,pins = <
 551                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 552                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 553                         >;
 554                 };
 555
 556                 pinctrl_usbotg: usbotggrp {
 557                         fsl,pins = <
 558                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 559                         >;
 560                 };
 561
 562                 pinctrl_usdhc3: usdhc3grp {
 563                         fsl,pins = <
 564                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 565                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 566                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 567                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 568                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 569                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 570                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 571                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 572                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 573                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 574                         >;
 575                 };
 576
 577                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 578                         fsl,pins = <
 579                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 580                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 581                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 582                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 583                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 584                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 585                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 586                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 587                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 588                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 589                         >;
 590                 };
 591
 592                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 593                         fsl,pins = <
 594                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 595                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 596                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 597                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 598                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 599                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 600                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 601                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 602                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 603                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 604                         >;
 605                 };
 606
 607                 pinctrl_weim_cs0: weimcs0grp {
 608                         fsl,pins = <
 609                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 610                         >;
 611                 };
 612
 613                 pinctrl_weim_nor: weimnorgrp {
 614                         fsl,pins = <
 615                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 616                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 617                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 618                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 619                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 620                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 621                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 622                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 623                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 624                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 625                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 626                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 627                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 628                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 629                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 630                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 631                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 632                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 633                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 634                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 635                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 636                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 637                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 638                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 639                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 640                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 641                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 642                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 643                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 644                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 645                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 646                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 647                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 648                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 649                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 650                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 651                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 652                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 653                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 654                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 655                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 656                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 657                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 658                         >;
 659                 };
 660         };
 661 };
 662
 663 &ldb {
 664         status = "okay";
 665
 666         lvds-channel@0 {
 667                 fsl,data-mapping = "spwg";
 668                 fsl,data-width = <18>;
 669                 status = "okay";
 670
 671                 display-timings {
 672                         native-mode = <&timing0>;
 673                         timing0: hsd100pxn1 {
 674                                 clock-frequency = <65000000>;
 675                                 hactive = <1024>;
 676                                 vactive = <768>;
 677                                 hback-porch = <220>;
 678                                 hfront-porch = <40>;
 679                                 vback-porch = <21>;
 680                                 vfront-porch = <7>;
 681                                 hsync-len = <60>;
 682                                 vsync-len = <10>;
 683                         };
 684                 };
 685         };
 686 };
 687
 688 &pwm3 {
 689         pinctrl-names = "default";
 690         pinctrl-0 = <&pinctrl_pwm3>;
 691         status = "okay";
 692 };
 693
 694 &spdif {
 695         pinctrl-names = "default";
 696         pinctrl-0 = <&pinctrl_spdif>;
 697         status = "okay";
 698 };
 699
 700 &uart4 {
 701         pinctrl-names = "default";
 702         pinctrl-0 = <&pinctrl_uart4>;
 703         status = "okay";
 704 };
 705
 706 &usbh1 {
 707         vbus-supply = <&reg_usb_h1_vbus>;
 708         status = "okay";
 709 };
 710
 711 &usbotg {
 712         vbus-supply = <&reg_usb_otg_vbus>;
 713         pinctrl-names = "default";
 714         pinctrl-0 = <&pinctrl_usbotg>;
 715         status = "okay";
 716 };
 717
 718 &usdhc3 {
 719         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 720         pinctrl-0 = <&pinctrl_usdhc3>;
 721         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 722         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 723         cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 724         wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 725         status = "okay";
 726 };
 727
 728 &weim {
 729         pinctrl-names = "default";
 730         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 731         ranges = <0 0 0x08000000 0x08000000>;
 732         status = "disabled"; /* pin conflict with SPI NOR */
 733
 734         nor@0,0 {
 735                 compatible = "cfi-flash";
 736                 reg = <0 0 0x02000000>;
 737                 #address-cells = <1>;
 738                 #size-cells = <1>;
 739                 bank-width = <2>;
 740                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 741                                 0x0000c000 0x1404a38e 0x00000000>;
 742         };
 743 };