arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

   1 /*
   2  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         model = "Phytec phyFLEX-i.MX6 Ouad";
  16         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  17
  18         memory {
  19                 reg = <0x10000000 0x80000000>;
  20         };
  21
  22         regulators {
  23                 compatible = "simple-bus";
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 reg_usb_otg_vbus: regulator@0 {
  28                         compatible = "regulator-fixed";
  29                         reg = <0>;
  30                         regulator-name = "usb_otg_vbus";
  31                         regulator-min-microvolt = <5000000>;
  32                         regulator-max-microvolt = <5000000>;
  33                         gpio = <&gpio4 15 0>;
  34                 };
  35
  36                 reg_usb_h1_vbus: regulator@1 {
  37                         compatible = "regulator-fixed";
  38                         reg = <1>;
  39                         regulator-name = "usb_h1_vbus";
  40                         regulator-min-microvolt = <5000000>;
  41                         regulator-max-microvolt = <5000000>;
  42                         gpio = <&gpio1 0 0>;
  43                 };
  44         };
  45
  46         gpio_leds: leds {
  47                 compatible = "gpio-leds";
  48
  49                 green {
  50                         label = "phyflex:green";
  51                         gpios = <&gpio1 30 0>;
  52                 };
  53
  54                 red {
  55                         label = "phyflex:red";
  56                         gpios = <&gpio2 31 0>;
  57                 };
  58         };
  59 };
  60
  61 &ecspi3 {
  62         pinctrl-names = "default";
  63         pinctrl-0 = <&pinctrl_ecspi3>;
  64         status = "okay";
  65         fsl,spi-num-chipselects = <1>;
  66         cs-gpios = <&gpio4 24 0>;
  67
  68         flash@0 {
  69                 compatible = "m25p80";
  70                 spi-max-frequency = <20000000>;
  71                 reg = <0>;
  72         };
  73 };
  74
  75 &i2c1 {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_i2c1>;
  78         status = "okay";
  79
  80         eeprom@50 {
  81                 compatible = "atmel,24c32";
  82                 reg = <0x50>;
  83         };
  84
  85         pmic@58 {
  86                 compatible = "dlg,da9063";
  87                 reg = <0x58>;
  88                 interrupt-parent = <&gpio4>;
  89                 interrupts = <17 0x8>; /* active-low GPIO4_17 */
  90
  91                 regulators {
  92                         vddcore_reg: bcore1 {
  93                                 regulator-min-microvolt = <730000>;
  94                                 regulator-max-microvolt = <1380000>;
  95                                 regulator-always-on;
  96                         };
  97
  98                         vddsoc_reg: bcore2 {
  99                                 regulator-min-microvolt = <730000>;
 100                                 regulator-max-microvolt = <1380000>;
 101                                 regulator-always-on;
 102                         };
 103
 104                         vdd_ddr3_reg: bpro {
 105                                 regulator-min-microvolt = <1500000>;
 106                                 regulator-max-microvolt = <1500000>;
 107                                 regulator-always-on;
 108                         };
 109
 110                         vdd_3v3_reg: bperi {
 111                                 regulator-min-microvolt = <3300000>;
 112                                 regulator-max-microvolt = <3300000>;
 113                                 regulator-always-on;
 114                         };
 115
 116                         vdd_buckmem_reg: bmem {
 117                                 regulator-min-microvolt = <3300000>;
 118                                 regulator-max-microvolt = <3300000>;
 119                                 regulator-always-on;
 120                         };
 121
 122                         vdd_eth_reg: bio {
 123                                 regulator-min-microvolt = <1200000>;
 124                                 regulator-max-microvolt = <1200000>;
 125                                 regulator-always-on;
 126                         };
 127
 128                         vdd_eth_io_reg: ldo4 {
 129                                 regulator-min-microvolt = <2500000>;
 130                                 regulator-max-microvolt = <2500000>;
 131                                 regulator-always-on;
 132                         };
 133
 134                         vdd_mx6_snvs_reg: ldo5 {
 135                                 regulator-min-microvolt = <3000000>;
 136                                 regulator-max-microvolt = <3000000>;
 137                                 regulator-always-on;
 138                         };
 139
 140                         vdd_3v3_pmic_io_reg: ldo6 {
 141                                 regulator-min-microvolt = <3300000>;
 142                                 regulator-max-microvolt = <3300000>;
 143                                 regulator-always-on;
 144                         };
 145
 146                         vdd_sd0_reg: ldo9 {
 147                                 regulator-min-microvolt = <3300000>;
 148                                 regulator-max-microvolt = <3300000>;
 149                         };
 150
 151                         vdd_sd1_reg: ldo10 {
 152                                 regulator-min-microvolt = <3300000>;
 153                                 regulator-max-microvolt = <3300000>;
 154                         };
 155
 156                         vdd_mx6_high_reg: ldo11 {
 157                                 regulator-min-microvolt = <3000000>;
 158                                 regulator-max-microvolt = <3000000>;
 159                                 regulator-always-on;
 160                         };
 161                 };
 162         };
 163 };
 164
 165 &iomuxc {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_hog>;
 168
 169         imx6q-phytec-pfla02 {
 170                 pinctrl_hog: hoggrp {
 171                         fsl,pins = <
 172                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 173                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
 174                                 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
 175                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
 176                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
 177                         >;
 178                 };
 179
 180                 pinctrl_ecspi3: ecspi3grp {
 181                         fsl,pins = <
 182                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 183                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 184                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 185                         >;
 186                 };
 187
 188                 pinctrl_enet: enetgrp {
 189                         fsl,pins = <
 190                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 191                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 192                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 193                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 194                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 195                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 196                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 197                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 198                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 199                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 200                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 201                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 202                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 203                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 204                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 205                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 206                         >;
 207                 };
 208
 209                 pinctrl_gpmi_nand: gpminandgrp {
 210                         fsl,pins = <
 211                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 212                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 213                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 214                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 215                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 216                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 217                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 218                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 219                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 220                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 221                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 222                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 223                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 224                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 225                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 226                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 227                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 228                         >;
 229                 };
 230
 231                 pinctrl_i2c1: i2c1grp {
 232                         fsl,pins = <
 233                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 234                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 235                         >;
 236                 };
 237
 238                 pinctrl_uart3: uart3grp {
 239                         fsl,pins = <
 240                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 241                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 242                                 MX6QDL_PAD_EIM_D30__UART3_RTS_B         0x1b0b1
 243                                 MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 244                         >;
 245                 };
 246
 247                 pinctrl_uart4: uart4grp {
 248                         fsl,pins = <
 249                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 250                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 251                         >;
 252                 };
 253
 254                 pinctrl_usbh1: usbh1grp {
 255                         fsl,pins = <
 256                                 MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
 257                         >;
 258                 };
 259
 260                 pinctrl_usbotg: usbotggrp {
 261                         fsl,pins = <
 262                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 263                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 264                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
 265                         >;
 266                 };
 267
 268                 pinctrl_usdhc2: usdhc2grp {
 269                         fsl,pins = <
 270                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 271                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 272                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 273                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 274                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 275                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 276                         >;
 277                 };
 278
 279                 pinctrl_usdhc3: usdhc3grp {
 280                         fsl,pins = <
 281                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 282                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 283                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 284                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 285                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 286                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 287                         >;
 288                 };
 289
 290                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 291                         fsl,pins = <
 292                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 293                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 294                         >;
 295                 };
 296         };
 297 };
 298
 299 &fec {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_enet>;
 302         phy-mode = "rgmii";
 303         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 304         phy-supply = <&vdd_eth_io_reg>;
 305         status = "disabled";
 306 };
 307
 308 &gpmi {
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_gpmi_nand>;
 311         nand-on-flash-bbt;
 312         status = "disabled";
 313 };
 314
 315 &uart3 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart3>;
 318         status = "disabled";
 319 };
 320
 321 &uart4 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_uart4>;
 324         status = "disabled";
 325 };
 326
 327 &usbh1 {
 328         vbus-supply = <&reg_usb_h1_vbus>;
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&pinctrl_usbh1>;
 331         status = "disabled";
 332 };
 333
 334 &usbotg {
 335         vbus-supply = <&reg_usb_otg_vbus>;
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_usbotg>;
 338         disable-over-current;
 339         status = "disabled";
 340 };
 341
 342 &usdhc2 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_usdhc2>;
 345         cd-gpios = <&gpio1 4 0>;
 346         wp-gpios = <&gpio1 2 0>;
 347         status = "disabled";
 348 };
 349
 350 &usdhc3 {
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_usdhc3
 353                      &pinctrl_usdhc3_cdwp>;
 354         cd-gpios = <&gpio1 27 0>;
 355         wp-gpios = <&gpio1 29 0>;
 356         status = "disabled";
 357 };