arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
   4  * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
   5  * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
   6  *
   7  * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/sound/fsl-imx-audmux.h>
  12
  13 / {
  14         reg_1p0v_s0: regulator-1p0v-s0 {
  15                 compatible = "regulator-fixed";
  16                 regulator-name = "V_1V0_S0";
  17                 regulator-min-microvolt = <1000000>;
  18                 regulator-max-microvolt = <1000000>;
  19                 regulator-always-on;
  20                 regulator-boot-on;
  21                 vin-supply = <&reg_smarc_suppy>;
  22         };
  23
  24         reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "V_1V35_VCOREDIG_S5";
  27                 regulator-min-microvolt = <1350000>;
  28                 regulator-max-microvolt = <1350000>;
  29                 regulator-always-on;
  30                 regulator-boot-on;
  31                 vin-supply = <&reg_3p3v_s5>;
  32         };
  33
  34         reg_1p8v_s5: regulator-1p8v-s5 {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "V_1V8_S5";
  37                 regulator-min-microvolt = <1800000>;
  38                 regulator-max-microvolt = <1800000>;
  39                 regulator-always-on;
  40                 regulator-boot-on;
  41                 vin-supply = <&reg_3p3v_s5>;
  42         };
  43
  44         reg_3p3v_s0: regulator-3p3v-s0 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "V_3V3_S0";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49                 regulator-always-on;
  50                 regulator-boot-on;
  51                 vin-supply = <&reg_3p3v_s5>;
  52         };
  53
  54         reg_3p3v_s0: regulator-3p3v-s0 {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "V_3V3_S0";
  57                 regulator-min-microvolt = <3300000>;
  58                 regulator-max-microvolt = <3300000>;
  59                 regulator-always-on;
  60                 regulator-boot-on;
  61                 vin-supply = <&reg_3p3v_s5>;
  62         };
  63
  64         reg_3p3v_s5: regulator-3p3v-s5 {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "V_3V3_S5";
  67                 regulator-min-microvolt = <3300000>;
  68                 regulator-max-microvolt = <3300000>;
  69                 regulator-always-on;
  70                 regulator-boot-on;
  71                 vin-supply = <&reg_smarc_suppy>;
  72         };
  73
  74         reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
  75                 compatible = "regulator-fixed";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&pinctrl_lcdbklt_en>;
  78                 regulator-name = "LCD_BKLT_EN";
  79                 regulator-min-microvolt = <1800000>;
  80                 regulator-max-microvolt = <1800000>;
  81                 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
  86                 compatible = "regulator-fixed";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcdvdd_en>;
  89                 regulator-name = "LCD_VDD_EN";
  90                 regulator-min-microvolt = <1800000>;
  91                 regulator-max-microvolt = <1800000>;
  92                 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  93                 enable-active-high;
  94         };
  95
  96         reg_smarc_rtc: regulator-smarc-rtc {
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "V_IN_RTC_BATT";
  99                 regulator-min-microvolt = <3300000>;
 100                 regulator-max-microvolt = <3300000>;
 101                 regulator-always-on;
 102                 regulator-boot-on;
 103         };
 104
 105         /* Module supply range can be 3.00V ... 5.25V */
 106         reg_smarc_suppy: regulator-smarc-supply {
 107                 compatible = "regulator-fixed";
 108                 regulator-name = "V_IN_WIDE";
 109                 regulator-min-microvolt = <5000000>;
 110                 regulator-max-microvolt = <5000000>;
 111                 regulator-always-on;
 112                 regulator-boot-on;
 113         };
 114
 115         lcd: lcd {
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 compatible = "fsl,imx-parallel-display";
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&pinctrl_lcd>;
 121                 status = "disabled";
 122
 123                 port@0 {
 124                         reg = <0>;
 125
 126                         lcd_in: endpoint {
 127                         };
 128                 };
 129
 130                 port@1 {
 131                         reg = <1>;
 132
 133                         lcd_out: endpoint {
 134                         };
 135                 };
 136         };
 137
 138         lcd_backlight: lcd-backlight {
 139                 compatible = "pwm-backlight";
 140                 pwms = <&pwm4 0 5000000>;
 141                 pwm-names = "LCD_BKLT_PWM";
 142
 143                 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 144                 default-brightness-level = <4>;
 145
 146                 power-supply = <&reg_smarc_lcdbklt>;
 147                 status = "disabled";
 148         };
 149
 150         i2c_intern: i2c-gpio-intern {
 151                 compatible = "i2c-gpio";
 152                 pinctrl-names = "default";
 153                 pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
 154                 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 155                 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 156                 i2c-gpio,delay-us = <2>; /* ~100 kHz */
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159         };
 160
 161         i2c_lcd: i2c-gpio-lcd {
 162                 compatible = "i2c-gpio";
 163                 pinctrl-names = "default";
 164                 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
 165                 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 166                 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 167                 i2c-gpio,delay-us = <2>; /* ~100 kHz */
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 status = "disabld";
 171         };
 172
 173         i2c_cam: i2c-gpio-cam {
 174                 compatible = "i2c-gpio";
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
 177                 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 178                 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 179                 i2c-gpio,delay-us = <2>; /* ~100 kHz */
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 status = "disabld";
 183         };
 184 };
 185
 186 /* I2S0, I2S1 */
 187 &audmux {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_audmux>;
 190
 191         audmux_ssi1 {
 192                 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
 193                 fsl,port-config = <
 194                         (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
 195                          IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
 196                          IMX_AUDMUX_V2_PTCR_SYN    |
 197                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 198                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 199                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
 200                 >;
 201         };
 202
 203         audmux_adu3 {
 204                 fsl,audmux-port = <MX51_AUDMUX_PORT3>;
 205                 fsl,port-config = <
 206                         IMX_AUDMUX_V2_PTCR_SYN
 207                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
 208                 >;
 209         };
 210
 211         audmux_ssi2 {
 212                 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
 213                 fsl,port-config = <
 214                         (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
 215                          IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
 216                          IMX_AUDMUX_V2_PTCR_SYN    |
 217                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 218                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 219                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
 220                 >;
 221         };
 222
 223         audmux_adu4 {
 224                 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
 225                 fsl,port-config = <
 226                         IMX_AUDMUX_V2_PTCR_SYN
 227                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
 228                 >;
 229         };
 230 };
 231
 232 /* CAN0 */
 233 &can1 {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_flexcan1>;
 236 };
 237
 238 /* CAN1 */
 239 &can2 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_flexcan2>;
 242 };
 243
 244 /* SPI1 */
 245 &ecspi2 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_ecspi2>;
 248         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
 249                    <&gpio2 27 GPIO_ACTIVE_HIGH>;
 250 };
 251
 252 /* SPI0 */
 253 &ecspi4 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_ecspi4>;
 256         cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
 257                    <&gpio3 29 GPIO_ACTIVE_HIGH>;
 258         status = "okay";
 259
 260         /* default boot source: workaround #1 for errata ERR006282 */
 261         smarc_flash: spi-flash@0 {
 262                 compatible = "winbond,w25q16dw", "jedec,spi-nor";
 263                 reg = <0>;
 264                 spi-max-frequency = <20000000>;
 265         };
 266 };
 267
 268 /* GBE */
 269 &fec {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&pinctrl_enet>;
 272         phy-mode = "rgmii";
 273         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 274 };
 275
 276 &i2c_intern {
 277         pmic@8 {
 278                 compatible = "fsl,pfuze100";
 279                 reg = <0x08>;
 280
 281                 regulators {
 282                         reg_v_core_s0: sw1ab {
 283                                 regulator-name = "V_CORE_S0";
 284                                 regulator-min-microvolt = <300000>;
 285                                 regulator-max-microvolt = <1875000>;
 286                                 regulator-boot-on;
 287                                 regulator-always-on;
 288                         };
 289
 290                         reg_vddsoc_s0: sw1c {
 291                                 regulator-name = "V_VDDSOC_S0";
 292                                 regulator-min-microvolt = <300000>;
 293                                 regulator-max-microvolt = <1875000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         reg_3p15v_s0: sw2 {
 299                                 regulator-name = "V_3V15_S0";
 300                                 regulator-min-microvolt = <800000>;
 301                                 regulator-max-microvolt = <3300000>;
 302                                 regulator-boot-on;
 303                                 regulator-always-on;
 304                         };
 305
 306                         /* sw3a/b is used in dual mode, but driver does not
 307                          * support it. Although, there's no need to control
 308                          * DDR power - so just leaving dummy entries for sw3a
 309                          * and sw3b for now.
 310                          */
 311                         sw3a {
 312                                 regulator-min-microvolt = <400000>;
 313                                 regulator-max-microvolt = <1975000>;
 314                                 regulator-boot-on;
 315                                 regulator-always-on;
 316                         };
 317
 318                         sw3b {
 319                                 regulator-min-microvolt = <400000>;
 320                                 regulator-max-microvolt = <1975000>;
 321                                 regulator-boot-on;
 322                                 regulator-always-on;
 323                         };
 324
 325                         reg_1p8v_s0: sw4 {
 326                                 regulator-name = "V_1V8_S0";
 327                                 regulator-min-microvolt = <800000>;
 328                                 regulator-max-microvolt = <3300000>;
 329                                 regulator-boot-on;
 330                                 regulator-always-on;
 331                         };
 332
 333                         /* Regulator for USB */
 334                         reg_5p0v_s0: swbst {
 335                                 regulator-name = "V_5V0_S0";
 336                                 regulator-min-microvolt = <5000000>;
 337                                 regulator-max-microvolt = <5150000>;
 338                                 regulator-boot-on;
 339                         };
 340
 341                         reg_vsnvs: vsnvs {
 342                                 regulator-min-microvolt = <1000000>;
 343                                 regulator-max-microvolt = <3000000>;
 344                                 regulator-boot-on;
 345                                 regulator-always-on;
 346                         };
 347
 348                         reg_vrefddr: vrefddr {
 349                                 regulator-boot-on;
 350                                 regulator-always-on;
 351                         };
 352
 353                         /*
 354                          * Per schematics, of all VGEN's, only VGEN5 has some
 355                          * usage ... but even that - over DNI resistor
 356                          */
 357                         vgen1 {
 358                                 regulator-min-microvolt = <800000>;
 359                                 regulator-max-microvolt = <1550000>;
 360                         };
 361
 362                         vgen2 {
 363                                 regulator-min-microvolt = <800000>;
 364                                 regulator-max-microvolt = <1550000>;
 365                         };
 366
 367                         vgen3 {
 368                                 regulator-min-microvolt = <1800000>;
 369                                 regulator-max-microvolt = <3300000>;
 370                         };
 371
 372                         vgen4 {
 373                                 regulator-min-microvolt = <1800000>;
 374                                 regulator-max-microvolt = <3300000>;
 375                         };
 376
 377                         reg_2p5v_s0: vgen5 {
 378                                 regulator-name = "V_2V5_S0";
 379                                 regulator-min-microvolt = <1800000>;
 380                                 regulator-max-microvolt = <3300000>;
 381                         };
 382
 383                         vgen6 {
 384                                 regulator-min-microvolt = <1800000>;
 385                                 regulator-max-microvolt = <3300000>;
 386                         };
 387                 };
 388         };
 389 };
 390
 391 /* I2C_GP */
 392 &i2c1 {
 393         clock-frequency = <100000>;
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_i2c1>;
 396 };
 397
 398 /* HDMI_CTRL */
 399 &i2c2 {
 400         clock-frequency = <100000>;
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_i2c2>;
 403 };
 404
 405 /* I2C_PM */
 406 &i2c3 {
 407         clock-frequency = <100000>;
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_i2c3>;
 410         status = "okay";
 411
 412         smarc_eeprom: eeprom@50 {
 413                 compatible = "atmel,24c32";
 414                 reg = <0x50>;
 415                 pagesize = <32>;
 416         };
 417 };
 418
 419 &iomuxc {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
 422
 423         pinctrl_audmux: audmuxgrp {
 424                 fsl,pins = <
 425                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 426                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 427                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 428                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 429
 430                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 431                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 432                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 433                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 434
 435                         /* AUDIO MCLK */
 436                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2         0x000b0
 437                 >;
 438         };
 439
 440         pinctrl_ecspi2: ecspi2grp {
 441                 fsl,pins = <
 442                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 443                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 444                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 445
 446                         MX6QDL_PAD_EIM_RW__GPIO2_IO26  0x1b0b0 /* CS0 */
 447                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
 448                 >;
 449         };
 450
 451         pinctrl_ecspi4: ecspi4grp {
 452                 fsl,pins = <
 453                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 454                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 455                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 456
 457                         /* SPI_IMX_CS2# - connected to internal flash */
 458                         MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
 459                         /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
 460                         MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 461                 >;
 462         };
 463
 464         pinctrl_flexcan1: flexcan1grp {
 465                 fsl,pins = <
 466                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 467                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 468                 >;
 469         };
 470
 471         pinctrl_flexcan2: flexcan2grp {
 472                 fsl,pins = <
 473                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 474                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 475                 >;
 476         };
 477
 478         pinctrl_gpio: gpiogrp {
 479                 fsl,pins = <
 480                         MX6QDL_PAD_EIM_DA0__GPIO3_IO00  0x1b0b0 /* GPIO0 / CAM0_PWR# */
 481                         MX6QDL_PAD_EIM_DA1__GPIO3_IO01  0x1b0b0 /* GPIO1 / CAM1_PWR# */
 482                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02  0x1b0b0 /* GPIO2 / CAM0_RST# */
 483                         MX6QDL_PAD_EIM_DA3__GPIO3_IO03  0x1b0b0 /* GPIO3 / CAM1_RST# */
 484                         MX6QDL_PAD_EIM_DA4__GPIO3_IO04  0x1b0b0 /* GPIO4 / HDA_RST#  */
 485                         MX6QDL_PAD_EIM_DA5__GPIO3_IO05  0x1b0b0 /* GPIO5 / PWM_OUT   */
 486                         MX6QDL_PAD_EIM_DA6__GPIO3_IO06  0x1b0b0 /* GPIO6 / TACHIN    */
 487                         MX6QDL_PAD_EIM_DA7__GPIO3_IO07  0x1b0b0 /* GPIO7 / PCAM_FLD  */
 488                         MX6QDL_PAD_EIM_DA8__GPIO3_IO08  0x1b0b0 /* GPIO8 / CAN0_ERR# */
 489                         MX6QDL_PAD_EIM_DA9__GPIO3_IO09  0x1b0b0 /* GPIO9 / CAN1_ERR# */
 490                         MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10            */
 491                         MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11            */
 492                 >;
 493         };
 494
 495         pinctrl_enet: enetgrp {
 496                 fsl,pins = <
 497                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 498                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 499                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 500                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 501                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 502                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 503                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 504                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 505                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 506                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 507                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 508                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 509
 510                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 511                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 512                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 513                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b0b0 /* RST_GBE0_PHY# */
 514                 >;
 515         };
 516
 517         pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
 518                 fsl,pins = <
 519                         MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0 /* SCL */
 520                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
 521                 >;
 522         };
 523
 524         pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
 525                 fsl,pins = <
 526                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30  0x1b0b0 /* SCL */
 527                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
 528                 >;
 529         };
 530
 531         pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
 534                         MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
 535                 >;
 536         };
 537
 538         pinctrl_i2c1: i2c1grp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 541                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 542                 >;
 543         };
 544
 545         pinctrl_i2c2: i2c2grp {
 546                 fsl,pins = <
 547                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 548                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 549                 >;
 550         };
 551
 552         pinctrl_i2c3: i2c3grp {
 553                 fsl,pins = <
 554                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 555                         MX6QDL_PAD_GPIO_16__I2C3_SDA            0x4001b8b1
 556                 >;
 557         };
 558
 559         pinctrl_lcd: lcdgrp {
 560                 fsl,pins = <
 561                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00  0x100f1
 562                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01  0x100f1
 563                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02  0x100f1
 564                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03  0x100f1
 565                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04  0x100f1
 566                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05  0x100f1
 567                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06  0x100f1
 568                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07  0x100f1
 569                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08  0x100f1
 570                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09  0x100f1
 571                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
 572                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
 573                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
 574                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
 575                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
 576                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
 577                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
 578                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
 579                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
 580                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
 581                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
 582                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
 583                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
 584                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
 585
 586                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
 587                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f1 /* DE */
 588                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f1 /* HSYNC */
 589                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f1 /* VSYNC */
 590                 >;
 591         };
 592
 593         pinctrl_lcdbklt_en: lcdbkltengrp {
 594                 fsl,pins = <
 595                         MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
 596                 >;
 597         };
 598
 599         pinctrl_lcdvdd_en: lcdvddengrp {
 600                 fsl,pins = <
 601                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
 602                 >;
 603         };
 604
 605         pinctrl_mipi_csi: mipi-csigrp {
 606                 fsl,pins = <
 607                         MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
 608                 >;
 609         };
 610
 611         pinctrl_mgmt_gpios: mgmt-gpiosgrp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b0 /* LID#           */
 614                         MX6QDL_PAD_SD3_DAT7__GPIO6_IO17         0x1b0b0 /* SLEEP#         */
 615                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0 /* CHARGING#      */
 616                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* CHARGER_PRSNT# */
 617                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x1b0b0 /* CARRIER_STBY#  */
 618                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x1b0b0 /* BATLOW#        */
 619                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x1b0b0 /* TEST#          */
 620                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0 /* VDD_IO_SEL_D#  */
 621                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0 /* POWER_BTN#     */
 622                 >;
 623         };
 624
 625         pinctrl_pcie: pciegrp {
 626                 fsl,pins = <
 627                         MX6QDL_PAD_EIM_D18__GPIO3_IO18  0x1b0b0 /* PCI_A_PRSNT# */
 628                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A#  */
 629                         MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE#   */
 630                 >;
 631         };
 632
 633         pinctrl_pwm4: pwm4grp {
 634                 fsl,pins = <
 635                         MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
 636                 >;
 637         };
 638
 639         pinctrl_uart1: uart1grp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 642                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 643                         MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
 644                         MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
 645                 >;
 646         };
 647
 648         pinctrl_uart2: uart2grp {
 649                 fsl,pins = <
 650                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 651                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
 652                 >;
 653         };
 654
 655         pinctrl_uart4: uart4grp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
 658                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
 659                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
 660                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
 661                 >;
 662         };
 663
 664         pinctrl_uart5: uart5grp {
 665                 fsl,pins = <
 666                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
 667                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
 668                 >;
 669         };
 670
 671         pinctrl_usbotg: usbotggrp {
 672                 fsl,pins = <
 673                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
 674                         /* power, oc muxed but not used by the driver */
 675                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x1b0b0 /* USB power */
 676                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b0b0 /* USB OC */
 677                 >;
 678         };
 679
 680         pinctrl_usdhc3: usdhc3grp {
 681                 fsl,pins = <
 682                         MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
 683                         MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
 684                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 685                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 686                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 687                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 688
 689                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
 690                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
 691                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
 692                 >;
 693         };
 694
 695         pinctrl_usdhc4: usdhc4grp {
 696                 fsl,pins = <
 697                         MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
 698                         MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
 699                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
 700                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
 701                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
 702                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
 703                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
 704                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
 705                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
 706                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
 707                 >;
 708         };
 709
 710         pinctrl_wdog1: wdog1rp {
 711                 fsl,pins = <
 712                         MX6QDL_PAD_GPIO_9__WDOG1_B      0x1b0b0
 713                 >;
 714         };
 715 };
 716
 717 &mipi_csi {
 718         pinctrl-names = "default";
 719         pinctrl-0 = <&pinctrl_mipi_csi>;
 720 };
 721
 722 &pcie {
 723         pinctrl-names = "default";
 724         pinctrl-0 = <&pinctrl_pcie>;
 725         wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
 726         reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 727 };
 728
 729 /* LCD_BKLT_PWM */
 730 &pwm4 {
 731         pinctrl-names = "default";
 732         pinctrl-0 = <&pinctrl_pwm4>;
 733 };
 734
 735 &reg_arm {
 736         vin-supply = <&reg_v_core_s0>;
 737 };
 738
 739 &reg_pu {
 740         vin-supply = <&reg_vddsoc_s0>;
 741 };
 742
 743 &reg_soc {
 744         vin-supply = <&reg_vddsoc_s0>;
 745 };
 746
 747 /* SER0 */
 748 &uart1 {
 749         pinctrl-names = "default";
 750         pinctrl-0 = <&pinctrl_uart1>;
 751         uart-has-rtscts;
 752 };
 753
 754 /* SER1 */
 755 &uart2 {
 756         pinctrl-names = "default";
 757         pinctrl-0 = <&pinctrl_uart2>;
 758 };
 759
 760 /* SER2 */
 761 &uart4 {
 762         pinctrl-names = "default";
 763         pinctrl-0 = <&pinctrl_uart4>;
 764         uart-has-rtscts;
 765 };
 766
 767 /* SER3 */
 768 &uart5 {
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&pinctrl_uart5>;
 771 };
 772
 773 /* USB0 */
 774 &usbotg {
 775         /*
 776          * no 'imx6-usb-charger-detection'
 777          * since USB_OTG_CHD_B pin is not wired
 778          */
 779         pinctrl-names = "default";
 780         pinctrl-0 = <&pinctrl_usbotg>;
 781 };
 782
 783 /* USB1/2 via hub */
 784 &usbh1 {
 785         vbus-supply = <&reg_5p0v_s0>;
 786 };
 787
 788 /* SDIO */
 789 &usdhc3 {
 790         pinctrl-names = "default";
 791         pinctrl-0 = <&pinctrl_usdhc3>;
 792         cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 793         wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 794         no-1-8-v;
 795 };
 796
 797 /* SDMMC */
 798 &usdhc4 {
 799         /* Internal eMMC, optional on some boards */
 800         pinctrl-names = "default";
 801         pinctrl-0 = <&pinctrl_usdhc4>;
 802         bus-width = <8>;
 803         no-sdio;
 804         no-sd;
 805         non-removable;
 806         vmmc-supply = <&reg_3p3v_s0>;
 807         vqmmc-supply = <&reg_1p8v_s0>;
 808 };
 809
 810 &wdog1 {
 811         /* CPLD is feeded by watchdog (hardwired) */
 812         pinctrl-names = "default";
 813         pinctrl-0 = <&pinctrl_wdog1>;
 814         status = "okay";
 815 };