arch/arm/boot/dts/imx6qdl-icore.dtsi

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/input/input.h>
  45 #include <dt-bindings/sound/fsl-imx-audmux.h>
  46
  47 / {
  48         memory {
  49                 reg = <0x10000000 0x80000000>;
  50         };
  51
  52         backlight {
  53                 compatible = "pwm-backlight";
  54                 pwms = <&pwm3 0 100000>;
  55                 brightness-levels = <0 4 8 16 32 64 128 255>;
  56                 default-brightness-level = <7>;
  57         };
  58
  59         reg_1p8v: regulator-1p8v {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "1P8V";
  62                 regulator-min-microvolt = <1800000>;
  63                 regulator-max-microvolt = <1800000>;
  64                 regulator-boot-on;
  65                 regulator-always-on;
  66         };
  67
  68
  69         reg_2p5v: regulator-3p3v {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "2P5V";
  72                 regulator-min-microvolt = <2500000>;
  73                 regulator-max-microvolt = <2500000>;
  74                 regulator-boot-on;
  75                 regulator-always-on;
  76         };
  77
  78         reg_3p3v: regulator-3p3v {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "3P3V";
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83                 regulator-boot-on;
  84                 regulator-always-on;
  85         };
  86
  87         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "usb_h1_vbus";
  90                 regulator-min-microvolt = <5000000>;
  91                 regulator-max-microvolt = <5000000>;
  92                 regulator-boot-on;
  93                 regulator-always-on;
  94         };
  95
  96         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "usb_otg_vbus";
  99                 regulator-min-microvolt = <5000000>;
 100                 regulator-max-microvolt = <5000000>;
 101                 regulator-boot-on;
 102                 regulator-always-on;
 103         };
 104
 105         rmii_clk: clock-rmii-clk {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <25000000>;  /* 25MHz for example */
 109         };
 110
 111         sound {
 112                 compatible = "simple-audio-card";
 113                 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
 114                 simple-audio-card,format = "i2s";
 115                 simple-audio-card,bitclock-master = <&dailink_master>;
 116                 simple-audio-card,frame-master = <&dailink_master>;
 117                 simple-audio-card,widgets =
 118                         "Microphone", "Mic Jack",
 119                         "Headphone", "Headphone Jack",
 120                         "Line", "Line In Jack",
 121                         "Speaker", "Line Out Jack",
 122                         "Speaker", "Ext Spk";
 123                 simple-audio-card,routing =
 124                         "MIC_IN", "Mic Jack",
 125                         "Mic Jack", "Mic Bias",
 126                         "Headphone Jack", "HP_OUT";
 127
 128                 simple-audio-card,cpu {
 129                         sound-dai = <&ssi1>;
 130                 };
 131
 132                 dailink_master: simple-audio-card,codec {
 133                         sound-dai = <&sgtl5000>;
 134                 };
 135         };
 136 };
 137
 138 &audmux {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_audmux>;
 141         status = "okay";
 142
 143
 144         audmux_ssi1 {
 145                 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
 146                 fsl,port-config = <
 147                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 148                         IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
 149                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 150                         IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
 151                         IMX_AUDMUX_V2_PTCR_SYN)
 152                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
 153                 >;
 154         };
 155
 156         audmux_aud4 {
 157                 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
 158                 fsl,port-config = <
 159                         IMX_AUDMUX_V2_PTCR_SYN
 160                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
 161                 >;
 162         };
 163 };
 164
 165 &can1 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_flexcan1>;
 168         xceiver-supply = <&reg_3p3v>;
 169 };
 170
 171 &can2 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_flexcan2>;
 174         xceiver-supply = <&reg_3p3v>;
 175 };
 176
 177 &clks {
 178         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
 179         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 180 };
 181
 182 &fec {
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&pinctrl_enet>;
 185         phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 186         clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
 187         phy-mode = "rmii";
 188         status = "okay";
 189 };
 190
 191 &gpmi {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_gpmi_nand>;
 194         nand-on-flash-bbt;
 195         status = "okay";
 196 };
 197
 198 &i2c1 {
 199         clock-frequency = <100000>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_i2c1>;
 202         status = "okay";
 203 };
 204
 205 &i2c2 {
 206         clock-frequency = <100000>;
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_i2c2>;
 209         status = "okay";
 210 };
 211
 212 &i2c3 {
 213         clock-frequency = <100000>;
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&pinctrl_i2c3>;
 216         status = "okay";
 217
 218         sgtl5000: codec@a {
 219                 #sound-dai-cells = <0>;
 220                 compatible = "fsl,sgtl5000";
 221                 reg = <0x0a>;
 222                 clocks = <&clks IMX6QDL_CLK_CKO>;
 223                 VDDA-supply = <&reg_2p5v>;
 224                 VDDIO-supply = <&reg_3p3v>;
 225                 VDDD-supply = <&reg_1p8v>;
 226         };
 227 };
 228
 229 &pwm3 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_pwm3>;
 232         status = "okay";
 233 };
 234
 235 &ssi1 {
 236         fsl,mode = "i2s-slave";
 237         status = "okay";
 238 };
 239
 240 &uart4 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_uart4>;
 243         status = "okay";
 244 };
 245
 246 &usbh1 {
 247         vbus-supply = <&reg_usb_h1_vbus>;
 248         disable-over-current;
 249         status = "okay";
 250 };
 251
 252 &usbotg {
 253         vbus-supply = <&reg_usb_otg_vbus>;
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_usbotg>;
 256         disable-over-current;
 257         status = "okay";
 258 };
 259
 260 &usdhc1 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_usdhc1>;
 263         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 264         no-1-8-v;
 265         status = "okay";
 266 };
 267
 268 &iomuxc {
 269         pinctrl_audmux: audmux {
 270                 fsl,pins = <
 271                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 272                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 273                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 274                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 275                 >;
 276         };
 277
 278         pinctrl_enet: enetgrp {
 279                 fsl,pins = <
 280                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 281                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
 282                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 283                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 284                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 285                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 286                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 287                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 288                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 289                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 290                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 291                 >;
 292         };
 293
 294         pinctrl_flexcan1: flexcan1grp {
 295                 fsl,pins = <
 296                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 297                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 298                 >;
 299         };
 300
 301         pinctrl_flexcan2: flexcan2grp {
 302                 fsl,pins = <
 303                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 304                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 305                 >;
 306         };
 307
 308         pinctrl_gpmi_nand: gpmi-nand {
 309                 fsl,pins = <
 310                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 311                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 312                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 313                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 314                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 315                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 316                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 317                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 318                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 319                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 320                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 321                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 322                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 323                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 324                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 325                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 326                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 327                 >;
 328         };
 329
 330         pinctrl_i2c1: i2c1grp {
 331                 fsl,pins = <
 332                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 333                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 334                 >;
 335         };
 336
 337         pinctrl_i2c2: i2c2grp {
 338                 fsl,pins = <
 339                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 340                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 341                 >;
 342         };
 343
 344         pinctrl_i2c3: i2c3grp {
 345                 fsl,pins = <
 346                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 347                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 348                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 349                 >;
 350         };
 351
 352         pinctrl_uart4: uart4grp {
 353                 fsl,pins = <
 354                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 355                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 356                 >;
 357         };
 358
 359         pinctrl_pwm3: pwm3grp {
 360                 fsl,pins = <
 361                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 362                 >;
 363         };
 364
 365         pinctrl_usbotg: usbotggrp {
 366                 fsl,pins = <
 367                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 368                 >;
 369         };
 370
 371         pinctrl_usdhc1: usdhc1grp {
 372                 fsl,pins = <
 373                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 374                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
 375                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
 376                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
 377                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
 378                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 379                 >;
 380         };
 381 };