arch/arm/boot/dts/imx6qdl-icore.dtsi

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/input/input.h>
  45
  46 / {
  47         memory {
  48                 reg = <0x10000000 0x80000000>;
  49         };
  50
  51         reg_3p3v: regulator-3p3v {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "3P3V";
  54                 regulator-min-microvolt = <3300000>;
  55                 regulator-max-microvolt = <3300000>;
  56                 regulator-boot-on;
  57                 regulator-always-on;
  58         };
  59
  60         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "usb_h1_vbus";
  63                 regulator-min-microvolt = <5000000>;
  64                 regulator-max-microvolt = <5000000>;
  65                 regulator-boot-on;
  66                 regulator-always-on;
  67         };
  68
  69         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "usb_otg_vbus";
  72                 regulator-min-microvolt = <5000000>;
  73                 regulator-max-microvolt = <5000000>;
  74                 regulator-boot-on;
  75                 regulator-always-on;
  76         };
  77
  78         rmii_clk: clock-rmii-clk {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <25000000>;  /* 25MHz for example */
  82         };
  83 };
  84
  85 &can1 {
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_flexcan1>;
  88         xceiver-supply = <&reg_3p3v>;
  89 };
  90
  91 &can2 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_flexcan2>;
  94         xceiver-supply = <&reg_3p3v>;
  95 };
  96
  97 &clks {
  98         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
  99         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 100 };
 101
 102 &fec {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_enet>;
 105         phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 106         clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
 107         phy-mode = "rmii";
 108         status = "okay";
 109 };
 110
 111 &gpmi {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_gpmi_nand>;
 114         nand-on-flash-bbt;
 115         status = "okay";
 116 };
 117
 118 &i2c1 {
 119         clock-frequency = <100000>;
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_i2c1>;
 122         status = "okay";
 123 };
 124
 125 &i2c2 {
 126         clock-frequency = <100000>;
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_i2c2>;
 129         status = "okay";
 130 };
 131
 132 &i2c3 {
 133         clock-frequency = <100000>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_i2c3>;
 136         status = "okay";
 137 };
 138
 139 &uart4 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_uart4>;
 142         status = "okay";
 143 };
 144
 145 &usbh1 {
 146         vbus-supply = <&reg_usb_h1_vbus>;
 147         disable-over-current;
 148         status = "okay";
 149 };
 150
 151 &usbotg {
 152         vbus-supply = <&reg_usb_otg_vbus>;
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_usbotg>;
 155         disable-over-current;
 156         status = "okay";
 157 };
 158
 159 &usdhc1 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_usdhc1>;
 162         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 163         no-1-8-v;
 164         status = "okay";
 165 };
 166
 167 &iomuxc {
 168         pinctrl_enet: enetgrp {
 169                 fsl,pins = <
 170                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 171                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
 172                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 173                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 174                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 175                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 176                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 177                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 178                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 179                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 180                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 181                 >;
 182         };
 183
 184         pinctrl_flexcan1: flexcan1grp {
 185                 fsl,pins = <
 186                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 187                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 188                 >;
 189         };
 190
 191         pinctrl_flexcan2: flexcan2grp {
 192                 fsl,pins = <
 193                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 194                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 195                 >;
 196         };
 197
 198         pinctrl_gpmi_nand: gpmi-nand {
 199                 fsl,pins = <
 200                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 201                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 202                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 203                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 204                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 205                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 206                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 207                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 208                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 209                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 210                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 211                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 212                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 213                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 214                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 215                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 216                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 217                 >;
 218         };
 219
 220         pinctrl_i2c1: i2c1grp {
 221                 fsl,pins = <
 222                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 223                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 224                 >;
 225         };
 226
 227         pinctrl_i2c2: i2c2grp {
 228                 fsl,pins = <
 229                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 230                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 231                 >;
 232         };
 233
 234         pinctrl_i2c3: i2c3grp {
 235                 fsl,pins = <
 236                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 237                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 238                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 239                 >;
 240         };
 241
 242         pinctrl_uart4: uart4grp {
 243                 fsl,pins = <
 244                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 245                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 246                 >;
 247         };
 248
 249         pinctrl_usbotg: usbotggrp {
 250                 fsl,pins = <
 251                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 252                 >;
 253         };
 254
 255         pinctrl_usdhc1: usdhc1grp {
 256                 fsl,pins = <
 257                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 258                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
 259                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
 260                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
 261                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
 262                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 263                 >;
 264         };
 265 };