arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright (C) 2015 Amarula Solutions B.V.
   4  * Copyright (C) 2015 Engicam S.r.l.
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/clock/imx6qdl-clock.h>
   9 #include <dt-bindings/sound/fsl-imx-audmux.h>
  10
  11 / {
  12         memory@10000000 {
  13                 reg = <0x10000000 0x80000000>;
  14         };
  15
  16         reg_1p8v: regulator-1p8v {
  17                 compatible = "regulator-fixed";
  18                 regulator-name = "1P8V";
  19                 regulator-min-microvolt = <1800000>;
  20                 regulator-max-microvolt = <1800000>;
  21                 regulator-boot-on;
  22                 regulator-always-on;
  23         };
  24
  25         reg_2p5v: regulator-2p5v {
  26                 compatible = "regulator-fixed";
  27                 regulator-name = "2P5V";
  28                 regulator-min-microvolt = <2500000>;
  29                 regulator-max-microvolt = <2500000>;
  30                 regulator-boot-on;
  31                 regulator-always-on;
  32         };
  33
  34         reg_3p3v: regulator-3p3v {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "3P3V";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 regulator-boot-on;
  40                 regulator-always-on;
  41         };
  42
  43         reg_sd3_vmmc: regulator-sd3-vmmc {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "P3V3_SD3_SWITCHED";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48                 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
  49                 enable-active-high;
  50         };
  51
  52         reg_sd4_vmmc: regulator-sd4-vmmc {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "P3V3_SD4_SWITCHED";
  55                 regulator-min-microvolt = <3300000>;
  56                 regulator-max-microvolt = <3300000>;
  57                 regulator-boot-on;
  58                 regulator-always-on;
  59         };
  60
  61         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "usb_h1_vbus";
  64                 regulator-min-microvolt = <5000000>;
  65                 regulator-max-microvolt = <5000000>;
  66                 regulator-boot-on;
  67                 regulator-always-on;
  68         };
  69
  70         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "usb_otg_vbus";
  73                 regulator-min-microvolt = <5000000>;
  74                 regulator-max-microvolt = <5000000>;
  75                 regulator-boot-on;
  76                 regulator-always-on;
  77         };
  78
  79         usb_hub: usb-hub {
  80                 compatible = "smsc,usb3503a";
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_usbhub>;
  83                 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
  84                 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
  85                 clock-names = "refclk";
  86         };
  87
  88         sound {
  89                 compatible = "simple-audio-card";
  90                 simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
  91                 simple-audio-card,format = "i2s";
  92                 simple-audio-card,bitclock-master = <&dailink_master>;
  93                 simple-audio-card,frame-master = <&dailink_master>;
  94                 simple-audio-card,widgets =
  95                         "Microphone", "Mic Jack",
  96                         "Headphone", "Headphone Jack",
  97                         "Line", "Line In Jack",
  98                         "Speaker", "Line Out Jack",
  99                         "Speaker", "Ext Spk";
 100                 simple-audio-card,routing =
 101                         "MIC_IN", "Mic Jack",
 102                         "Mic Jack", "Mic Bias",
 103                         "Headphone Jack", "HP_OUT";
 104
 105                 simple-audio-card,cpu {
 106                         sound-dai = <&ssi1>;
 107                 };
 108
 109                 dailink_master: simple-audio-card,codec {
 110                         sound-dai = <&sgtl5000>;
 111                 };
 112         };
 113 };
 114
 115 &audmux {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_audmux>;
 118         status = "okay";
 119
 120         audmux_ssi1 {
 121                 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
 122                 fsl,port-config = <
 123                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 124                         IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
 125                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 126                         IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
 127                         IMX_AUDMUX_V2_PTCR_SYN)
 128                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
 129                 >;
 130         };
 131
 132         audmux_aud4 {
 133                 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
 134                 fsl,port-config = <
 135                         IMX_AUDMUX_V2_PTCR_SYN
 136                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
 137                 >;
 138         };
 139 };
 140
 141 &can1 {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_can1>;
 144         xceiver-supply = <&reg_3p3v>;
 145         status = "okay";
 146 };
 147
 148 &can2 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_can2>;
 151         xceiver-supply = <&reg_3p3v>;
 152         status = "okay";
 153 };
 154
 155 &clks {
 156         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
 157         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 158 };
 159
 160 &fec {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_enet>;
 163         phy-handle = <&eth_phy>;
 164         phy-mode = "rgmii";
 165         status = "okay";
 166
 167         mdio {
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170
 171                 eth_phy: ethernet-phy@0 {
 172                         reg = <0x0>;
 173                         rxc-skew-ps = <1140>;
 174                         txc-skew-ps = <1140>;
 175                         txen-skew-ps = <600>;
 176                         rxdv-skew-ps = <240>;
 177                         rxd0-skew-ps = <420>;
 178                         rxd1-skew-ps = <600>;
 179                         rxd2-skew-ps = <420>;
 180                         rxd3-skew-ps = <240>;
 181                         txd0-skew-ps = <60>;
 182                         txd1-skew-ps = <60>;
 183                         txd2-skew-ps = <60>;
 184                         txd3-skew-ps = <240>;
 185                 };
 186         };
 187 };
 188
 189 &i2c1 {
 190         clock-frequency = <100000>;
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_i2c1>;
 193         status = "okay";
 194 };
 195
 196 &i2c2 {
 197         clock-frequency = <100000>;
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_i2c2>;
 200         status = "okay";
 201 };
 202
 203 &i2c3 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_i2c3>;
 206         status = "okay";
 207
 208         sgtl5000: codec@a {
 209                 #sound-dai-cells = <0>;
 210                 compatible = "fsl,sgtl5000";
 211                 reg = <0x0a>;
 212                 clocks = <&clks IMX6QDL_CLK_CKO>;
 213                 VDDA-supply = <&reg_2p5v>;
 214                 VDDIO-supply = <&reg_3p3v>;
 215                 VDDD-supply = <&reg_1p8v>;
 216         };
 217 };
 218
 219 &pcie {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_pcie>;
 222         reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
 223         status = "okay";
 224 };
 225
 226 &ssi1 {
 227         fsl,mode = "i2s-slave";
 228         status = "okay";
 229 };
 230
 231 &uart4 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_uart4>;
 234         status = "okay";
 235 };
 236
 237 &usbh1 {
 238         vbus-supply = <&reg_usb_h1_vbus>;
 239         disable-over-current;
 240         clocks = <&clks IMX6QDL_CLK_USBOH3>;
 241         status = "okay";
 242 };
 243
 244 &usbotg {
 245         vbus-supply = <&reg_usb_otg_vbus>;
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_usbotg>;
 248         disable-over-current;
 249         status = "okay";
 250 };
 251
 252 &usdhc1 {
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_usdhc1>;
 255         no-1-8-v;
 256         status = "okay";
 257 };
 258
 259 &usdhc3 {
 260         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 261         pinctrl-0 = <&pinctrl_usdhc3>;
 262         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 263         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 264         vmcc-supply = <&reg_sd3_vmmc>;
 265         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 266         bus-witdh = <4>;
 267         no-1-8-v;
 268         status = "okay";
 269 };
 270
 271 &usdhc4 {
 272         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 273         pinctrl-0 = <&pinctrl_usdhc4>;
 274         pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
 275         pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
 276         vmcc-supply = <&reg_sd4_vmmc>;
 277         bus-witdh = <8>;
 278         no-1-8-v;
 279         non-removable;
 280         status = "okay";
 281 };
 282
 283 &iomuxc {
 284         pinctrl_audmux: audmuxgrp {
 285                 fsl,pins = <
 286                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 287                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 288                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 289                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 290                 >;
 291         };
 292
 293         pinctrl_enet: enetgrp {
 294                 fsl,pins = <
 295                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 296                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 297                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
 298                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
 299                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
 300                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
 301                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
 302                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 303                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 304                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 305                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 306                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 307                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 308                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 309                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 310                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 311                 >;
 312         };
 313
 314         pinctrl_can1: can1grp {
 315                 fsl,pins = <
 316                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 317                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 318                 >;
 319         };
 320
 321         pinctrl_can2: can2grp {
 322                 fsl,pins = <
 323                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 324                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 325                 >;
 326         };
 327
 328         pinctrl_i2c1: i2c1grp {
 329                 fsl,pins = <
 330                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 331                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 332                 >;
 333         };
 334
 335         pinctrl_i2c2: i2c2grp {
 336                 fsl,pins = <
 337                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 338                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 339                 >;
 340         };
 341
 342         pinctrl_i2c3: i2c3grp {
 343                 fsl,pins = <
 344                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 345                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 346                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 347                 >;
 348         };
 349
 350         pinctrl_pcie: pciegrp {
 351                 fsl,pins = <
 352                         MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059  /* PCIe Reset */
 353                 >;
 354         };
 355
 356         pinctrl_uart4: uart4grp {
 357                 fsl,pins = <
 358                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 359                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 360                 >;
 361         };
 362
 363         pinctrl_usbhub: usbhubgrp {
 364                 fsl,pins = <
 365                         MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059  /* HUB USB Reset */
 366                 >;
 367         };
 368
 369         pinctrl_usbotg: usbotggrp {
 370                 fsl,pins = <
 371                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 372                 >;
 373         };
 374
 375         pinctrl_usdhc1: usdhc1grp {
 376                 fsl,pins = <
 377                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 378                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 379                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 380                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 381                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 382                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 383                 >;
 384         };
 385
 386         pinctrl_usdhc3: usdhc3grp {
 387                 fsl,pins = <
 388                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 389                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
 390                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
 391                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
 392                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
 393                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
 394                         MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059  /* CD */
 395                         MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059  /* PWR */
 396                 >;
 397         };
 398
 399         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 400                 fsl,pins = <
 401                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1
 402                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1
 403                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
 404                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
 405                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
 406                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
 407                 >;
 408         };
 409
 410         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 411                 fsl,pins = <
 412                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9
 413                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9
 414                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
 415                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
 416                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
 417                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
 418                 >;
 419         };
 420
 421         pinctrl_usdhc4: usdhc4grp {
 422                 fsl,pins = <
 423                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
 424                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
 425                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
 426                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
 427                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
 428                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
 429                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
 430                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
 431                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
 432                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
 433                 >;
 434         };
 435
 436         pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
 437                 fsl,pins = <
 438                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1
 439                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1
 440                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
 441                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
 442                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
 443                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
 444                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
 445                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
 446                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
 447                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
 448                 >;
 449         };
 450
 451         pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
 452                 fsl,pins = <
 453                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9
 454                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9
 455                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
 456                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
 457                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
 458                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
 459                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
 460                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
 461                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
 462                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
 463                 >;
 464         };
 465 };