arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi

   1 /*
   2  * Copyright (C) 2015 Amarula Solutions B.V.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/clock/imx6qdl-clock.h>
  44
  45 / {
  46         memory {
  47                 reg = <0x10000000 0x80000000>;
  48         };
  49
  50         reg_1p8v: regulator-1p8v {
  51                 compatible = "regulator-fixed";
  52                 regulator-name = "1P8V";
  53                 regulator-min-microvolt = <1800000>;
  54                 regulator-max-microvolt = <1800000>;
  55                 regulator-boot-on;
  56                 regulator-always-on;
  57         };
  58
  59         reg_2p5v: regulator-2p5v {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "2P5V";
  62                 regulator-min-microvolt = <2500000>;
  63                 regulator-max-microvolt = <2500000>;
  64                 regulator-boot-on;
  65                 regulator-always-on;
  66         };
  67
  68         reg_3p3v: regulator-3p3v {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "3P3V";
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 regulator-boot-on;
  74                 regulator-always-on;
  75         };
  76
  77         reg_sd3_vmmc: regulator-sd3-vmmc {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "P3V3_SD3_SWITCHED";
  80                 regulator-min-microvolt = <3300000>;
  81                 regulator-max-microvolt = <3300000>;
  82                 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
  83                 enable-active-high;
  84         };
  85
  86         reg_sd4_vmmc: regulator-sd4-vmmc {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "P3V3_SD4_SWITCHED";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 regulator-boot-on;
  92                 regulator-always-on;
  93         };
  94
  95         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "usb_h1_vbus";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 regulator-boot-on;
 101                 regulator-always-on;
 102         };
 103
 104         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 105                 compatible = "regulator-fixed";
 106                 regulator-name = "usb_otg_vbus";
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109                 regulator-boot-on;
 110                 regulator-always-on;
 111         };
 112
 113         usb_hub: usb-hub {
 114                 compatible = "smsc,usb3503a";
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&pinctrl_usbhub>;
 117                 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 118                 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
 119                 clock-names = "refclk";
 120         };
 121 };
 122
 123 &clks {
 124         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
 125         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 126 };
 127
 128 &audmux {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_audmux>;
 131         status = "okay";
 132 };
 133
 134 &fec {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_enet>;
 137         phy-handle = <&eth_phy>;
 138         phy-mode = "rgmii";
 139         status = "okay";
 140
 141         mdio {
 142                 eth_phy: ethernet-phy {
 143                         rxc-skew-ps = <1140>;
 144                         txc-skew-ps = <1140>;
 145                         txen-skew-ps = <600>;
 146                         rxdv-skew-ps = <240>;
 147                         rxd0-skew-ps = <420>;
 148                         rxd1-skew-ps = <600>;
 149                         rxd2-skew-ps = <420>;
 150                         rxd3-skew-ps = <240>;
 151                         txd0-skew-ps = <60>;
 152                         txd1-skew-ps = <60>;
 153                         txd2-skew-ps = <60>;
 154                         txd3-skew-ps = <240>;
 155                 };
 156         };
 157 };
 158
 159 &i2c1 {
 160         clock-frequency = <100000>;
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_i2c1>;
 163         status = "okay";
 164 };
 165
 166 &i2c2 {
 167         clock-frequency = <100000>;
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_i2c2>;
 170         status = "okay";
 171 };
 172
 173 &i2c3 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_i2c3>;
 176         status = "okay";
 177 };
 178
 179 &pcie {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_pcie>;
 182         reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
 183         status = "okay";
 184 };
 185
 186 &ssi1 {
 187         status = "okay";
 188 };
 189
 190 &uart4 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_uart4>;
 193         status = "okay";
 194 };
 195
 196 &usbh1 {
 197         vbus-supply = <&reg_usb_h1_vbus>;
 198         disable-over-current;
 199         clocks = <&clks IMX6QDL_CLK_USBOH3>;
 200         status = "okay";
 201 };
 202
 203 &usbotg {
 204         vbus-supply = <&reg_usb_otg_vbus>;
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_usbotg>;
 207         disable-over-current;
 208         status = "okay";
 209 };
 210
 211 &usdhc1 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_usdhc1>;
 214         no-1-8-v;
 215         status = "okay";
 216 };
 217
 218 &usdhc3 {
 219         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 220         pinctrl-0 = <&pinctrl_usdhc3>;
 221         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 222         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 223         vmcc-supply = <&reg_sd3_vmmc>;
 224         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 225         bus-witdh = <4>;
 226         no-1-8-v;
 227         status = "okay";
 228 };
 229
 230 &usdhc4 {
 231         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 232         pinctrl-0 = <&pinctrl_usdhc4>;
 233         pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
 234         pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
 235         vmcc-supply = <&reg_sd4_vmmc>;
 236         bus-witdh = <8>;
 237         no-1-8-v;
 238         non-removable;
 239         status = "okay";
 240 };
 241
 242 &iomuxc {
 243         pinctrl_audmux: audmux {
 244                 fsl,pins = <
 245                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 246                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 247                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 248                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 249                 >;
 250         };
 251
 252         pinctrl_enet: enetgrp {
 253                 fsl,pins = <
 254                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 255                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 256                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
 257                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
 258                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
 259                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
 260                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
 261                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 262                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 263                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 264                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 265                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 266                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 267                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 268                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 269                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 270                 >;
 271         };
 272
 273         pinctrl_i2c1: i2c1grp {
 274                 fsl,pins = <
 275                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 276                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 277                 >;
 278         };
 279
 280         pinctrl_i2c2: i2c2grp {
 281                 fsl,pins = <
 282                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 283                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 284                 >;
 285         };
 286
 287         pinctrl_i2c3: i2c3grp {
 288                 fsl,pins = <
 289                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 290                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 291                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 292                 >;
 293         };
 294
 295         pinctrl_pcie: pciegrp {
 296                 fsl,pins = <
 297                         MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059  /* PCIe Reset */
 298                 >;
 299         };
 300
 301         pinctrl_uart4: uart4grp {
 302                 fsl,pins = <
 303                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 304                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 305                 >;
 306         };
 307
 308         pinctrl_usbhub: usbhubgrp {
 309                 fsl,pins = <
 310                         MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059  /* HUB USB Reset */
 311                 >;
 312         };
 313
 314         pinctrl_usbotg: usbotggrp {
 315                 fsl,pins = <
 316                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 317                 >;
 318         };
 319
 320         pinctrl_usdhc1: usdhc1grp {
 321                 fsl,pins = <
 322                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 323                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 324                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 325                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 326                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 327                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 328                 >;
 329         };
 330
 331         pinctrl_usdhc3: usdhc3grp {
 332                 fsl,pins = <
 333                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 334                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
 335                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
 336                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
 337                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
 338                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
 339                         MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059  /* CD */
 340                         MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059  /* PWR */
 341                 >;
 342         };
 343
 344         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 345                 fsl,pins = <
 346                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1
 347                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1
 348                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
 349                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
 350                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
 351                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
 352                 >;
 353         };
 354
 355         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 356                 fsl,pins = <
 357                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9
 358                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9
 359                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
 360                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
 361                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
 362                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
 363                 >;
 364         };
 365
 366         pinctrl_usdhc4: usdhc4grp {
 367                 fsl,pins = <
 368                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
 369                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
 370                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
 371                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
 372                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
 373                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
 374                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
 375                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
 376                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
 377                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
 378                 >;
 379         };
 380
 381         pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
 382                 fsl,pins = <
 383                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1
 384                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1
 385                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
 386                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
 387                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
 388                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
 389                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
 390                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
 391                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
 392                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
 393                 >;
 394         };
 395
 396         pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
 397                 fsl,pins = <
 398                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9
 399                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9
 400                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
 401                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
 402                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
 403                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
 404                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
 405                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
 406                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
 407                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
 408                 >;
 409         };
 410 };