arch/arm/boot/dts/imx6qdl-gw54xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/sound/fsl-imx-audmux.h>
  14
  15 / {
  16         /* these are used by bootloader for disabling nodes */
  17         aliases {
  18                 led0 = &led0;
  19                 led1 = &led1;
  20                 led2 = &led2;
  21                 nand = &gpmi;
  22                 ssi0 = &ssi1;
  23                 usb0 = &usbh1;
  24                 usb1 = &usbotg;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttymxc1,115200";
  29         };
  30
  31         backlight {
  32                 compatible = "pwm-backlight";
  33                 pwms = <&pwm4 0 5000000>;
  34                 brightness-levels = <0 4 8 16 32 64 128 255>;
  35                 default-brightness-level = <7>;
  36         };
  37
  38         leds {
  39                 compatible = "gpio-leds";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_gpio_leds>;
  42
  43                 led0: user1 {
  44                         label = "user1";
  45                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  46                         default-state = "on";
  47                         linux,default-trigger = "heartbeat";
  48                 };
  49
  50                 led1: user2 {
  51                         label = "user2";
  52                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  53                         default-state = "off";
  54                 };
  55
  56                 led2: user3 {
  57                         label = "user3";
  58                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  59                         default-state = "off";
  60                 };
  61         };
  62
  63         memory@10000000 {
  64                 device_type = "memory";
  65                 reg = <0x10000000 0x40000000>;
  66         };
  67
  68         pps {
  69                 compatible = "pps-gpio";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&pinctrl_pps>;
  72                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  73                 status = "okay";
  74         };
  75
  76         regulators {
  77                 compatible = "simple-bus";
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 reg_1p0v: regulator@0 {
  82                         compatible = "regulator-fixed";
  83                         reg = <0>;
  84                         regulator-name = "1P0V";
  85                         regulator-min-microvolt = <1000000>;
  86                         regulator-max-microvolt = <1000000>;
  87                         regulator-always-on;
  88                 };
  89
  90                 reg_3p3v: regulator@1 {
  91                         compatible = "regulator-fixed";
  92                         reg = <1>;
  93                         regulator-name = "3P3V";
  94                         regulator-min-microvolt = <3300000>;
  95                         regulator-max-microvolt = <3300000>;
  96                         regulator-always-on;
  97                 };
  98
  99                 reg_usb_h1_vbus: regulator@2 {
 100                         compatible = "regulator-fixed";
 101                         reg = <2>;
 102                         regulator-name = "usb_h1_vbus";
 103                         regulator-min-microvolt = <5000000>;
 104                         regulator-max-microvolt = <5000000>;
 105                         regulator-always-on;
 106                 };
 107
 108                 reg_usb_otg_vbus: regulator@3 {
 109                         compatible = "regulator-fixed";
 110                         reg = <3>;
 111                         regulator-name = "usb_otg_vbus";
 112                         regulator-min-microvolt = <5000000>;
 113                         regulator-max-microvolt = <5000000>;
 114                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 115                         enable-active-high;
 116                 };
 117         };
 118
 119         sound-analog {
 120                 compatible = "fsl,imx6q-ventana-sgtl5000",
 121                              "fsl,imx-audio-sgtl5000";
 122                 model = "sgtl5000-audio";
 123                 ssi-controller = <&ssi1>;
 124                 audio-codec = <&sgtl5000>;
 125                 audio-routing =
 126                         "MIC_IN", "Mic Jack",
 127                         "Mic Jack", "Mic Bias",
 128                         "Headphone Jack", "HP_OUT";
 129                 mux-int-port = <1>;
 130                 mux-ext-port = <4>;
 131         };
 132 };
 133
 134 &audmux {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
 137         status = "okay";
 138
 139         ssi2 {
 140                 fsl,audmux-port = <1>;
 141                 fsl,port-config = <
 142                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 143                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 144                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 145                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 146                         IMX_AUDMUX_V2_PTCR_SYN)
 147                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 148                 >;
 149         };
 150
 151         aud5 {
 152                 fsl,audmux-port = <4>;
 153                 fsl,port-config = <
 154                         IMX_AUDMUX_V2_PTCR_SYN
 155                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
 156         };
 157 };
 158
 159 &can1 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_flexcan1>;
 162         status = "okay";
 163 };
 164
 165 &clks {
 166         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 167                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 168         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 169                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 170 };
 171
 172 &ecspi2 {
 173         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_ecspi2>;
 176         status = "okay";
 177 };
 178
 179 &fec {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_enet>;
 182         phy-mode = "rgmii-id";
 183         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 184         status = "okay";
 185 };
 186
 187 &gpmi {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_gpmi_nand>;
 190         status = "okay";
 191 };
 192
 193 &hdmi {
 194         ddc-i2c-bus = <&i2c3>;
 195         status = "okay";
 196 };
 197
 198 &i2c1 {
 199         clock-frequency = <100000>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_i2c1>;
 202         status = "okay";
 203
 204         eeprom1: eeprom@50 {
 205                 compatible = "atmel,24c02";
 206                 reg = <0x50>;
 207                 pagesize = <16>;
 208         };
 209
 210         eeprom2: eeprom@51 {
 211                 compatible = "atmel,24c02";
 212                 reg = <0x51>;
 213                 pagesize = <16>;
 214         };
 215
 216         eeprom3: eeprom@52 {
 217                 compatible = "atmel,24c02";
 218                 reg = <0x52>;
 219                 pagesize = <16>;
 220         };
 221
 222         eeprom4: eeprom@53 {
 223                 compatible = "atmel,24c02";
 224                 reg = <0x53>;
 225                 pagesize = <16>;
 226         };
 227
 228         gpio: pca9555@23 {
 229                 compatible = "nxp,pca9555";
 230                 reg = <0x23>;
 231                 gpio-controller;
 232                 #gpio-cells = <2>;
 233         };
 234
 235         rtc: ds1672@68 {
 236                 compatible = "dallas,ds1672";
 237                 reg = <0x68>;
 238         };
 239 };
 240
 241 &i2c2 {
 242         clock-frequency = <100000>;
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_i2c2>;
 245         status = "okay";
 246
 247         pmic: pfuze100@8 {
 248                 compatible = "fsl,pfuze100";
 249                 reg = <0x08>;
 250
 251                 regulators {
 252                         sw1a_reg: sw1ab {
 253                                 regulator-min-microvolt = <300000>;
 254                                 regulator-max-microvolt = <1875000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                                 regulator-ramp-delay = <6250>;
 258                         };
 259
 260                         sw1c_reg: sw1c {
 261                                 regulator-min-microvolt = <300000>;
 262                                 regulator-max-microvolt = <1875000>;
 263                                 regulator-boot-on;
 264                                 regulator-always-on;
 265                                 regulator-ramp-delay = <6250>;
 266                         };
 267
 268                         sw2_reg: sw2 {
 269                                 regulator-min-microvolt = <800000>;
 270                                 regulator-max-microvolt = <3950000>;
 271                                 regulator-boot-on;
 272                                 regulator-always-on;
 273                         };
 274
 275                         sw3a_reg: sw3a {
 276                                 regulator-min-microvolt = <400000>;
 277                                 regulator-max-microvolt = <1975000>;
 278                                 regulator-boot-on;
 279                                 regulator-always-on;
 280                         };
 281
 282                         sw3b_reg: sw3b {
 283                                 regulator-min-microvolt = <400000>;
 284                                 regulator-max-microvolt = <1975000>;
 285                                 regulator-boot-on;
 286                                 regulator-always-on;
 287                         };
 288
 289                         sw4_reg: sw4 {
 290                                 regulator-min-microvolt = <800000>;
 291                                 regulator-max-microvolt = <3300000>;
 292                         };
 293
 294                         swbst_reg: swbst {
 295                                 regulator-min-microvolt = <5000000>;
 296                                 regulator-max-microvolt = <5150000>;
 297                                 regulator-boot-on;
 298                                 regulator-always-on;
 299                         };
 300
 301                         snvs_reg: vsnvs {
 302                                 regulator-min-microvolt = <1000000>;
 303                                 regulator-max-microvolt = <3000000>;
 304                                 regulator-boot-on;
 305                                 regulator-always-on;
 306                         };
 307
 308                         vref_reg: vrefddr {
 309                                 regulator-boot-on;
 310                                 regulator-always-on;
 311                         };
 312
 313                         vgen1_reg: vgen1 {
 314                                 regulator-min-microvolt = <800000>;
 315                                 regulator-max-microvolt = <1550000>;
 316                         };
 317
 318                         vgen2_reg: vgen2 {
 319                                 regulator-min-microvolt = <800000>;
 320                                 regulator-max-microvolt = <1550000>;
 321                         };
 322
 323                         vgen3_reg: vgen3 {
 324                                 regulator-min-microvolt = <1800000>;
 325                                 regulator-max-microvolt = <3300000>;
 326                         };
 327
 328                         vgen4_reg: vgen4 {
 329                                 regulator-min-microvolt = <1800000>;
 330                                 regulator-max-microvolt = <3300000>;
 331                                 regulator-always-on;
 332                         };
 333
 334                         vgen5_reg: vgen5 {
 335                                 regulator-min-microvolt = <1800000>;
 336                                 regulator-max-microvolt = <3300000>;
 337                                 regulator-always-on;
 338                         };
 339
 340                         vgen6_reg: vgen6 {
 341                                 regulator-min-microvolt = <1800000>;
 342                                 regulator-max-microvolt = <3300000>;
 343                                 regulator-always-on;
 344                         };
 345                 };
 346         };
 347 };
 348
 349 &i2c3 {
 350         clock-frequency = <100000>;
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_i2c3>;
 353         status = "okay";
 354
 355         sgtl5000: audio-codec@a {
 356                 compatible = "fsl,sgtl5000";
 357                 reg = <0x0a>;
 358                 clocks = <&clks IMX6QDL_CLK_CKO>;
 359                 VDDA-supply = <&sw4_reg>;
 360                 VDDIO-supply = <&reg_3p3v>;
 361         };
 362
 363         touchscreen: egalax_ts@4 {
 364                 compatible = "eeti,egalax_ts";
 365                 reg = <0x04>;
 366                 interrupt-parent = <&gpio7>;
 367                 interrupts = <12 2>;
 368                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 369         };
 370 };
 371
 372 &ldb {
 373         status = "okay";
 374
 375         lvds-channel@0 {
 376                 fsl,data-mapping = "spwg";
 377                 fsl,data-width = <18>;
 378                 status = "okay";
 379
 380                 display-timings {
 381                         native-mode = <&timing0>;
 382                         timing0: hsd100pxn1 {
 383                                 clock-frequency = <65000000>;
 384                                 hactive = <1024>;
 385                                 vactive = <768>;
 386                                 hback-porch = <220>;
 387                                 hfront-porch = <40>;
 388                                 vback-porch = <21>;
 389                                 vfront-porch = <7>;
 390                                 hsync-len = <60>;
 391                                 vsync-len = <10>;
 392                         };
 393                 };
 394         };
 395 };
 396
 397 &pcie {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_pcie>;
 400         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 401         status = "okay";
 402 };
 403
 404 &pwm1 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 407         status = "disabled";
 408 };
 409
 410 &pwm2 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 413         status = "disabled";
 414 };
 415
 416 &pwm3 {
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 419         status = "disabled";
 420 };
 421
 422 &pwm4 {
 423         pinctrl-names = "default", "state_dio";
 424         pinctrl-0 = <&pinctrl_pwm4_backlight>;
 425         pinctrl-1 = <&pinctrl_pwm4_dio>;
 426         status = "okay";
 427 };
 428
 429 &ssi1 {
 430         status = "okay";
 431 };
 432
 433 &ssi2 {
 434         status = "okay";
 435 };
 436
 437 &uart1 {
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&pinctrl_uart1>;
 440         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 441         status = "okay";
 442 };
 443
 444 &uart2 {
 445         pinctrl-names = "default";
 446         pinctrl-0 = <&pinctrl_uart2>;
 447         status = "okay";
 448 };
 449
 450 &uart5 {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_uart5>;
 453         status = "okay";
 454 };
 455
 456 &usbotg {
 457         vbus-supply = <&reg_usb_otg_vbus>;
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_usbotg>;
 460         disable-over-current;
 461         status = "okay";
 462 };
 463
 464 &usbh1 {
 465         vbus-supply = <&reg_usb_h1_vbus>;
 466         status = "okay";
 467 };
 468
 469 &usdhc3 {
 470         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 471         pinctrl-0 = <&pinctrl_usdhc3>;
 472         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 473         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 474         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 475         vmmc-supply = <&reg_3p3v>;
 476         no-1-8-v; /* firmware will remove if board revision supports */
 477         status = "okay";
 478 };
 479
 480 &wdog1 {
 481         status = "disabled";
 482 };
 483
 484 &wdog2 {
 485         pinctrl-names = "default";
 486         pinctrl-0 = <&pinctrl_wdog>;
 487         fsl,ext-reset-output;
 488         status = "okay";
 489 };
 490
 491 &iomuxc {
 492         pinctrl_audmux: audmuxgrp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 495                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 496                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 497                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 498                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 499                         MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
 500                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 501                         MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
 502                 >;
 503         };
 504
 505         pinctrl_enet: enetgrp {
 506                 fsl,pins = <
 507                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 508                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 509                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 510                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 511                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 512                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 513                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 514                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 515                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 516                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 517                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 518                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 519                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 520                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 521                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 522                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 523                 >;
 524         };
 525
 526         pinctrl_ecspi2: escpi2grp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 529                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 530                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 531                         MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 532                 >;
 533         };
 534
 535         pinctrl_flexcan1: flexcan1grp {
 536                 fsl,pins = <
 537                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 538                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 539                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 540                 >;
 541         };
 542
 543         pinctrl_gpio_leds: gpioledsgrp {
 544                 fsl,pins = <
 545                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 546                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 547                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 548                 >;
 549         };
 550
 551         pinctrl_gpmi_nand: gpminandgrp {
 552                 fsl,pins = <
 553                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 554                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 555                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 556                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 557                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 558                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 559                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 560                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 561                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 562                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 563                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 564                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 565                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 566                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 567                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 568                 >;
 569         };
 570
 571         pinctrl_i2c1: i2c1grp {
 572                 fsl,pins = <
 573                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 574                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 575                 >;
 576         };
 577
 578         pinctrl_i2c2: i2c2grp {
 579                 fsl,pins = <
 580                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 581                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 582                 >;
 583         };
 584
 585         pinctrl_i2c3: i2c3grp {
 586                 fsl,pins = <
 587                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 588                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 589                 >;
 590         };
 591
 592         pinctrl_pcie: pciegrp {
 593                 fsl,pins = <
 594                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
 595                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
 596                 >;
 597         };
 598
 599         pinctrl_pps: ppsgrp {
 600                 fsl,pins = <
 601                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 602                 >;
 603         };
 604
 605         pinctrl_pwm1: pwm1grp {
 606                 fsl,pins = <
 607                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 608                 >;
 609         };
 610
 611         pinctrl_pwm2: pwm2grp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 614                 >;
 615         };
 616
 617         pinctrl_pwm3: pwm3grp {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 620                 >;
 621         };
 622
 623         pinctrl_pwm4_backlight: pwm4grpbacklight {
 624                 fsl,pins = <
 625                         /* LVDS_PWM J6.5 */
 626                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 627                 >;
 628         };
 629
 630         pinctrl_pwm4_dio: pwm4grpdio {
 631                 fsl,pins = <
 632                         /* DIO3 J16.4 */
 633                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 634                 >;
 635         };
 636
 637         pinctrl_uart1: uart1grp {
 638                 fsl,pins = <
 639                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 640                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 641                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 642                 >;
 643         };
 644
 645         pinctrl_uart2: uart2grp {
 646                 fsl,pins = <
 647                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 648                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 649                 >;
 650         };
 651
 652         pinctrl_uart5: uart5grp {
 653                 fsl,pins = <
 654                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 655                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 656                 >;
 657         };
 658
 659         pinctrl_usbotg: usbotggrp {
 660                 fsl,pins = <
 661                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 662                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 663                 >;
 664         };
 665
 666         pinctrl_usdhc3: usdhc3grp {
 667                 fsl,pins = <
 668                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 669                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 670                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 671                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 672                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 673                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 674                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 675                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 676                 >;
 677         };
 678
 679         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 682                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 683                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 684                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 685                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 686                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 687                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 688                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 689                 >;
 690         };
 691
 692         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 693                 fsl,pins = <
 694                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 695                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 696                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 697                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 698                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 699                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 700                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 701                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 702                 >;
 703         };
 704
 705         pinctrl_wdog: wdoggrp {
 706                 fsl,pins = <
 707                         MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 708                 >;
 709         };
 710 };