Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qdl-dfi-fs700-m60.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3
4 / {
5         regulators {
6                 compatible = "simple-bus";
7                 #address-cells = <1>;
8                 #size-cells = <0>;
9
10                 dummy_reg: regulator@0 {
11                         compatible = "regulator-fixed";
12                         reg = <0>;
13                         regulator-name = "dummy-supply";
14                 };
15
16                 reg_usb_otg_vbus: regulator@1 {
17                         compatible = "regulator-fixed";
18                         reg = <1>;
19                         regulator-name = "usb_otg_vbus";
20                         regulator-min-microvolt = <5000000>;
21                         regulator-max-microvolt = <5000000>;
22                         gpio = <&gpio3 22 0>;
23                         enable-active-high;
24                 };
25         };
26
27         chosen {
28                 stdout-path = &uart1;
29         };
30 };
31
32 &ecspi3 {
33         cs-gpios = <&gpio4 24 0>;
34         pinctrl-names = "default";
35         pinctrl-0 = <&pinctrl_ecspi3>;
36         status = "okay";
37
38         flash: m25p80@0 {
39                 #address-cells = <1>;
40                 #size-cells = <1>;
41                 compatible = "sst,sst25vf040b", "jedec,spi-nor";
42                 spi-max-frequency = <20000000>;
43                 reg = <0>;
44         };
45 };
46
47 &fec {
48         pinctrl-names = "default";
49         pinctrl-0 = <&pinctrl_enet>;
50         status = "okay";
51         phy-mode = "rgmii";
52 };
53
54 &iomuxc {
55         pinctrl-names = "default";
56         pinctrl-0 = <&pinctrl_hog>;
57
58         imx6qdl-dfi-fs700-m60 {
59                 pinctrl_hog: hoggrp {
60                         fsl,pins = <
61                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
62                                 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */
63                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */
64                                 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
65                         >;
66                 };
67
68                 pinctrl_enet: enetgrp {
69                         fsl,pins = <
70                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
71                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
72                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
73                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
74                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
75                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
76                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
77                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
78                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
79                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
80                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
81                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
82                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
83                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
84                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
85                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
86                         >;
87                 };
88
89                 pinctrl_i2c2: i2c2grp {
90                         fsl,pins = <
91                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
92                                 MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
93                         >;
94                 };
95
96                 pinctrl_uart1: uart1grp {
97                         fsl,pins = <
98                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
99                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
100                         >;
101                 };
102
103                 pinctrl_usbotg: usbotggrp {
104                         fsl,pins = <
105                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
106                         >;
107                 };
108
109                 pinctrl_usdhc2: usdhc2grp {
110                         fsl,pins = <
111                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
112                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
113                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
114                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
115                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
116                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
117                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */
118                         >;
119                 };
120
121                 pinctrl_usdhc3: usdhc3grp {
122                         fsl,pins = <
123                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
124                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
125                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
126                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
127                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
128                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
129                         >;
130                 };
131
132                 pinctrl_usdhc4: usdhc4grp {
133                         fsl,pins = <
134                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
135                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
136                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
137                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
138                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
139                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
140                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
141                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
142                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
143                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
144                         >;
145                 };
146
147                 pinctrl_ecspi3: ecspi3grp {
148                         fsl,pins = <
149                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
150                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
151                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
152                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
153                         >;
154                 };
155         };
156 };
157
158 &i2c2 {
159         pinctrl-names = "default";
160         pinctrl-0 = <&pinctrl_i2c2>;
161         status = "okay";
162 };
163
164 &uart1 {
165         pinctrl-names = "default";
166         pinctrl-0 = <&pinctrl_uart1>;
167         status = "okay";
168 };
169
170 &usbh1 {
171         status = "okay";
172 };
173
174 &usbotg {
175         vbus-supply = <&reg_usb_otg_vbus>;
176         pinctrl-names = "default";
177         pinctrl-0 = <&pinctrl_usbotg>;
178         disable-over-current;
179         dr_mode = "host";
180         status = "okay";
181 };
182
183 &usdhc2 { /* module slot */
184         pinctrl-names = "default";
185         pinctrl-0 = <&pinctrl_usdhc2>;
186         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
187         status = "okay";
188 };
189
190 &usdhc3 { /* baseboard slot */
191         pinctrl-names = "default";
192         pinctrl-0 = <&pinctrl_usdhc3>;
193 };
194
195 &usdhc4 { /* eMMC */
196         pinctrl-names = "default";
197         pinctrl-0 = <&pinctrl_usdhc4>;
198         bus-width = <8>;
199         non-removable;
200         status = "okay";
201 };