arch/arm/boot/dts/imx6qdl-colibri.dtsi

   1 /*
   2  * Copyright 2014-2016 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Colibri iMX6DL/S Module";
  48         compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
  49
  50         backlight: backlight {
  51                 compatible = "pwm-backlight";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  54                 pwms = <&pwm3 0 5000000>;
  55                 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
  56                 status = "disabled";
  57         };
  58
  59         reg_module_3v3: regulator-module-3v3 {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "+V3.3";
  62                 regulator-min-microvolt = <3300000>;
  63                 regulator-max-microvolt = <3300000>;
  64                 regulator-always-on;
  65         };
  66
  67         reg_module_3v3_audio: regulator-module-3v3-audio {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "+V3.3_AUDIO";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_usb_host_vbus: regulator-usb-host-vbus {
  76                 compatible = "regulator-fixed";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
  79                 regulator-name = "usb_host_vbus";
  80                 regulator-min-microvolt = <5000000>;
  81                 regulator-max-microvolt = <5000000>;
  82                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
  83                 status = "disabled";
  84         };
  85
  86         sound {
  87                 compatible = "fsl,imx-audio-sgtl5000";
  88                 model = "imx6dl-colibri-sgtl5000";
  89                 ssi-controller = <&ssi1>;
  90                 audio-codec = <&codec>;
  91                 audio-routing =
  92                         "Headphone Jack", "HP_OUT",
  93                         "LINE_IN", "Line In Jack",
  94                         "MIC_IN", "Mic Jack",
  95                         "Mic Jack", "Mic Bias";
  96                 mux-int-port = <1>;
  97                 mux-ext-port = <5>;
  98         };
  99
 100         /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
 101         sound_spdif: sound-spdif {
 102                 compatible = "fsl,imx-audio-spdif";
 103                 model = "imx-spdif";
 104                 spdif-controller = <&spdif>;
 105                 spdif-in;
 106                 spdif-out;
 107                 status = "disabled";
 108         };
 109 };
 110
 111 &audmux {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
 114         status = "okay";
 115 };
 116
 117 /* Optional on SODIMM 55/63 */
 118 &can1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_flexcan1>;
 121         status = "disabled";
 122 };
 123
 124 /* Optional on SODIMM 178/188 */
 125 &can2 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_flexcan2>;
 128         status = "disabled";
 129 };
 130
 131 /* Colibri SSP */
 132 &ecspi4 {
 133         cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_ecspi4>;
 136         status = "disabled";
 137 };
 138
 139 &fec {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_enet>;
 142         phy-mode = "rmii";
 143         status = "okay";
 144 };
 145
 146 &hdmi {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 149         status = "disabled";
 150 };
 151
 152 /*
 153  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 154  * touch screen controller
 155  */
 156 &i2c2 {
 157         clock-frequency = <100000>;
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_i2c2>;
 160         status = "okay";
 161
 162         pmic: pfuze100@8 {
 163                 compatible = "fsl,pfuze100";
 164                 reg = <0x08>;
 165
 166                 regulators {
 167                         sw1a_reg: sw1ab {
 168                                 regulator-min-microvolt = <300000>;
 169                                 regulator-max-microvolt = <1875000>;
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                                 regulator-ramp-delay = <6250>;
 173                         };
 174
 175                         sw1c_reg: sw1c {
 176                                 regulator-min-microvolt = <300000>;
 177                                 regulator-max-microvolt = <1875000>;
 178                                 regulator-boot-on;
 179                                 regulator-always-on;
 180                                 regulator-ramp-delay = <6250>;
 181                         };
 182
 183                         sw3a_reg: sw3a {
 184                                 regulator-min-microvolt = <400000>;
 185                                 regulator-max-microvolt = <1975000>;
 186                                 regulator-boot-on;
 187                                 regulator-always-on;
 188                         };
 189
 190                         swbst_reg: swbst {
 191                                 regulator-min-microvolt = <5000000>;
 192                                 regulator-max-microvolt = <5150000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         snvs_reg: vsnvs {
 198                                 regulator-min-microvolt = <1000000>;
 199                                 regulator-max-microvolt = <3000000>;
 200                                 regulator-boot-on;
 201                                 regulator-always-on;
 202                         };
 203
 204                         vref_reg: vrefddr {
 205                                 regulator-boot-on;
 206                                 regulator-always-on;
 207                         };
 208
 209                         /* vgen1: unused */
 210
 211                         vgen2_reg: vgen2 {
 212                                 regulator-min-microvolt = <800000>;
 213                                 regulator-max-microvolt = <1550000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         /* vgen3: unused */
 219
 220                         vgen4_reg: vgen4 {
 221                                 regulator-min-microvolt = <1800000>;
 222                                 regulator-max-microvolt = <1800000>;
 223                                 regulator-boot-on;
 224                                 regulator-always-on;
 225                         };
 226
 227                         vgen5_reg: vgen5 {
 228                                 regulator-min-microvolt = <1800000>;
 229                                 regulator-max-microvolt = <3300000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         vgen6_reg: vgen6 {
 235                                 regulator-min-microvolt = <1800000>;
 236                                 regulator-max-microvolt = <3300000>;
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240                 };
 241         };
 242
 243         codec: sgtl5000@a {
 244                 compatible = "fsl,sgtl5000";
 245                 reg = <0x0a>;
 246                 clocks = <&clks IMX6QDL_CLK_CKO>;
 247                 VDDA-supply = <&reg_module_3v3_audio>;
 248                 VDDIO-supply = <&reg_module_3v3>;
 249                 VDDD-supply = <&vgen4_reg>;
 250                 lrclk-strength = <3>;
 251         };
 252
 253         /* STMPE811 touch screen controller */
 254         stmpe811@41 {
 255                 compatible = "st,stmpe811";
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&pinctrl_touch_int>;
 258                 reg = <0x41>;
 259                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 260                 interrupt-parent = <&gpio6>;
 261                 interrupt-controller;
 262                 id = <0>;
 263                 blocks = <0x5>;
 264                 irq-trigger = <0x1>;
 265                 /* 3.25 MHz ADC clock speed */
 266                 st,adc-freq = <1>;
 267                 /* 12-bit ADC */
 268                 st,mod-12b = <1>;
 269                 /* internal ADC reference */
 270                 st,ref-sel = <0>;
 271                 /* ADC converstion time: 80 clocks */
 272                 st,sample-time = <4>;
 273
 274                 stmpe_touchscreen {
 275                         compatible = "st,stmpe-ts";
 276                         /* 8 sample average control */
 277                         st,ave-ctrl = <3>;
 278                         /* 7 length fractional part in z */
 279                         st,fraction-z = <7>;
 280                         /*
 281                          * 50 mA typical 80 mA max touchscreen drivers
 282                          * current limit value
 283                          */
 284                         st,i-drive = <1>;
 285                         /* 1 ms panel driver settling time */
 286                         st,settling = <3>;
 287                         /* 5 ms touch detect interrupt delay */
 288                         st,touch-det-delay = <5>;
 289                 };
 290
 291                 stmpe_adc {
 292                         compatible = "st,stmpe-adc";
 293                         /* forbid to use ADC channels 3-0 (touch) */
 294                         st,norequest-mask = <0x0F>;
 295                 };
 296         };
 297 };
 298
 299 /*
 300  * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 301  */
 302 &i2c3 {
 303         clock-frequency = <100000>;
 304         pinctrl-names = "default", "recovery";
 305         pinctrl-0 = <&pinctrl_i2c3>;
 306         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 307         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 308         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 309         status = "disabled";
 310 };
 311
 312 /* Colibri PWM<B> */
 313 &pwm1 {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_pwm1>;
 316         status = "disabled";
 317 };
 318
 319 /* Colibri PWM<D> */
 320 &pwm2 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_pwm2>;
 323         status = "disabled";
 324 };
 325
 326 /* Colibri PWM<A> */
 327 &pwm3 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_pwm3>;
 330         status = "disabled";
 331 };
 332
 333 /* Colibri PWM<C> */
 334 &pwm4 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_pwm4>;
 337         status = "disabled";
 338 };
 339
 340 /* Optional S/PDIF out on SODIMM 137 */
 341 &spdif {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_spdif>;
 344         status = "disabled";
 345 };
 346
 347 &ssi1 {
 348         status = "okay";
 349 };
 350
 351 /* Colibri UART_A */
 352 &uart1 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 355         fsl,dte-mode;
 356         uart-has-rtscts;
 357         status = "disabled";
 358 };
 359
 360 /* Colibri UART_B */
 361 &uart2 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_uart2_dte>;
 364         fsl,dte-mode;
 365         uart-has-rtscts;
 366         status = "disabled";
 367 };
 368
 369 /* Colibri UART_C */
 370 &uart3 {
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&pinctrl_uart3_dte>;
 373         fsl,dte-mode;
 374         status = "disabled";
 375 };
 376
 377 &usbotg {
 378         pinctrl-names = "default";
 379         disable-over-current;
 380         dr_mode = "peripheral";
 381         status = "disabled";
 382 };
 383
 384 /* Colibri MMC */
 385 &usdhc1 {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
 388         cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
 389         disable-wp;
 390         vqmmc-supply = <&reg_module_3v3>;
 391         bus-width = <4>;
 392         no-1-8-v;
 393         status = "disabled";
 394 };
 395
 396 /* eMMC */
 397 &usdhc3 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_usdhc3>;
 400         vqmmc-supply = <&reg_module_3v3>;
 401         bus-width = <8>;
 402         no-1-8-v;
 403         non-removable;
 404         status = "okay";
 405 };
 406
 407 &weim {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
 410                      &pinctrl_weim_cs1   &pinctrl_weim_cs2
 411                      &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
 412         #address-cells = <2>;
 413         #size-cells = <1>;
 414         status = "disabled";
 415 };
 416
 417 &iomuxc {
 418         pinctrl_audmux: audmuxgrp {
 419                 fsl,pins = <
 420                         MX6QDL_PAD_KEY_COL0__AUD5_TXC   0x130b0
 421                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD   0x130b0
 422                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS  0x130b0
 423                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD   0x130b0
 424                         /* SGTL5000 sys_mclk */
 425                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x000b0
 426                 >;
 427         };
 428
 429         pinctrl_cam_mclk: cammclkgrp {
 430                 fsl,pins = <
 431                         /* Parallel Camera CAM sys_mclk */
 432                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 433                 >;
 434         };
 435
 436         pinctrl_ecspi4: ecspi4grp {
 437                 fsl,pins = <
 438                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 439                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 440                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 441                         /* SPI CS */
 442                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x000b1
 443                 >;
 444         };
 445
 446         pinctrl_enet: enetgrp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 449                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 450                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 451                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 452                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 453                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 454                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 455                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 456                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 457                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
 458                 >;
 459         };
 460
 461         pinctrl_flexcan1: flexcan1grp {
 462                 fsl,pins = <
 463                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 464                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 465                 >;
 466         };
 467
 468         pinctrl_flexcan2: flexcan2grp {
 469                 fsl,pins = <
 470                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 471                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 472                 >;
 473         };
 474
 475         pinctrl_gpio_bl_on: gpioblon {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0
 478                 >;
 479         };
 480
 481         pinctrl_gpio_keys: gpiokeys {
 482                 fsl,pins = <
 483                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x130b0
 484                 >;
 485         };
 486
 487         pinctrl_hdmi_ddc: hdmiddcgrp {
 488                 fsl,pins = <
 489                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 490                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 491                 >;
 492         };
 493
 494         pinctrl_i2c2: i2c2grp {
 495                 fsl,pins = <
 496                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 497                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 498                 >;
 499         };
 500
 501         pinctrl_i2c3: i2c3grp {
 502                 fsl,pins = <
 503                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 504                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 505                 >;
 506         };
 507
 508         pinctrl_i2c3_recovery: i2c3recoverygrp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
 511                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
 512                 >;
 513         };
 514
 515         pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
 516                 fsl,pins = <
 517                         MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12    0xb0b1
 518                         MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13    0xb0b1
 519                         MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14    0xb0b1
 520                         MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15    0xb0b1
 521                         MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16    0xb0b1
 522                         MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17    0xb0b1
 523                         MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18    0xb0b1
 524                         MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19    0xb0b1
 525                         MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK    0xb0b1
 526                         MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC     0xb0b1
 527                         MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC     0xb0b1
 528                         /* Disable PWM pins on camera interface */
 529                         MX6QDL_PAD_SD4_DAT1__GPIO2_IO09         0x40
 530                         MX6QDL_PAD_GPIO_1__GPIO1_IO01           0x40
 531                 >;
 532         };
 533
 534         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 535                 fsl,pins = <
 536                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0xa1
 537                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0xa1
 538                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0xa1
 539                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0xa1
 540                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0xa1
 541                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0xa1
 542                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0xa1
 543                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0xa1
 544                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0xa1
 545                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0xa1
 546                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0xa1
 547                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0xa1
 548                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0xa1
 549                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0xa1
 550                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0xa1
 551                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0xa1
 552                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0xa1
 553                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0xa1
 554                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0xa1
 555                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0xa1
 556                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0xa1
 557                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0xa1
 558                 >;
 559         };
 560
 561         pinctrl_mic_gnd: gpiomicgnd {
 562                 fsl,pins = <
 563                         /* Controls Mic GND, PU or '1' pull Mic GND to GND */
 564                         MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
 565                 >;
 566         };
 567
 568         pinctrl_mmc_cd: gpiommccd {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
 571                 >;
 572         };
 573
 574         pinctrl_pwm1: pwm1grp {
 575                 fsl,pins = <
 576                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b1
 577                 >;
 578         };
 579
 580         pinctrl_pwm2: pwm2grp {
 581                 fsl,pins = <
 582                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 583                         MX6QDL_PAD_EIM_A21__GPIO2_IO17  0x00040
 584                 >;
 585         };
 586
 587         pinctrl_pwm3: pwm3grp {
 588                 fsl,pins = <
 589                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b1
 590                         MX6QDL_PAD_EIM_A22__GPIO2_IO16  0x00040
 591                 >;
 592         };
 593
 594         pinctrl_pwm4: pwm4grp {
 595                 fsl,pins = <
 596                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT   0x1b0b1
 597                 >;
 598         };
 599
 600         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 601                 fsl,pins = <
 602                         /* USBH_EN */
 603                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x0f058
 604                 >;
 605         };
 606
 607         pinctrl_spdif: spdifgrp {
 608                 fsl,pins = <
 609                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 610                 >;
 611         };
 612
 613         pinctrl_touch_int: gpiotouchintgrp {
 614                 fsl,pins = <
 615                         /* STMPE811 interrupt */
 616                         MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
 617                 >;
 618         };
 619
 620         pinctrl_uart1_dce: uart1dcegrp {
 621                 fsl,pins = <
 622                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 623                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 624                 >;
 625         };
 626
 627         /* DTE mode */
 628         pinctrl_uart1_dte: uart1dtegrp {
 629                 fsl,pins = <
 630                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 631                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 632                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 633                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 634                 >;
 635         };
 636
 637         /* Additional DTR, DSR, DCD */
 638         pinctrl_uart1_ctrl: uart1ctrlgrp {
 639                 fsl,pins = <
 640                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 641                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 642                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 643                 >;
 644         };
 645
 646         pinctrl_uart2_dte: uart2dtegrp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 649                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 650                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 651                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 652                 >;
 653         };
 654
 655         pinctrl_uart3_dte: uart3dtegrp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_SD4_CLK__UART3_TX_DATA       0x1b0b1
 658                         MX6QDL_PAD_SD4_CMD__UART3_RX_DATA       0x1b0b1
 659                 >;
 660         };
 661
 662         pinctrl_usbc_det: usbcdetgrp {
 663                 fsl,pins = <
 664                         /* USBC_DET */
 665                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 666                         /* USBC_DET_EN */
 667                         MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26     0x0f058
 668                         /* USBC_DET_OVERWRITE */
 669                         MX6QDL_PAD_RGMII_RXC__GPIO6_IO30        0x0f058
 670                 >;
 671         };
 672
 673         pinctrl_usdhc1: usdhc1grp {
 674                 fsl,pins = <
 675                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 676                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 677                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 678                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 679                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 680                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 681                 >;
 682         };
 683
 684         pinctrl_usdhc3: usdhc3grp {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 687                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 688                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 689                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 690                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 691                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 692                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 693                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 694                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 695                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 696                         /* eMMC reset */
 697                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x17059
 698                 >;
 699         };
 700
 701         pinctrl_weim_cs0: weimcs0grp {
 702                 fsl,pins = <
 703                         /* nEXT_CS0 */
 704                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 705                 >;
 706         };
 707
 708         pinctrl_weim_cs1: weimcs1grp {
 709                 fsl,pins = <
 710                         /* nEXT_CS1 */
 711                         MX6QDL_PAD_EIM_CS1__EIM_CS1_B   0xb0b1
 712                 >;
 713         };
 714
 715         pinctrl_weim_cs2: weimcs2grp {
 716                 fsl,pins = <
 717                         /* nEXT_CS2 */
 718                         MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0xb0b1
 719                 >;
 720         };
 721
 722         pinctrl_weim_sram: weimsramgrp {
 723                 fsl,pins = <
 724                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 725                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 726                         /* Data */
 727                         MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00     0x1b0b0
 728                         MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01       0x1b0b0
 729                         MX6QDL_PAD_CSI0_DAT4__EIM_DATA02        0x1b0b0
 730                         MX6QDL_PAD_CSI0_DAT5__EIM_DATA03        0x1b0b0
 731                         MX6QDL_PAD_CSI0_DAT6__EIM_DATA04        0x1b0b0
 732                         MX6QDL_PAD_CSI0_DAT7__EIM_DATA05        0x1b0b0
 733                         MX6QDL_PAD_CSI0_DAT8__EIM_DATA06        0x1b0b0
 734                         MX6QDL_PAD_CSI0_DAT9__EIM_DATA07        0x1b0b0
 735                         MX6QDL_PAD_CSI0_DAT12__EIM_DATA08       0x1b0b0
 736                         MX6QDL_PAD_CSI0_DAT13__EIM_DATA09       0x1b0b0
 737                         MX6QDL_PAD_CSI0_DAT14__EIM_DATA10       0x1b0b0
 738                         MX6QDL_PAD_CSI0_DAT15__EIM_DATA11       0x1b0b0
 739                         MX6QDL_PAD_CSI0_DAT16__EIM_DATA12       0x1b0b0
 740                         MX6QDL_PAD_CSI0_DAT17__EIM_DATA13       0x1b0b0
 741                         MX6QDL_PAD_CSI0_DAT18__EIM_DATA14       0x1b0b0
 742                         MX6QDL_PAD_CSI0_DAT19__EIM_DATA15       0x1b0b0
 743                         /* Address */
 744                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 745                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 746                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 747                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 748                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 749                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 750                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 751                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 752                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 753                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 754                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 755                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 756                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 757                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 758                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 759                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 760                 >;
 761         };
 762
 763         pinctrl_weim_rdnwr: weimrdnwr {
 764                 fsl,pins = <
 765                         MX6QDL_PAD_SD2_CLK__GPIO1_IO10          0x0040
 766                         MX6QDL_PAD_RGMII_TD3__GPIO6_IO23        0x130b0
 767                 >;
 768         };
 769
 770         pinctrl_weim_npwe: weimnpwe {
 771                 fsl,pins = <
 772                         MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x0040
 773                         MX6QDL_PAD_RGMII_TD2__GPIO6_IO22        0x130b0
 774                 >;
 775         };
 776
 777         /* ADDRESS[16:18] [25] used as GPIO */
 778         pinctrl_weim_gpio_1: weimgpio-1 {
 779                 fsl,pins = <
 780                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 781                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 782                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 783                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 784                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 785                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 786                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 787                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 788                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 789                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 790                 >;
 791         };
 792
 793         /* ADDRESS[19:24] used as GPIO */
 794         pinctrl_weim_gpio_2: weimgpio-2 {
 795                 fsl,pins = <
 796                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 797                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 798                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 799                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 800                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 801                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 802                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 803                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 804                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 805                 >;
 806         };
 807
 808         /* DATA[16:31] used as GPIO */
 809         pinctrl_weim_gpio_3: weimgpio-3 {
 810                 fsl,pins = <
 811                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x1b0b0
 812                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x1b0b0
 813                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0
 814                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 815                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0
 816                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 817                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0
 818                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x1b0b0
 819                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
 820                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 821                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x1b0b0
 822                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x1b0b0
 823                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
 824                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0
 825                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 826                 >;
 827         };
 828
 829         /* DQM[0:3] used as GPIO */
 830         pinctrl_weim_gpio_4: weimgpio-4 {
 831                 fsl,pins = <
 832                         MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x1b0b0
 833                         MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x1b0b0
 834                         MX6QDL_PAD_SD2_DAT2__GPIO1_IO13         0x1b0b0
 835                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b0
 836                 >;
 837         };
 838
 839         /* RDY used as GPIO */
 840         pinctrl_weim_gpio_5: weimgpio-5 {
 841                 fsl,pins = <
 842                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b0
 843                 >;
 844         };
 845
 846         /* ADDRESS[16] DATA[30] used as GPIO */
 847         pinctrl_weim_gpio_6: weimgpio-6 {
 848                 fsl,pins = <
 849                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 850                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0
 851                 >;
 852         };
 853 };