arch/arm/boot/dts/imx6qdl-apf6.dtsi

   1 /*
   2  * Copyright 2015 Armadeus Systems
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/interrupt-controller/irq.h>
  50
  51 &fec {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_enet>;
  54         phy-mode = "rgmii-id";
  55         phy-reset-duration = <10>;
  56         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  57         status = "okay";
  58 };
  59
  60 /* Bluetooth */
  61 &uart2 {
  62         pinctrl-names = "default";
  63         pinctrl-0 = <&pinctrl_uart2>;
  64         status = "okay";
  65 };
  66
  67 /* Wi-Fi */
  68 &usdhc1 {
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_usdhc1>;
  71         non-removable;
  72         status = "okay";
  73
  74         #address-cells = <1>;
  75         #size-cells = <0>;
  76         wlcore: wlcore@2 {
  77                 compatible = "ti,wl1271";
  78                 reg = <2>;
  79                 interrupt-parent = <&gpio2>;
  80                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
  81                 ref-clock-frequency = <38400000>;
  82                 tcxo-clock-frequency = <38400000>;
  83         };
  84 };
  85
  86 /* eMMC */
  87 &usdhc3 {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_usdhc3>;
  90         bus-width = <8>;
  91         no-1-8-v;
  92         non-removable;
  93         status = "okay";
  94 };
  95
  96 &iomuxc {
  97         apf6 {
  98                 pinctrl_enet: enetgrp {
  99                         fsl,pins = <
 100                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
 101                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 102                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 103                                 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x130b0
 104                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x130b0
 105                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 106                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 107                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 108                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 109                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 110                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 111                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x13030
 112                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 113                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 114                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1f030
 115                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1f030
 116                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 117                         >;
 118                 };
 119
 120                 pinctrl_uart2: uart2grp {
 121                         fsl,pins = <
 122                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b0
 123                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b0
 124                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b0
 125                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b0
 126                                 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x130b0 /* BT_EN */
 127                         >;
 128                 };
 129
 130                 pinctrl_usdhc1: usdhc1grp {
 131                         fsl,pins = <
 132                                 MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17059
 133                                 MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10059
 134                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17059
 135                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17059
 136                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17059
 137                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17059
 138                                 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
 139                                 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
 140                         >;
 141                 };
 142
 143                 pinctrl_usdhc3: usdhc3grp {
 144                         fsl,pins = <
 145                                 MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 146                                 MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 147                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 148                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 149                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 150                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 151                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 152                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 153                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 154                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 155                         >;
 156                 };
 157         };
 158 };