arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 device_type = "memory";
  53                 reg = <0x10000000 0>;
  54         };
  55
  56         backlight: backlight {
  57                 compatible = "pwm-backlight";
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  60                 pwms = <&pwm4 0 5000000>;
  61                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  62                 status = "disabled";
  63         };
  64
  65         reg_module_3v3: regulator-module-3v3 {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "+V3.3";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-always-on;
  71         };
  72
  73         reg_module_3v3_audio: regulator-module-3v3-audio {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "+V3.3_AUDIO";
  76                 regulator-min-microvolt = <3300000>;
  77                 regulator-max-microvolt = <3300000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  82                 compatible = "regulator-fixed";
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  85                 regulator-name = "usb_otg_vbus";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  89                 enable-active-high;
  90                 status = "disabled";
  91         };
  92
  93         /* on module USB hub */
  94         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
  95                 compatible = "regulator-fixed";
  96                 pinctrl-names = "default";
  97                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
  98                 regulator-name = "usb_host_vbus_hub";
  99                 regulator-min-microvolt = <5000000>;
 100                 regulator-max-microvolt = <5000000>;
 101                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 102                 startup-delay-us = <2000>;
 103                 enable-active-high;
 104                 status = "okay";
 105         };
 106
 107         reg_usb_host_vbus: regulator-usb-host-vbus {
 108                 compatible = "regulator-fixed";
 109                 pinctrl-names = "default";
 110                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 111                 regulator-name = "usb_host_vbus";
 112                 regulator-min-microvolt = <5000000>;
 113                 regulator-max-microvolt = <5000000>;
 114                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 115                 enable-active-high;
 116                 vin-supply = <&reg_usb_host_vbus_hub>;
 117                 status = "disabled";
 118         };
 119
 120         sound {
 121                 compatible = "fsl,imx-audio-sgtl5000";
 122                 model = "imx6q-apalis-sgtl5000";
 123                 ssi-controller = <&ssi1>;
 124                 audio-codec = <&codec>;
 125                 audio-routing =
 126                         "LINE_IN", "Line In Jack",
 127                         "MIC_IN", "Mic Jack",
 128                         "Mic Jack", "Mic Bias",
 129                         "Headphone Jack", "HP_OUT";
 130                 mux-int-port = <1>;
 131                 mux-ext-port = <4>;
 132         };
 133
 134         sound_spdif: sound-spdif {
 135                 compatible = "fsl,imx-audio-spdif";
 136                 model = "imx-spdif";
 137                 spdif-controller = <&spdif>;
 138                 spdif-in;
 139                 spdif-out;
 140                 status = "disabled";
 141         };
 142 };
 143
 144 &audmux {
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_audmux>;
 147         status = "okay";
 148 };
 149
 150 &can1 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_flexcan1>;
 153         status = "disabled";
 154 };
 155
 156 &can2 {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_flexcan2>;
 159         status = "disabled";
 160 };
 161
 162 /* Apalis SPI1 */
 163 &ecspi1 {
 164         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_ecspi1>;
 167         status = "disabled";
 168 };
 169
 170 /* Apalis SPI2 */
 171 &ecspi2 {
 172         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_ecspi2>;
 175         status = "disabled";
 176 };
 177
 178 &fec {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_enet>;
 181         phy-mode = "rgmii";
 182         phy-handle = <&ethphy>;
 183         phy-reset-duration = <10>;
 184         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 185         status = "okay";
 186
 187         mdio {
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190
 191                 ethphy: ethernet-phy@7 {
 192                         interrupt-parent = <&gpio1>;
 193                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 194                         reg = <7>;
 195                 };
 196         };
 197 };
 198
 199 &hdmi {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 202         status = "disabled";
 203 };
 204
 205 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 206 &i2c1 {
 207         clock-frequency = <100000>;
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pinctrl_i2c1>;
 210         status = "disabled";
 211 };
 212
 213 /*
 214  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 215  * touch screen controller
 216  */
 217 &i2c2 {
 218         clock-frequency = <100000>;
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_i2c2>;
 221         status = "okay";
 222
 223         pmic: pfuze100@8 {
 224                 compatible = "fsl,pfuze100";
 225                 reg = <0x08>;
 226
 227                 regulators {
 228                         sw1a_reg: sw1ab {
 229                                 regulator-min-microvolt = <300000>;
 230                                 regulator-max-microvolt = <1875000>;
 231                                 regulator-boot-on;
 232                                 regulator-always-on;
 233                                 regulator-ramp-delay = <6250>;
 234                         };
 235
 236                         sw1c_reg: sw1c {
 237                                 regulator-min-microvolt = <300000>;
 238                                 regulator-max-microvolt = <1875000>;
 239                                 regulator-boot-on;
 240                                 regulator-always-on;
 241                                 regulator-ramp-delay = <6250>;
 242                         };
 243
 244                         sw3a_reg: sw3a {
 245                                 regulator-min-microvolt = <400000>;
 246                                 regulator-max-microvolt = <1975000>;
 247                                 regulator-boot-on;
 248                                 regulator-always-on;
 249                         };
 250
 251                         swbst_reg: swbst {
 252                                 regulator-min-microvolt = <5000000>;
 253                                 regulator-max-microvolt = <5150000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         snvs_reg: vsnvs {
 259                                 regulator-min-microvolt = <1000000>;
 260                                 regulator-max-microvolt = <3000000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                         };
 264
 265                         vref_reg: vrefddr {
 266                                 regulator-boot-on;
 267                                 regulator-always-on;
 268                         };
 269
 270                         vgen1_reg: vgen1 {
 271                                 regulator-min-microvolt = <800000>;
 272                                 regulator-max-microvolt = <1550000>;
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         vgen2_reg: vgen2 {
 278                                 regulator-min-microvolt = <800000>;
 279                                 regulator-max-microvolt = <1550000>;
 280                                 regulator-boot-on;
 281                                 regulator-always-on;
 282                         };
 283
 284                         vgen3_reg: vgen3 {
 285                                 regulator-min-microvolt = <1800000>;
 286                                 regulator-max-microvolt = <3300000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen4_reg: vgen4 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <1800000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         vgen5_reg: vgen5 {
 299                                 regulator-min-microvolt = <1800000>;
 300                                 regulator-max-microvolt = <3300000>;
 301                                 regulator-boot-on;
 302                                 regulator-always-on;
 303                         };
 304
 305                         vgen6_reg: vgen6 {
 306                                 regulator-min-microvolt = <1800000>;
 307                                 regulator-max-microvolt = <3300000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311                 };
 312         };
 313
 314         codec: sgtl5000@a {
 315                 compatible = "fsl,sgtl5000";
 316                 reg = <0x0a>;
 317                 clocks = <&clks IMX6QDL_CLK_CKO>;
 318                 VDDA-supply = <&reg_module_3v3_audio>;
 319                 VDDIO-supply = <&reg_module_3v3>;
 320                 VDDD-supply = <&vgen4_reg>;
 321         };
 322
 323         /* STMPE811 touch screen controller */
 324         stmpe811@41 {
 325                 compatible = "st,stmpe811";
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&pinctrl_touch_int>;
 328                 reg = <0x41>;
 329                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 330                 interrupt-parent = <&gpio4>;
 331                 interrupt-controller;
 332                 id = <0>;
 333                 blocks = <0x5>;
 334                 irq-trigger = <0x1>;
 335                 /* 3.25 MHz ADC clock speed */
 336                 st,adc-freq = <1>;
 337                 /* 12-bit ADC */
 338                 st,mod-12b = <1>;
 339                 /* internal ADC reference */
 340                 st,ref-sel = <0>;
 341                 /* ADC converstion time: 80 clocks */
 342                 st,sample-time = <4>;
 343
 344                 stmpe_touchscreen {
 345                         compatible = "st,stmpe-ts";
 346                         /* 8 sample average control */
 347                         st,ave-ctrl = <3>;
 348                         /* 7 length fractional part in z */
 349                         st,fraction-z = <7>;
 350                         /*
 351                          * 50 mA typical 80 mA max touchscreen drivers
 352                          * current limit value
 353                          */
 354                         st,i-drive = <1>;
 355                         /* 1 ms panel driver settling time */
 356                         st,settling = <3>;
 357                         /* 5 ms touch detect interrupt delay */
 358                         st,touch-det-delay = <5>;
 359                 };
 360
 361                 stmpe_adc {
 362                         compatible = "st,stmpe-adc";
 363                         /* forbid to use ADC channels 3-0 (touch) */
 364                         st,norequest-mask = <0x0F>;
 365                 };
 366         };
 367 };
 368
 369 /*
 370  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 371  * board)
 372  */
 373 &i2c3 {
 374         clock-frequency = <100000>;
 375         pinctrl-names = "default", "recovery";
 376         pinctrl-0 = <&pinctrl_i2c3>;
 377         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 378         scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 379         sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 380         status = "disabled";
 381 };
 382
 383 &pwm1 {
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&pinctrl_pwm1>;
 386         status = "disabled";
 387 };
 388
 389 &pwm2 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_pwm2>;
 392         status = "disabled";
 393 };
 394
 395 &pwm3 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_pwm3>;
 398         status = "disabled";
 399 };
 400
 401 &pwm4 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_pwm4>;
 404         status = "disabled";
 405 };
 406
 407 &spdif {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_spdif>;
 410         status = "disabled";
 411 };
 412
 413 &ssi1 {
 414         status = "okay";
 415 };
 416
 417 &uart1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 420         fsl,dte-mode;
 421         uart-has-rtscts;
 422         status = "disabled";
 423 };
 424
 425 &uart2 {
 426         pinctrl-names = "default";
 427         pinctrl-0 = <&pinctrl_uart2_dte>;
 428         fsl,dte-mode;
 429         uart-has-rtscts;
 430         status = "disabled";
 431 };
 432
 433 &uart4 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart4_dte>;
 436         fsl,dte-mode;
 437         status = "disabled";
 438 };
 439
 440 &uart5 {
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&pinctrl_uart5_dte>;
 443         fsl,dte-mode;
 444         status = "disabled";
 445 };
 446
 447 &usbotg {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_usbotg>;
 450         disable-over-current;
 451         status = "disabled";
 452 };
 453
 454 /* MMC1 */
 455 &usdhc1 {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 458         vqmmc-supply = <&reg_module_3v3>;
 459         bus-width = <8>;
 460         disable-wp;
 461         no-1-8-v;
 462         status = "disabled";
 463 };
 464
 465 /* SD1 */
 466 &usdhc2 {
 467         pinctrl-names = "default";
 468         pinctrl-0 = <&pinctrl_usdhc2>;
 469         vqmmc-supply = <&reg_module_3v3>;
 470         bus-width = <4>;
 471         disable-wp;
 472         no-1-8-v;
 473         status = "disabled";
 474 };
 475
 476 /* eMMC */
 477 &usdhc3 {
 478         pinctrl-names = "default";
 479         pinctrl-0 = <&pinctrl_usdhc3>;
 480         vqmmc-supply = <&reg_module_3v3>;
 481         bus-width = <8>;
 482         no-1-8-v;
 483         non-removable;
 484         status = "okay";
 485 };
 486
 487 &weim {
 488         status = "disabled";
 489 };
 490
 491 &iomuxc {
 492         pinctrl_apalis_gpio1: gpio2io04grp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 495                 >;
 496         };
 497
 498         pinctrl_apalis_gpio2: gpio2io05grp {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 501                 >;
 502         };
 503
 504         pinctrl_apalis_gpio3: gpio2io06grp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 507                 >;
 508         };
 509
 510         pinctrl_apalis_gpio4: gpio2io07grp {
 511                 fsl,pins = <
 512                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 513                 >;
 514         };
 515
 516         pinctrl_apalis_gpio5: gpio6io10grp {
 517                 fsl,pins = <
 518                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 519                 >;
 520         };
 521
 522         pinctrl_apalis_gpio6: gpio6io09grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 525                 >;
 526         };
 527
 528         pinctrl_apalis_gpio7: gpio1io02grp {
 529                 fsl,pins = <
 530                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 531                 >;
 532         };
 533
 534         pinctrl_apalis_gpio8: gpio1io06grp {
 535                 fsl,pins = <
 536                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 537                 >;
 538         };
 539
 540         pinctrl_audmux: audmuxgrp {
 541                 fsl,pins = <
 542                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 543                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 544                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 545                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 546                         /* SGTL5000 sys_mclk */
 547                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 548                 >;
 549         };
 550
 551         pinctrl_cam_mclk: cammclkgrp {
 552                 fsl,pins = <
 553                         /* CAM sys_mclk */
 554                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 555                 >;
 556         };
 557
 558         pinctrl_ecspi1: ecspi1grp {
 559                 fsl,pins = <
 560                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 561                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 562                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 563                         /* SPI1 cs */
 564                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 565                 >;
 566         };
 567
 568         pinctrl_ecspi2: ecspi2grp {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 571                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 572                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 573                         /* SPI2 cs */
 574                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 575                 >;
 576         };
 577
 578         pinctrl_enet: enetgrp {
 579                 fsl,pins = <
 580                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 581                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 582                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 583                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 584                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 585                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 586                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 587                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 588                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 589                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 590                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 591                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 592                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 593                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 594                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 595                         /* Ethernet PHY reset */
 596                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 597                         /* Ethernet PHY interrupt */
 598                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 599                 >;
 600         };
 601
 602         pinctrl_flexcan1: flexcan1grp {
 603                 fsl,pins = <
 604                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 605                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 606                 >;
 607         };
 608
 609         pinctrl_flexcan2: flexcan2grp {
 610                 fsl,pins = <
 611                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 612                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 613                 >;
 614         };
 615
 616         pinctrl_gpio_bl_on: gpioblon {
 617                 fsl,pins = <
 618                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 619                 >;
 620         };
 621
 622         pinctrl_gpio_keys: gpio1io04grp {
 623                 fsl,pins = <
 624                         /* Power button */
 625                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 626                 >;
 627         };
 628
 629         pinctrl_hdmi_cec: hdmicecgrp {
 630                 fsl,pins = <
 631                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 632                 >;
 633         };
 634
 635         pinctrl_hdmi_ddc: hdmiddcgrp {
 636                 fsl,pins = <
 637                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 638                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 639                 >;
 640         };
 641
 642         pinctrl_i2c1: i2c1grp {
 643                 fsl,pins = <
 644                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 645                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 646                 >;
 647         };
 648
 649         pinctrl_i2c2: i2c2grp {
 650                 fsl,pins = <
 651                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 652                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 653                 >;
 654         };
 655
 656         pinctrl_i2c3: i2c3grp {
 657                 fsl,pins = <
 658                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 659                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 660                 >;
 661         };
 662
 663         pinctrl_i2c3_recovery: i2c3recoverygrp {
 664                 fsl,pins = <
 665                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 666                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 667                 >;
 668         };
 669
 670         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 671                 fsl,pins = <
 672                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 673                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 674                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 675                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 676                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 677                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 678                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 679                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 680                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 681                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 682                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 683                 >;
 684         };
 685
 686         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 687                 fsl,pins = <
 688                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 689                         /* DE */
 690                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 691                         /* HSync */
 692                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 693                         /* VSync */
 694                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 695                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 696                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 697                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 698                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 699                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 700                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 701                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 702                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 703                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 704                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 705                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 706                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 707                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 708                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 709                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 710                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 711                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 712                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 713                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 714                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 715                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 716                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 717                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 718                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 719                 >;
 720         };
 721
 722         pinctrl_ipu2_vdac: ipu2vdacgrp {
 723                 fsl,pins = <
 724                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 725                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 726                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 727                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 728                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 729                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 730                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 731                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 732                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 733                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 734                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 735                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 736                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 737                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 738                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 739                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 740                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 741                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 742                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 743                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 744                 >;
 745         };
 746
 747         pinctrl_mmc_cd: gpiommccdgrp {
 748                 fsl,pins = <
 749                          /* MMC1 CD */
 750                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 751                 >;
 752         };
 753
 754         pinctrl_pwm1: pwm1grp {
 755                 fsl,pins = <
 756                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 757                 >;
 758         };
 759
 760         pinctrl_pwm2: pwm2grp {
 761                 fsl,pins = <
 762                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 763                 >;
 764         };
 765
 766         pinctrl_pwm3: pwm3grp {
 767                 fsl,pins = <
 768                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 769                 >;
 770         };
 771
 772         pinctrl_pwm4: pwm4grp {
 773                 fsl,pins = <
 774                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 775                 >;
 776         };
 777
 778         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 779                 fsl,pins = <
 780                         /* USBH_EN */
 781                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 782                 >;
 783         };
 784
 785         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 786                 fsl,pins = <
 787                         /* USBH_HUB_EN */
 788                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 789                 >;
 790         };
 791
 792         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 793                 fsl,pins = <
 794                         /* USBO1 power en */
 795                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 796                 >;
 797         };
 798
 799         pinctrl_reset_moci: gpioresetmocigrp {
 800                 fsl,pins = <
 801                         /* RESET_MOCI control */
 802                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 803                 >;
 804         };
 805
 806         pinctrl_sd_cd: gpiosdcdgrp {
 807                 fsl,pins = <
 808                         /* SD1 CD */
 809                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 810                 >;
 811         };
 812
 813         pinctrl_spdif: spdifgrp {
 814                 fsl,pins = <
 815                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 816                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 817                 >;
 818         };
 819
 820         pinctrl_touch_int: gpiotouchintgrp {
 821                 fsl,pins = <
 822                         /* STMPE811 interrupt */
 823                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 824                 >;
 825         };
 826
 827         pinctrl_uart1_dce: uart1dcegrp {
 828                 fsl,pins = <
 829                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 830                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 831                 >;
 832         };
 833
 834         /* DTE mode */
 835         pinctrl_uart1_dte: uart1dtegrp {
 836                 fsl,pins = <
 837                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 838                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 839                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 840                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 841                 >;
 842         };
 843
 844         /* Additional DTR, DSR, DCD */
 845         pinctrl_uart1_ctrl: uart1ctrlgrp {
 846                 fsl,pins = <
 847                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 848                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 849                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 850                 >;
 851         };
 852
 853         pinctrl_uart2_dce: uart2dcegrp {
 854                 fsl,pins = <
 855                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 856                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 857                 >;
 858         };
 859
 860         /* DTE mode */
 861         pinctrl_uart2_dte: uart2dtegrp {
 862                 fsl,pins = <
 863                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 864                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 865                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 866                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 867                 >;
 868         };
 869
 870         pinctrl_uart4_dce: uart4dcegrp {
 871                 fsl,pins = <
 872                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 873                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 874                 >;
 875         };
 876
 877         /* DTE mode */
 878         pinctrl_uart4_dte: uart4dtegrp {
 879                 fsl,pins = <
 880                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 881                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 882                 >;
 883         };
 884
 885         pinctrl_uart5_dce: uart5dcegrp {
 886                 fsl,pins = <
 887                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 888                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 889                 >;
 890         };
 891
 892         /* DTE mode */
 893         pinctrl_uart5_dte: uart5dtegrp {
 894                 fsl,pins = <
 895                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 896                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 897                 >;
 898         };
 899
 900         pinctrl_usbotg: usbotggrp {
 901                 fsl,pins = <
 902                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 903                 >;
 904         };
 905
 906         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 907                 fsl,pins = <
 908                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 909                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 910                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 911                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 912                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 913                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 914                 >;
 915         };
 916
 917         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 918                 fsl,pins = <
 919                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 920                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 921                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 922                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 923                 >;
 924         };
 925
 926         pinctrl_usdhc2: usdhc2grp {
 927                 fsl,pins = <
 928                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 929                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 930                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 931                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 932                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 933                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 934                 >;
 935         };
 936
 937         pinctrl_usdhc3: usdhc3grp {
 938                 fsl,pins = <
 939                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 940                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 941                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 942                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 943                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 944                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 945                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 946                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 947                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 948                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 949                         /* eMMC reset */
 950                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 951                 >;
 952         };
 953 };