arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 reg = <0x10000000 0>;
  53         };
  54
  55         backlight: backlight {
  56                 compatible = "pwm-backlight";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  59                 pwms = <&pwm4 0 5000000>;
  60                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  61                 status = "disabled";
  62         };
  63
  64         reg_1p8v: regulator-1p8v {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "1P8V";
  67                 regulator-min-microvolt = <1800000>;
  68                 regulator-max-microvolt = <1800000>;
  69                 regulator-always-on;
  70         };
  71
  72         reg_2p5v: regulator-2p5v {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "2P5V";
  75                 regulator-min-microvolt = <2500000>;
  76                 regulator-max-microvolt = <2500000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_3p3v: regulator-3p3v {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "3P3V";
  83                 regulator-min-microvolt = <3300000>;
  84                 regulator-max-microvolt = <3300000>;
  85                 regulator-always-on;
  86         };
  87
  88         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  89                 compatible = "regulator-fixed";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  92                 regulator-name = "usb_otg_vbus";
  93                 regulator-min-microvolt = <5000000>;
  94                 regulator-max-microvolt = <5000000>;
  95                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97                 status = "disabled";
  98         };
  99
 100         /* on module USB hub */
 101         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
 102                 compatible = "regulator-fixed";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
 105                 regulator-name = "usb_host_vbus_hub";
 106                 regulator-min-microvolt = <5000000>;
 107                 regulator-max-microvolt = <5000000>;
 108                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 109                 startup-delay-us = <2000>;
 110                 enable-active-high;
 111                 status = "okay";
 112         };
 113
 114         reg_usb_host_vbus: regulator-usb-host-vbus {
 115                 compatible = "regulator-fixed";
 116                 pinctrl-names = "default";
 117                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 118                 regulator-name = "usb_host_vbus";
 119                 regulator-min-microvolt = <5000000>;
 120                 regulator-max-microvolt = <5000000>;
 121                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 122                 enable-active-high;
 123                 vin-supply = <&reg_usb_host_vbus_hub>;
 124                 status = "disabled";
 125         };
 126
 127         sound {
 128                 compatible = "fsl,imx-audio-sgtl5000";
 129                 model = "imx6q-apalis-sgtl5000";
 130                 ssi-controller = <&ssi1>;
 131                 audio-codec = <&codec>;
 132                 audio-routing =
 133                         "LINE_IN", "Line In Jack",
 134                         "MIC_IN", "Mic Jack",
 135                         "Mic Jack", "Mic Bias",
 136                         "Headphone Jack", "HP_OUT";
 137                 mux-int-port = <1>;
 138                 mux-ext-port = <4>;
 139         };
 140
 141         sound_spdif: sound-spdif {
 142                 compatible = "fsl,imx-audio-spdif";
 143                 model = "imx-spdif";
 144                 spdif-controller = <&spdif>;
 145                 spdif-in;
 146                 spdif-out;
 147                 status = "disabled";
 148         };
 149 };
 150
 151 &audmux {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_audmux>;
 154         status = "okay";
 155 };
 156
 157 &can1 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_flexcan1>;
 160         status = "disabled";
 161 };
 162
 163 &can2 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_flexcan2>;
 166         status = "disabled";
 167 };
 168
 169 /* Apalis SPI1 */
 170 &ecspi1 {
 171         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_ecspi1>;
 174         status = "disabled";
 175 };
 176
 177 /* Apalis SPI2 */
 178 &ecspi2 {
 179         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_ecspi2>;
 182         status = "disabled";
 183 };
 184
 185 &fec {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_enet>;
 188         phy-mode = "rgmii";
 189         phy-handle = <&ethphy>;
 190         phy-reset-duration = <10>;
 191         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 192         status = "okay";
 193
 194         mdio {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197
 198                 ethphy: ethernet-phy@7 {
 199                         interrupt-parent = <&gpio1>;
 200                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 201                         reg = <7>;
 202                 };
 203         };
 204 };
 205
 206 &hdmi {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 209         status = "disabled";
 210 };
 211
 212 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 213 &i2c1 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c1>;
 217         status = "disabled";
 218 };
 219
 220 /*
 221  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 222  * touch screen controller
 223  */
 224 &i2c2 {
 225         clock-frequency = <100000>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_i2c2>;
 228         status = "okay";
 229
 230         pmic: pfuze100@8 {
 231                 compatible = "fsl,pfuze100";
 232                 reg = <0x08>;
 233
 234                 regulators {
 235                         sw1a_reg: sw1ab {
 236                                 regulator-min-microvolt = <300000>;
 237                                 regulator-max-microvolt = <1875000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                                 regulator-ramp-delay = <6250>;
 241                         };
 242
 243                         sw1c_reg: sw1c {
 244                                 regulator-min-microvolt = <300000>;
 245                                 regulator-max-microvolt = <1875000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                                 regulator-ramp-delay = <6250>;
 249                         };
 250
 251                         sw3a_reg: sw3a {
 252                                 regulator-min-microvolt = <400000>;
 253                                 regulator-max-microvolt = <1975000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         swbst_reg: swbst {
 259                                 regulator-min-microvolt = <5000000>;
 260                                 regulator-max-microvolt = <5150000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                         };
 264
 265                         snvs_reg: vsnvs {
 266                                 regulator-min-microvolt = <1000000>;
 267                                 regulator-max-microvolt = <3000000>;
 268                                 regulator-boot-on;
 269                                 regulator-always-on;
 270                         };
 271
 272                         vref_reg: vrefddr {
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         vgen1_reg: vgen1 {
 278                                 regulator-min-microvolt = <800000>;
 279                                 regulator-max-microvolt = <1550000>;
 280                                 regulator-boot-on;
 281                                 regulator-always-on;
 282                         };
 283
 284                         vgen2_reg: vgen2 {
 285                                 regulator-min-microvolt = <800000>;
 286                                 regulator-max-microvolt = <1550000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen3_reg: vgen3 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         vgen4_reg: vgen4 {
 299                                 regulator-min-microvolt = <1800000>;
 300                                 regulator-max-microvolt = <3300000>;
 301                                 regulator-boot-on;
 302                                 regulator-always-on;
 303                         };
 304
 305                         vgen5_reg: vgen5 {
 306                                 regulator-min-microvolt = <1800000>;
 307                                 regulator-max-microvolt = <3300000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311
 312                         vgen6_reg: vgen6 {
 313                                 regulator-min-microvolt = <1800000>;
 314                                 regulator-max-microvolt = <3300000>;
 315                                 regulator-boot-on;
 316                                 regulator-always-on;
 317                         };
 318                 };
 319         };
 320
 321         codec: sgtl5000@a {
 322                 compatible = "fsl,sgtl5000";
 323                 reg = <0x0a>;
 324                 clocks = <&clks IMX6QDL_CLK_CKO>;
 325                 VDDA-supply = <&reg_2p5v>;
 326                 VDDIO-supply = <&reg_3p3v>;
 327         };
 328
 329         /* STMPE811 touch screen controller */
 330         stmpe811@41 {
 331                 compatible = "st,stmpe811";
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&pinctrl_touch_int>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 reg = <0x41>;
 337                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 338                 interrupt-parent = <&gpio4>;
 339                 interrupt-controller;
 340                 id = <0>;
 341                 blocks = <0x5>;
 342                 irq-trigger = <0x1>;
 343
 344                 stmpe_touchscreen {
 345                         compatible = "st,stmpe-ts";
 346                         /* 3.25 MHz ADC clock speed */
 347                         st,adc-freq = <1>;
 348                         /* 8 sample average control */
 349                         st,ave-ctrl = <3>;
 350                         /* 7 length fractional part in z */
 351                         st,fraction-z = <7>;
 352                         /*
 353                          * 50 mA typical 80 mA max touchscreen drivers
 354                          * current limit value
 355                          */
 356                         st,i-drive = <1>;
 357                         /* 12-bit ADC */
 358                         st,mod-12b = <1>;
 359                         /* internal ADC reference */
 360                         st,ref-sel = <0>;
 361                         /* ADC converstion time: 80 clocks */
 362                         st,sample-time = <4>;
 363                         /* 1 ms panel driver settling time */
 364                         st,settling = <3>;
 365                         /* 5 ms touch detect interrupt delay */
 366                         st,touch-det-delay = <5>;
 367                 };
 368         };
 369 };
 370
 371 /*
 372  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 373  * board)
 374  */
 375 &i2c3 {
 376         clock-frequency = <100000>;
 377         pinctrl-names = "default", "recovery";
 378         pinctrl-0 = <&pinctrl_i2c3>;
 379         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 380         scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
 381         sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 382         status = "disabled";
 383 };
 384
 385 &pwm1 {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_pwm1>;
 388         status = "disabled";
 389 };
 390
 391 &pwm2 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_pwm2>;
 394         status = "disabled";
 395 };
 396
 397 &pwm3 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_pwm3>;
 400         status = "disabled";
 401 };
 402
 403 &pwm4 {
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_pwm4>;
 406         status = "disabled";
 407 };
 408
 409 &spdif {
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_spdif>;
 412         status = "disabled";
 413 };
 414
 415 &ssi1 {
 416         status = "okay";
 417 };
 418
 419 &uart1 {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 422         fsl,dte-mode;
 423         uart-has-rtscts;
 424         status = "disabled";
 425 };
 426
 427 &uart2 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_uart2_dte>;
 430         fsl,dte-mode;
 431         uart-has-rtscts;
 432         status = "disabled";
 433 };
 434
 435 &uart4 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart4_dte>;
 438         fsl,dte-mode;
 439         status = "disabled";
 440 };
 441
 442 &uart5 {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_uart5_dte>;
 445         fsl,dte-mode;
 446         status = "disabled";
 447 };
 448
 449 &usbotg {
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&pinctrl_usbotg>;
 452         disable-over-current;
 453         status = "disabled";
 454 };
 455
 456 /* MMC1 */
 457 &usdhc1 {
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 460         vqmmc-supply = <&reg_3p3v>;
 461         bus-width = <8>;
 462         voltage-ranges = <3300 3300>;
 463         status = "disabled";
 464 };
 465
 466 /* SD1 */
 467 &usdhc2 {
 468         pinctrl-names = "default";
 469         pinctrl-0 = <&pinctrl_usdhc2>;
 470         vqmmc-supply = <&reg_3p3v>;
 471         bus-width = <4>;
 472         voltage-ranges = <3300 3300>;
 473         status = "disabled";
 474 };
 475
 476 /* eMMC */
 477 &usdhc3 {
 478         pinctrl-names = "default";
 479         pinctrl-0 = <&pinctrl_usdhc3>;
 480         vqmmc-supply = <&reg_3p3v>;
 481         bus-width = <8>;
 482         voltage-ranges = <3300 3300>;
 483         non-removable;
 484         status = "okay";
 485 };
 486
 487 &weim {
 488         status = "disabled";
 489 };
 490
 491 &iomuxc {
 492         /* pins used on module */
 493         pinctrl-names = "default";
 494         pinctrl-0 = <&pinctrl_reset_moci>;
 495
 496         pinctrl_apalis_gpio1: gpio2io04grp {
 497                 fsl,pins = <
 498                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 499                 >;
 500         };
 501
 502         pinctrl_apalis_gpio2: gpio2io05grp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 505                 >;
 506         };
 507
 508         pinctrl_apalis_gpio3: gpio2io06grp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 511                 >;
 512         };
 513
 514         pinctrl_apalis_gpio4: gpio2io07grp {
 515                 fsl,pins = <
 516                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 517                 >;
 518         };
 519
 520         pinctrl_apalis_gpio5: gpio6io10grp {
 521                 fsl,pins = <
 522                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 523                 >;
 524         };
 525
 526         pinctrl_apalis_gpio6: gpio6io09grp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 529                 >;
 530         };
 531
 532         pinctrl_apalis_gpio7: gpio1io02grp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 535                 >;
 536         };
 537
 538         pinctrl_apalis_gpio8: gpio1io06grp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 541                 >;
 542         };
 543
 544         pinctrl_audmux: audmuxgrp {
 545                 fsl,pins = <
 546                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 547                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 548                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 549                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 550                         /* SGTL5000 sys_mclk */
 551                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 552                 >;
 553         };
 554
 555         pinctrl_cam_mclk: cammclkgrp {
 556                 fsl,pins = <
 557                         /* CAM sys_mclk */
 558                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 559                 >;
 560         };
 561
 562         pinctrl_ecspi1: ecspi1grp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 565                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 566                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 567                         /* SPI1 cs */
 568                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 569                 >;
 570         };
 571
 572         pinctrl_ecspi2: ecspi2grp {
 573                 fsl,pins = <
 574                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 575                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 576                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 577                         /* SPI2 cs */
 578                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 579                 >;
 580         };
 581
 582         pinctrl_enet: enetgrp {
 583                 fsl,pins = <
 584                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 585                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 586                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 587                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 588                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 589                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 590                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 591                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 592                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 593                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 594                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 595                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 596                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 597                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 598                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 599                         /* Ethernet PHY reset */
 600                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 601                         /* Ethernet PHY interrupt */
 602                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 603                 >;
 604         };
 605
 606         pinctrl_flexcan1: flexcan1grp {
 607                 fsl,pins = <
 608                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 609                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 610                 >;
 611         };
 612
 613         pinctrl_flexcan2: flexcan2grp {
 614                 fsl,pins = <
 615                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 616                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 617                 >;
 618         };
 619
 620         pinctrl_gpio_bl_on: gpioblon {
 621                 fsl,pins = <
 622                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 623                 >;
 624         };
 625
 626         pinctrl_gpio_keys: gpio1io04grp {
 627                 fsl,pins = <
 628                         /* Power button */
 629                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 630                 >;
 631         };
 632
 633         pinctrl_hdmi_cec: hdmicecgrp {
 634                 fsl,pins = <
 635                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 636                 >;
 637         };
 638
 639         pinctrl_hdmi_ddc: hdmiddcgrp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 642                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 643                 >;
 644         };
 645
 646         pinctrl_i2c1: i2c1grp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 649                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 650                 >;
 651         };
 652
 653         pinctrl_i2c2: i2c2grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 656                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 657                 >;
 658         };
 659
 660         pinctrl_i2c3: i2c3grp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 663                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 664                 >;
 665         };
 666
 667         pinctrl_i2c3_recovery: i2c3recoverygrp {
 668                 fsl,pins = <
 669                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 670                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 671                 >;
 672         };
 673
 674         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 675                 fsl,pins = <
 676                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 677                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 678                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 679                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 680                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 681                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 682                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 683                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 684                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 685                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 686                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 687                 >;
 688         };
 689
 690         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 691                 fsl,pins = <
 692                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 693                         /* DE */
 694                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 695                         /* HSync */
 696                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 697                         /* VSync */
 698                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 699                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 700                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 701                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 702                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 703                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 704                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 705                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 706                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 707                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 708                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 709                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 710                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 711                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 712                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 713                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 714                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 715                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 716                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 717                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 718                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 719                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 720                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 721                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 722                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 723                 >;
 724         };
 725
 726         pinctrl_ipu2_vdac: ipu2vdacgrp {
 727                 fsl,pins = <
 728                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 729                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 730                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 731                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 732                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 733                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 734                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 735                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 736                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 737                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 738                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 739                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 740                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 741                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 742                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 743                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 744                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 745                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 746                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 747                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 748                 >;
 749         };
 750
 751         pinctrl_mmc_cd: gpiommccdgrp {
 752                 fsl,pins = <
 753                          /* MMC1 CD */
 754                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 755                 >;
 756         };
 757
 758         pinctrl_pwm1: pwm1grp {
 759                 fsl,pins = <
 760                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 761                 >;
 762         };
 763
 764         pinctrl_pwm2: pwm2grp {
 765                 fsl,pins = <
 766                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 767                 >;
 768         };
 769
 770         pinctrl_pwm3: pwm3grp {
 771                 fsl,pins = <
 772                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 773                 >;
 774         };
 775
 776         pinctrl_pwm4: pwm4grp {
 777                 fsl,pins = <
 778                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 779                 >;
 780         };
 781
 782         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 783                 fsl,pins = <
 784                         /* USBH_EN */
 785                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 786                 >;
 787         };
 788
 789         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 790                 fsl,pins = <
 791                         /* USBH_HUB_EN */
 792                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 793                 >;
 794         };
 795
 796         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 797                 fsl,pins = <
 798                         /* USBO1 power en */
 799                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 800                 >;
 801         };
 802
 803         pinctrl_reset_moci: gpioresetmocigrp {
 804                 fsl,pins = <
 805                         /* RESET_MOCI control */
 806                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 807                 >;
 808         };
 809
 810         pinctrl_sd_cd: gpiosdcdgrp {
 811                 fsl,pins = <
 812                         /* SD1 CD */
 813                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 814                 >;
 815         };
 816
 817         pinctrl_spdif: spdifgrp {
 818                 fsl,pins = <
 819                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 820                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 821                 >;
 822         };
 823
 824         pinctrl_touch_int: gpiotouchintgrp {
 825                 fsl,pins = <
 826                         /* STMPE811 interrupt */
 827                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 828                 >;
 829         };
 830
 831         pinctrl_uart1_dce: uart1dcegrp {
 832                 fsl,pins = <
 833                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 834                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 835                 >;
 836         };
 837
 838         /* DTE mode */
 839         pinctrl_uart1_dte: uart1dtegrp {
 840                 fsl,pins = <
 841                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 842                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 843                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 844                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 845                 >;
 846         };
 847
 848         /* Additional DTR, DSR, DCD */
 849         pinctrl_uart1_ctrl: uart1ctrlgrp {
 850                 fsl,pins = <
 851                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 852                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 853                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 854                 >;
 855         };
 856
 857         pinctrl_uart2_dce: uart2dcegrp {
 858                 fsl,pins = <
 859                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 860                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 861                 >;
 862         };
 863
 864         /* DTE mode */
 865         pinctrl_uart2_dte: uart2dtegrp {
 866                 fsl,pins = <
 867                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 868                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 869                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 870                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 871                 >;
 872         };
 873
 874         pinctrl_uart4_dce: uart4dcegrp {
 875                 fsl,pins = <
 876                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 877                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 878                 >;
 879         };
 880
 881         /* DTE mode */
 882         pinctrl_uart4_dte: uart4dtegrp {
 883                 fsl,pins = <
 884                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 885                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 886                 >;
 887         };
 888
 889         pinctrl_uart5_dce: uart5dcegrp {
 890                 fsl,pins = <
 891                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 892                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 893                 >;
 894         };
 895
 896         /* DTE mode */
 897         pinctrl_uart5_dte: uart5dtegrp {
 898                 fsl,pins = <
 899                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 900                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 901                 >;
 902         };
 903
 904         pinctrl_usbotg: usbotggrp {
 905                 fsl,pins = <
 906                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 907                 >;
 908         };
 909
 910         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 911                 fsl,pins = <
 912                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 913                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 914                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 915                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 916                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 917                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 918                 >;
 919         };
 920
 921         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 922                 fsl,pins = <
 923                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 924                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 925                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 926                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 927                 >;
 928         };
 929
 930         pinctrl_usdhc2: usdhc2grp {
 931                 fsl,pins = <
 932                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 933                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 934                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 935                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 936                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 937                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 938                 >;
 939         };
 940
 941         pinctrl_usdhc3: usdhc3grp {
 942                 fsl,pins = <
 943                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 944                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 945                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 946                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 947                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 948                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 949                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 950                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 951                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 952                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 953                         /* eMMC reset */
 954                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 955                 >;
 956         };
 957
 958         pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
 959                 fsl,pins = <
 960                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9
 961                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9
 962                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
 963                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
 964                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
 965                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
 966                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
 967                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
 968                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
 969                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
 970                         /* eMMC reset */
 971                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9
 972                 >;
 973         };
 974
 975         pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
 976                 fsl,pins = <
 977                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9
 978                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9
 979                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
 980                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
 981                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
 982                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
 983                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
 984                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
 985                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
 986                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
 987                         /* eMMC reset */
 988                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9
 989                 >;
 990         };
 991 };