arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 reg = <0x10000000 0>;
  53         };
  54
  55         backlight: backlight {
  56                 compatible = "pwm-backlight";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  59                 pwms = <&pwm4 0 5000000>;
  60                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  61                 status = "disabled";
  62         };
  63
  64         reg_1p8v: regulator-1p8v {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "1P8V";
  67                 regulator-min-microvolt = <1800000>;
  68                 regulator-max-microvolt = <1800000>;
  69                 regulator-always-on;
  70         };
  71
  72         reg_2p5v: regulator-2p5v {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "2P5V";
  75                 regulator-min-microvolt = <2500000>;
  76                 regulator-max-microvolt = <2500000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_3p3v: regulator-3p3v {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "3P3V";
  83                 regulator-min-microvolt = <3300000>;
  84                 regulator-max-microvolt = <3300000>;
  85                 regulator-always-on;
  86         };
  87
  88         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  89                 compatible = "regulator-fixed";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  92                 regulator-name = "usb_otg_vbus";
  93                 regulator-min-microvolt = <5000000>;
  94                 regulator-max-microvolt = <5000000>;
  95                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97                 status = "disabled";
  98         };
  99
 100         /* on module USB hub */
 101         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
 102                 compatible = "regulator-fixed";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
 105                 regulator-name = "usb_host_vbus_hub";
 106                 regulator-min-microvolt = <5000000>;
 107                 regulator-max-microvolt = <5000000>;
 108                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 109                 startup-delay-us = <2000>;
 110                 enable-active-high;
 111                 status = "okay";
 112         };
 113
 114         reg_usb_host_vbus: regulator-usb-host-vbus {
 115                 compatible = "regulator-fixed";
 116                 pinctrl-names = "default";
 117                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 118                 regulator-name = "usb_host_vbus";
 119                 regulator-min-microvolt = <5000000>;
 120                 regulator-max-microvolt = <5000000>;
 121                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 122                 enable-active-high;
 123                 vin-supply = <&reg_usb_host_vbus_hub>;
 124                 status = "disabled";
 125         };
 126
 127         sound {
 128                 compatible = "fsl,imx-audio-sgtl5000";
 129                 model = "imx6q-apalis-sgtl5000";
 130                 ssi-controller = <&ssi1>;
 131                 audio-codec = <&codec>;
 132                 audio-routing =
 133                         "LINE_IN", "Line In Jack",
 134                         "MIC_IN", "Mic Jack",
 135                         "Mic Jack", "Mic Bias",
 136                         "Headphone Jack", "HP_OUT";
 137                 mux-int-port = <1>;
 138                 mux-ext-port = <4>;
 139         };
 140
 141         sound_spdif: sound-spdif {
 142                 compatible = "fsl,imx-audio-spdif";
 143                 model = "imx-spdif";
 144                 spdif-controller = <&spdif>;
 145                 spdif-in;
 146                 spdif-out;
 147                 status = "disabled";
 148         };
 149 };
 150
 151 &audmux {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_audmux>;
 154         status = "okay";
 155 };
 156
 157 &can1 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_flexcan1>;
 160         status = "disabled";
 161 };
 162
 163 &can2 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_flexcan2>;
 166         status = "disabled";
 167 };
 168
 169 /* Apalis SPI1 */
 170 &ecspi1 {
 171         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_ecspi1>;
 174         status = "disabled";
 175 };
 176
 177 /* Apalis SPI2 */
 178 &ecspi2 {
 179         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_ecspi2>;
 182         status = "disabled";
 183 };
 184
 185 &fec {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_enet>;
 188         phy-mode = "rgmii";
 189         phy-handle = <&ethphy>;
 190         phy-reset-duration = <10>;
 191         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 192         status = "okay";
 193
 194         mdio {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197
 198                 ethphy: ethernet-phy@7 {
 199                         interrupt-parent = <&gpio1>;
 200                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 201                         reg = <7>;
 202                 };
 203         };
 204 };
 205
 206 &hdmi {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 209         status = "disabled";
 210 };
 211
 212 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 213 &i2c1 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c1>;
 217         status = "disabled";
 218 };
 219
 220 /*
 221  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 222  * touch screen controller
 223  */
 224 &i2c2 {
 225         clock-frequency = <100000>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_i2c2>;
 228         status = "okay";
 229
 230         pmic: pfuze100@8 {
 231                 compatible = "fsl,pfuze100";
 232                 reg = <0x08>;
 233
 234                 regulators {
 235                         sw1a_reg: sw1ab {
 236                                 regulator-min-microvolt = <300000>;
 237                                 regulator-max-microvolt = <1875000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                                 regulator-ramp-delay = <6250>;
 241                         };
 242
 243                         sw1c_reg: sw1c {
 244                                 regulator-min-microvolt = <300000>;
 245                                 regulator-max-microvolt = <1875000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                                 regulator-ramp-delay = <6250>;
 249                         };
 250
 251                         sw3a_reg: sw3a {
 252                                 regulator-min-microvolt = <400000>;
 253                                 regulator-max-microvolt = <1975000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         swbst_reg: swbst {
 259                                 regulator-min-microvolt = <5000000>;
 260                                 regulator-max-microvolt = <5150000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                         };
 264
 265                         snvs_reg: vsnvs {
 266                                 regulator-min-microvolt = <1000000>;
 267                                 regulator-max-microvolt = <3000000>;
 268                                 regulator-boot-on;
 269                                 regulator-always-on;
 270                         };
 271
 272                         vref_reg: vrefddr {
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         vgen1_reg: vgen1 {
 278                                 regulator-min-microvolt = <800000>;
 279                                 regulator-max-microvolt = <1550000>;
 280                                 regulator-boot-on;
 281                                 regulator-always-on;
 282                         };
 283
 284                         vgen2_reg: vgen2 {
 285                                 regulator-min-microvolt = <800000>;
 286                                 regulator-max-microvolt = <1550000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen3_reg: vgen3 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         vgen4_reg: vgen4 {
 299                                 regulator-min-microvolt = <1800000>;
 300                                 regulator-max-microvolt = <3300000>;
 301                                 regulator-boot-on;
 302                                 regulator-always-on;
 303                         };
 304
 305                         vgen5_reg: vgen5 {
 306                                 regulator-min-microvolt = <1800000>;
 307                                 regulator-max-microvolt = <3300000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311
 312                         vgen6_reg: vgen6 {
 313                                 regulator-min-microvolt = <1800000>;
 314                                 regulator-max-microvolt = <3300000>;
 315                                 regulator-boot-on;
 316                                 regulator-always-on;
 317                         };
 318                 };
 319         };
 320
 321         codec: sgtl5000@a {
 322                 compatible = "fsl,sgtl5000";
 323                 reg = <0x0a>;
 324                 clocks = <&clks IMX6QDL_CLK_CKO>;
 325                 VDDA-supply = <&reg_2p5v>;
 326                 VDDIO-supply = <&reg_3p3v>;
 327         };
 328
 329         /* STMPE811 touch screen controller */
 330         stmpe811@41 {
 331                 compatible = "st,stmpe811";
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&pinctrl_touch_int>;
 334                 reg = <0x41>;
 335                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 336                 interrupt-parent = <&gpio4>;
 337                 interrupt-controller;
 338                 id = <0>;
 339                 blocks = <0x5>;
 340                 irq-trigger = <0x1>;
 341
 342                 stmpe_touchscreen {
 343                         compatible = "st,stmpe-ts";
 344                         /* 3.25 MHz ADC clock speed */
 345                         st,adc-freq = <1>;
 346                         /* 8 sample average control */
 347                         st,ave-ctrl = <3>;
 348                         /* 7 length fractional part in z */
 349                         st,fraction-z = <7>;
 350                         /*
 351                          * 50 mA typical 80 mA max touchscreen drivers
 352                          * current limit value
 353                          */
 354                         st,i-drive = <1>;
 355                         /* 12-bit ADC */
 356                         st,mod-12b = <1>;
 357                         /* internal ADC reference */
 358                         st,ref-sel = <0>;
 359                         /* ADC converstion time: 80 clocks */
 360                         st,sample-time = <4>;
 361                         /* 1 ms panel driver settling time */
 362                         st,settling = <3>;
 363                         /* 5 ms touch detect interrupt delay */
 364                         st,touch-det-delay = <5>;
 365                 };
 366         };
 367 };
 368
 369 /*
 370  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 371  * board)
 372  */
 373 &i2c3 {
 374         clock-frequency = <100000>;
 375         pinctrl-names = "default", "recovery";
 376         pinctrl-0 = <&pinctrl_i2c3>;
 377         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 378         scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
 379         sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 380         status = "disabled";
 381 };
 382
 383 &pwm1 {
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&pinctrl_pwm1>;
 386         status = "disabled";
 387 };
 388
 389 &pwm2 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_pwm2>;
 392         status = "disabled";
 393 };
 394
 395 &pwm3 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_pwm3>;
 398         status = "disabled";
 399 };
 400
 401 &pwm4 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_pwm4>;
 404         status = "disabled";
 405 };
 406
 407 &spdif {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_spdif>;
 410         status = "disabled";
 411 };
 412
 413 &ssi1 {
 414         status = "okay";
 415 };
 416
 417 &uart1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 420         fsl,dte-mode;
 421         uart-has-rtscts;
 422         status = "disabled";
 423 };
 424
 425 &uart2 {
 426         pinctrl-names = "default";
 427         pinctrl-0 = <&pinctrl_uart2_dte>;
 428         fsl,dte-mode;
 429         uart-has-rtscts;
 430         status = "disabled";
 431 };
 432
 433 &uart4 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart4_dte>;
 436         fsl,dte-mode;
 437         status = "disabled";
 438 };
 439
 440 &uart5 {
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&pinctrl_uart5_dte>;
 443         fsl,dte-mode;
 444         status = "disabled";
 445 };
 446
 447 &usbotg {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_usbotg>;
 450         disable-over-current;
 451         status = "disabled";
 452 };
 453
 454 /* MMC1 */
 455 &usdhc1 {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 458         vqmmc-supply = <&reg_3p3v>;
 459         bus-width = <8>;
 460         voltage-ranges = <3300 3300>;
 461         status = "disabled";
 462 };
 463
 464 /* SD1 */
 465 &usdhc2 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&pinctrl_usdhc2>;
 468         vqmmc-supply = <&reg_3p3v>;
 469         bus-width = <4>;
 470         voltage-ranges = <3300 3300>;
 471         status = "disabled";
 472 };
 473
 474 /* eMMC */
 475 &usdhc3 {
 476         pinctrl-names = "default";
 477         pinctrl-0 = <&pinctrl_usdhc3>;
 478         vqmmc-supply = <&reg_3p3v>;
 479         bus-width = <8>;
 480         voltage-ranges = <3300 3300>;
 481         non-removable;
 482         status = "okay";
 483 };
 484
 485 &weim {
 486         status = "disabled";
 487 };
 488
 489 &iomuxc {
 490         /* pins used on module */
 491         pinctrl-names = "default";
 492         pinctrl-0 = <&pinctrl_reset_moci>;
 493
 494         pinctrl_apalis_gpio1: gpio2io04grp {
 495                 fsl,pins = <
 496                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 497                 >;
 498         };
 499
 500         pinctrl_apalis_gpio2: gpio2io05grp {
 501                 fsl,pins = <
 502                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 503                 >;
 504         };
 505
 506         pinctrl_apalis_gpio3: gpio2io06grp {
 507                 fsl,pins = <
 508                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 509                 >;
 510         };
 511
 512         pinctrl_apalis_gpio4: gpio2io07grp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 515                 >;
 516         };
 517
 518         pinctrl_apalis_gpio5: gpio6io10grp {
 519                 fsl,pins = <
 520                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 521                 >;
 522         };
 523
 524         pinctrl_apalis_gpio6: gpio6io09grp {
 525                 fsl,pins = <
 526                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 527                 >;
 528         };
 529
 530         pinctrl_apalis_gpio7: gpio1io02grp {
 531                 fsl,pins = <
 532                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 533                 >;
 534         };
 535
 536         pinctrl_apalis_gpio8: gpio1io06grp {
 537                 fsl,pins = <
 538                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 539                 >;
 540         };
 541
 542         pinctrl_audmux: audmuxgrp {
 543                 fsl,pins = <
 544                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 545                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 546                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 547                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 548                         /* SGTL5000 sys_mclk */
 549                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 550                 >;
 551         };
 552
 553         pinctrl_cam_mclk: cammclkgrp {
 554                 fsl,pins = <
 555                         /* CAM sys_mclk */
 556                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 557                 >;
 558         };
 559
 560         pinctrl_ecspi1: ecspi1grp {
 561                 fsl,pins = <
 562                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 563                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 564                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 565                         /* SPI1 cs */
 566                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 567                 >;
 568         };
 569
 570         pinctrl_ecspi2: ecspi2grp {
 571                 fsl,pins = <
 572                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 573                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 574                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 575                         /* SPI2 cs */
 576                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 577                 >;
 578         };
 579
 580         pinctrl_enet: enetgrp {
 581                 fsl,pins = <
 582                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 583                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 584                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 585                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 586                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 587                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 588                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 589                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 590                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 591                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 592                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 593                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 594                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 595                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 596                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 597                         /* Ethernet PHY reset */
 598                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 599                         /* Ethernet PHY interrupt */
 600                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 601                 >;
 602         };
 603
 604         pinctrl_flexcan1: flexcan1grp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 607                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 608                 >;
 609         };
 610
 611         pinctrl_flexcan2: flexcan2grp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 614                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 615                 >;
 616         };
 617
 618         pinctrl_gpio_bl_on: gpioblon {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 621                 >;
 622         };
 623
 624         pinctrl_gpio_keys: gpio1io04grp {
 625                 fsl,pins = <
 626                         /* Power button */
 627                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 628                 >;
 629         };
 630
 631         pinctrl_hdmi_cec: hdmicecgrp {
 632                 fsl,pins = <
 633                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 634                 >;
 635         };
 636
 637         pinctrl_hdmi_ddc: hdmiddcgrp {
 638                 fsl,pins = <
 639                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 640                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 641                 >;
 642         };
 643
 644         pinctrl_i2c1: i2c1grp {
 645                 fsl,pins = <
 646                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 647                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 648                 >;
 649         };
 650
 651         pinctrl_i2c2: i2c2grp {
 652                 fsl,pins = <
 653                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 654                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 655                 >;
 656         };
 657
 658         pinctrl_i2c3: i2c3grp {
 659                 fsl,pins = <
 660                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 661                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 662                 >;
 663         };
 664
 665         pinctrl_i2c3_recovery: i2c3recoverygrp {
 666                 fsl,pins = <
 667                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 668                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 669                 >;
 670         };
 671
 672         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 673                 fsl,pins = <
 674                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 675                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 676                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 677                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 678                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 679                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 680                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 681                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 682                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 683                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 684                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 685                 >;
 686         };
 687
 688         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 689                 fsl,pins = <
 690                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 691                         /* DE */
 692                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 693                         /* HSync */
 694                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 695                         /* VSync */
 696                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 697                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 698                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 699                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 700                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 701                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 702                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 703                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 704                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 705                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 706                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 707                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 708                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 709                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 710                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 711                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 712                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 713                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 714                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 715                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 716                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 717                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 718                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 719                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 720                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 721                 >;
 722         };
 723
 724         pinctrl_ipu2_vdac: ipu2vdacgrp {
 725                 fsl,pins = <
 726                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 727                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 728                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 729                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 730                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 731                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 732                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 733                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 734                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 735                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 736                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 737                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 738                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 739                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 740                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 741                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 742                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 743                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 744                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 745                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 746                 >;
 747         };
 748
 749         pinctrl_mmc_cd: gpiommccdgrp {
 750                 fsl,pins = <
 751                          /* MMC1 CD */
 752                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 753                 >;
 754         };
 755
 756         pinctrl_pwm1: pwm1grp {
 757                 fsl,pins = <
 758                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 759                 >;
 760         };
 761
 762         pinctrl_pwm2: pwm2grp {
 763                 fsl,pins = <
 764                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 765                 >;
 766         };
 767
 768         pinctrl_pwm3: pwm3grp {
 769                 fsl,pins = <
 770                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 771                 >;
 772         };
 773
 774         pinctrl_pwm4: pwm4grp {
 775                 fsl,pins = <
 776                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 777                 >;
 778         };
 779
 780         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 781                 fsl,pins = <
 782                         /* USBH_EN */
 783                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 784                 >;
 785         };
 786
 787         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 788                 fsl,pins = <
 789                         /* USBH_HUB_EN */
 790                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 791                 >;
 792         };
 793
 794         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 795                 fsl,pins = <
 796                         /* USBO1 power en */
 797                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 798                 >;
 799         };
 800
 801         pinctrl_reset_moci: gpioresetmocigrp {
 802                 fsl,pins = <
 803                         /* RESET_MOCI control */
 804                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 805                 >;
 806         };
 807
 808         pinctrl_sd_cd: gpiosdcdgrp {
 809                 fsl,pins = <
 810                         /* SD1 CD */
 811                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 812                 >;
 813         };
 814
 815         pinctrl_spdif: spdifgrp {
 816                 fsl,pins = <
 817                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 818                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 819                 >;
 820         };
 821
 822         pinctrl_touch_int: gpiotouchintgrp {
 823                 fsl,pins = <
 824                         /* STMPE811 interrupt */
 825                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 826                 >;
 827         };
 828
 829         pinctrl_uart1_dce: uart1dcegrp {
 830                 fsl,pins = <
 831                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 832                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 833                 >;
 834         };
 835
 836         /* DTE mode */
 837         pinctrl_uart1_dte: uart1dtegrp {
 838                 fsl,pins = <
 839                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 840                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 841                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 842                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 843                 >;
 844         };
 845
 846         /* Additional DTR, DSR, DCD */
 847         pinctrl_uart1_ctrl: uart1ctrlgrp {
 848                 fsl,pins = <
 849                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 850                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 851                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 852                 >;
 853         };
 854
 855         pinctrl_uart2_dce: uart2dcegrp {
 856                 fsl,pins = <
 857                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 858                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 859                 >;
 860         };
 861
 862         /* DTE mode */
 863         pinctrl_uart2_dte: uart2dtegrp {
 864                 fsl,pins = <
 865                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 866                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 867                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 868                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 869                 >;
 870         };
 871
 872         pinctrl_uart4_dce: uart4dcegrp {
 873                 fsl,pins = <
 874                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 875                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 876                 >;
 877         };
 878
 879         /* DTE mode */
 880         pinctrl_uart4_dte: uart4dtegrp {
 881                 fsl,pins = <
 882                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 883                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 884                 >;
 885         };
 886
 887         pinctrl_uart5_dce: uart5dcegrp {
 888                 fsl,pins = <
 889                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 890                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 891                 >;
 892         };
 893
 894         /* DTE mode */
 895         pinctrl_uart5_dte: uart5dtegrp {
 896                 fsl,pins = <
 897                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 898                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 899                 >;
 900         };
 901
 902         pinctrl_usbotg: usbotggrp {
 903                 fsl,pins = <
 904                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 905                 >;
 906         };
 907
 908         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 909                 fsl,pins = <
 910                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 911                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 912                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 913                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 914                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 915                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 916                 >;
 917         };
 918
 919         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 920                 fsl,pins = <
 921                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 922                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 923                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 924                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 925                 >;
 926         };
 927
 928         pinctrl_usdhc2: usdhc2grp {
 929                 fsl,pins = <
 930                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 931                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 932                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 933                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 934                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 935                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 936                 >;
 937         };
 938
 939         pinctrl_usdhc3: usdhc3grp {
 940                 fsl,pins = <
 941                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 942                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 943                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 944                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 945                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 946                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 947                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 948                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 949                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 950                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 951                         /* eMMC reset */
 952                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 953                 >;
 954         };
 955
 956         pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
 957                 fsl,pins = <
 958                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9
 959                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9
 960                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
 961                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
 962                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
 963                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
 964                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
 965                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
 966                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
 967                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
 968                         /* eMMC reset */
 969                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9
 970                 >;
 971         };
 972
 973         pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
 974                 fsl,pins = <
 975                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9
 976                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9
 977                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
 978                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
 979                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
 980                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
 981                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
 982                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
 983                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
 984                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
 985                         /* eMMC reset */
 986                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9
 987                 >;
 988         };
 989 };