arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 reg = <0x10000000 0>;
  53         };
  54
  55         backlight: backlight {
  56                 compatible = "pwm-backlight";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  59                 pwms = <&pwm4 0 5000000>;
  60                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  61                 status = "disabled";
  62         };
  63
  64         reg_module_3v3: regulator-module-3v3 {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "+V3.3";
  67                 regulator-min-microvolt = <3300000>;
  68                 regulator-max-microvolt = <3300000>;
  69                 regulator-always-on;
  70         };
  71
  72         reg_module_3v3_audio: regulator-module-3v3-audio {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "+V3.3_AUDIO";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  81                 compatible = "regulator-fixed";
  82                 pinctrl-names = "default";
  83                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  84                 regulator-name = "usb_otg_vbus";
  85                 regulator-min-microvolt = <5000000>;
  86                 regulator-max-microvolt = <5000000>;
  87                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  88                 enable-active-high;
  89                 status = "disabled";
  90         };
  91
  92         /* on module USB hub */
  93         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
  97                 regulator-name = "usb_host_vbus_hub";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 101                 startup-delay-us = <2000>;
 102                 enable-active-high;
 103                 status = "okay";
 104         };
 105
 106         reg_usb_host_vbus: regulator-usb-host-vbus {
 107                 compatible = "regulator-fixed";
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 110                 regulator-name = "usb_host_vbus";
 111                 regulator-min-microvolt = <5000000>;
 112                 regulator-max-microvolt = <5000000>;
 113                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 114                 enable-active-high;
 115                 vin-supply = <&reg_usb_host_vbus_hub>;
 116                 status = "disabled";
 117         };
 118
 119         sound {
 120                 compatible = "fsl,imx-audio-sgtl5000";
 121                 model = "imx6q-apalis-sgtl5000";
 122                 ssi-controller = <&ssi1>;
 123                 audio-codec = <&codec>;
 124                 audio-routing =
 125                         "LINE_IN", "Line In Jack",
 126                         "MIC_IN", "Mic Jack",
 127                         "Mic Jack", "Mic Bias",
 128                         "Headphone Jack", "HP_OUT";
 129                 mux-int-port = <1>;
 130                 mux-ext-port = <4>;
 131         };
 132
 133         sound_spdif: sound-spdif {
 134                 compatible = "fsl,imx-audio-spdif";
 135                 model = "imx-spdif";
 136                 spdif-controller = <&spdif>;
 137                 spdif-in;
 138                 spdif-out;
 139                 status = "disabled";
 140         };
 141 };
 142
 143 &audmux {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_audmux>;
 146         status = "okay";
 147 };
 148
 149 &can1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_flexcan1>;
 152         status = "disabled";
 153 };
 154
 155 &can2 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_flexcan2>;
 158         status = "disabled";
 159 };
 160
 161 /* Apalis SPI1 */
 162 &ecspi1 {
 163         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_ecspi1>;
 166         status = "disabled";
 167 };
 168
 169 /* Apalis SPI2 */
 170 &ecspi2 {
 171         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_ecspi2>;
 174         status = "disabled";
 175 };
 176
 177 &fec {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_enet>;
 180         phy-mode = "rgmii";
 181         phy-handle = <&ethphy>;
 182         phy-reset-duration = <10>;
 183         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 184         status = "okay";
 185
 186         mdio {
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189
 190                 ethphy: ethernet-phy@7 {
 191                         interrupt-parent = <&gpio1>;
 192                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 193                         reg = <7>;
 194                 };
 195         };
 196 };
 197
 198 &hdmi {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 201         status = "disabled";
 202 };
 203
 204 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 205 &i2c1 {
 206         clock-frequency = <100000>;
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_i2c1>;
 209         status = "disabled";
 210 };
 211
 212 /*
 213  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 214  * touch screen controller
 215  */
 216 &i2c2 {
 217         clock-frequency = <100000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_i2c2>;
 220         status = "okay";
 221
 222         pmic: pfuze100@8 {
 223                 compatible = "fsl,pfuze100";
 224                 reg = <0x08>;
 225
 226                 regulators {
 227                         sw1a_reg: sw1ab {
 228                                 regulator-min-microvolt = <300000>;
 229                                 regulator-max-microvolt = <1875000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                                 regulator-ramp-delay = <6250>;
 233                         };
 234
 235                         sw1c_reg: sw1c {
 236                                 regulator-min-microvolt = <300000>;
 237                                 regulator-max-microvolt = <1875000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                                 regulator-ramp-delay = <6250>;
 241                         };
 242
 243                         sw3a_reg: sw3a {
 244                                 regulator-min-microvolt = <400000>;
 245                                 regulator-max-microvolt = <1975000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                         };
 249
 250                         swbst_reg: swbst {
 251                                 regulator-min-microvolt = <5000000>;
 252                                 regulator-max-microvolt = <5150000>;
 253                                 regulator-boot-on;
 254                                 regulator-always-on;
 255                         };
 256
 257                         snvs_reg: vsnvs {
 258                                 regulator-min-microvolt = <1000000>;
 259                                 regulator-max-microvolt = <3000000>;
 260                                 regulator-boot-on;
 261                                 regulator-always-on;
 262                         };
 263
 264                         vref_reg: vrefddr {
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         vgen1_reg: vgen1 {
 270                                 regulator-min-microvolt = <800000>;
 271                                 regulator-max-microvolt = <1550000>;
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275
 276                         vgen2_reg: vgen2 {
 277                                 regulator-min-microvolt = <800000>;
 278                                 regulator-max-microvolt = <1550000>;
 279                                 regulator-boot-on;
 280                                 regulator-always-on;
 281                         };
 282
 283                         vgen3_reg: vgen3 {
 284                                 regulator-min-microvolt = <1800000>;
 285                                 regulator-max-microvolt = <3300000>;
 286                                 regulator-boot-on;
 287                                 regulator-always-on;
 288                         };
 289
 290                         vgen4_reg: vgen4 {
 291                                 regulator-min-microvolt = <1800000>;
 292                                 regulator-max-microvolt = <1800000>;
 293                                 regulator-boot-on;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen5_reg: vgen5 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-boot-on;
 301                                 regulator-always-on;
 302                         };
 303
 304                         vgen6_reg: vgen6 {
 305                                 regulator-min-microvolt = <1800000>;
 306                                 regulator-max-microvolt = <3300000>;
 307                                 regulator-boot-on;
 308                                 regulator-always-on;
 309                         };
 310                 };
 311         };
 312
 313         codec: sgtl5000@a {
 314                 compatible = "fsl,sgtl5000";
 315                 reg = <0x0a>;
 316                 clocks = <&clks IMX6QDL_CLK_CKO>;
 317                 VDDA-supply = <&reg_module_3v3_audio>;
 318                 VDDIO-supply = <&reg_module_3v3>;
 319                 VDDD-supply = <&vgen4_reg>;
 320         };
 321
 322         /* STMPE811 touch screen controller */
 323         stmpe811@41 {
 324                 compatible = "st,stmpe811";
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&pinctrl_touch_int>;
 327                 reg = <0x41>;
 328                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 329                 interrupt-parent = <&gpio4>;
 330                 interrupt-controller;
 331                 id = <0>;
 332                 blocks = <0x5>;
 333                 irq-trigger = <0x1>;
 334
 335                 stmpe_touchscreen {
 336                         compatible = "st,stmpe-ts";
 337                         /* 3.25 MHz ADC clock speed */
 338                         st,adc-freq = <1>;
 339                         /* 8 sample average control */
 340                         st,ave-ctrl = <3>;
 341                         /* 7 length fractional part in z */
 342                         st,fraction-z = <7>;
 343                         /*
 344                          * 50 mA typical 80 mA max touchscreen drivers
 345                          * current limit value
 346                          */
 347                         st,i-drive = <1>;
 348                         /* 12-bit ADC */
 349                         st,mod-12b = <1>;
 350                         /* internal ADC reference */
 351                         st,ref-sel = <0>;
 352                         /* ADC converstion time: 80 clocks */
 353                         st,sample-time = <4>;
 354                         /* 1 ms panel driver settling time */
 355                         st,settling = <3>;
 356                         /* 5 ms touch detect interrupt delay */
 357                         st,touch-det-delay = <5>;
 358                 };
 359         };
 360 };
 361
 362 /*
 363  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 364  * board)
 365  */
 366 &i2c3 {
 367         clock-frequency = <100000>;
 368         pinctrl-names = "default", "recovery";
 369         pinctrl-0 = <&pinctrl_i2c3>;
 370         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 371         scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
 372         sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 373         status = "disabled";
 374 };
 375
 376 &pwm1 {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_pwm1>;
 379         status = "disabled";
 380 };
 381
 382 &pwm2 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_pwm2>;
 385         status = "disabled";
 386 };
 387
 388 &pwm3 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_pwm3>;
 391         status = "disabled";
 392 };
 393
 394 &pwm4 {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_pwm4>;
 397         status = "disabled";
 398 };
 399
 400 &spdif {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_spdif>;
 403         status = "disabled";
 404 };
 405
 406 &ssi1 {
 407         status = "okay";
 408 };
 409
 410 &uart1 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 413         fsl,dte-mode;
 414         uart-has-rtscts;
 415         status = "disabled";
 416 };
 417
 418 &uart2 {
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&pinctrl_uart2_dte>;
 421         fsl,dte-mode;
 422         uart-has-rtscts;
 423         status = "disabled";
 424 };
 425
 426 &uart4 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_uart4_dte>;
 429         fsl,dte-mode;
 430         status = "disabled";
 431 };
 432
 433 &uart5 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart5_dte>;
 436         fsl,dte-mode;
 437         status = "disabled";
 438 };
 439
 440 &usbotg {
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&pinctrl_usbotg>;
 443         disable-over-current;
 444         status = "disabled";
 445 };
 446
 447 /* MMC1 */
 448 &usdhc1 {
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 451         vqmmc-supply = <&reg_module_3v3>;
 452         bus-width = <8>;
 453         disable-wp;
 454         no-1-8-v;
 455         status = "disabled";
 456 };
 457
 458 /* SD1 */
 459 &usdhc2 {
 460         pinctrl-names = "default";
 461         pinctrl-0 = <&pinctrl_usdhc2>;
 462         vqmmc-supply = <&reg_module_3v3>;
 463         bus-width = <4>;
 464         disable-wp;
 465         no-1-8-v;
 466         status = "disabled";
 467 };
 468
 469 /* eMMC */
 470 &usdhc3 {
 471         pinctrl-names = "default";
 472         pinctrl-0 = <&pinctrl_usdhc3>;
 473         vqmmc-supply = <&reg_module_3v3>;
 474         bus-width = <8>;
 475         no-1-8-v;
 476         non-removable;
 477         status = "okay";
 478 };
 479
 480 &weim {
 481         status = "disabled";
 482 };
 483
 484 &iomuxc {
 485         pinctrl_apalis_gpio1: gpio2io04grp {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 488                 >;
 489         };
 490
 491         pinctrl_apalis_gpio2: gpio2io05grp {
 492                 fsl,pins = <
 493                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 494                 >;
 495         };
 496
 497         pinctrl_apalis_gpio3: gpio2io06grp {
 498                 fsl,pins = <
 499                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 500                 >;
 501         };
 502
 503         pinctrl_apalis_gpio4: gpio2io07grp {
 504                 fsl,pins = <
 505                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 506                 >;
 507         };
 508
 509         pinctrl_apalis_gpio5: gpio6io10grp {
 510                 fsl,pins = <
 511                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 512                 >;
 513         };
 514
 515         pinctrl_apalis_gpio6: gpio6io09grp {
 516                 fsl,pins = <
 517                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 518                 >;
 519         };
 520
 521         pinctrl_apalis_gpio7: gpio1io02grp {
 522                 fsl,pins = <
 523                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 524                 >;
 525         };
 526
 527         pinctrl_apalis_gpio8: gpio1io06grp {
 528                 fsl,pins = <
 529                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 530                 >;
 531         };
 532
 533         pinctrl_audmux: audmuxgrp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 536                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 537                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 538                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 539                         /* SGTL5000 sys_mclk */
 540                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 541                 >;
 542         };
 543
 544         pinctrl_cam_mclk: cammclkgrp {
 545                 fsl,pins = <
 546                         /* CAM sys_mclk */
 547                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 548                 >;
 549         };
 550
 551         pinctrl_ecspi1: ecspi1grp {
 552                 fsl,pins = <
 553                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 554                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 555                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 556                         /* SPI1 cs */
 557                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 558                 >;
 559         };
 560
 561         pinctrl_ecspi2: ecspi2grp {
 562                 fsl,pins = <
 563                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 564                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 565                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 566                         /* SPI2 cs */
 567                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 568                 >;
 569         };
 570
 571         pinctrl_enet: enetgrp {
 572                 fsl,pins = <
 573                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 574                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 575                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 576                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 577                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 578                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 579                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 580                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 581                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 582                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 583                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 584                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 585                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 586                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 587                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 588                         /* Ethernet PHY reset */
 589                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 590                         /* Ethernet PHY interrupt */
 591                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 592                 >;
 593         };
 594
 595         pinctrl_flexcan1: flexcan1grp {
 596                 fsl,pins = <
 597                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 598                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 599                 >;
 600         };
 601
 602         pinctrl_flexcan2: flexcan2grp {
 603                 fsl,pins = <
 604                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 605                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 606                 >;
 607         };
 608
 609         pinctrl_gpio_bl_on: gpioblon {
 610                 fsl,pins = <
 611                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 612                 >;
 613         };
 614
 615         pinctrl_gpio_keys: gpio1io04grp {
 616                 fsl,pins = <
 617                         /* Power button */
 618                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 619                 >;
 620         };
 621
 622         pinctrl_hdmi_cec: hdmicecgrp {
 623                 fsl,pins = <
 624                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 625                 >;
 626         };
 627
 628         pinctrl_hdmi_ddc: hdmiddcgrp {
 629                 fsl,pins = <
 630                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 631                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 632                 >;
 633         };
 634
 635         pinctrl_i2c1: i2c1grp {
 636                 fsl,pins = <
 637                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 638                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 639                 >;
 640         };
 641
 642         pinctrl_i2c2: i2c2grp {
 643                 fsl,pins = <
 644                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 645                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 646                 >;
 647         };
 648
 649         pinctrl_i2c3: i2c3grp {
 650                 fsl,pins = <
 651                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 652                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 653                 >;
 654         };
 655
 656         pinctrl_i2c3_recovery: i2c3recoverygrp {
 657                 fsl,pins = <
 658                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 659                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 660                 >;
 661         };
 662
 663         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 664                 fsl,pins = <
 665                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 666                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 667                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 668                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 669                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 670                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 671                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 672                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 673                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 674                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 675                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 676                 >;
 677         };
 678
 679         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 682                         /* DE */
 683                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 684                         /* HSync */
 685                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 686                         /* VSync */
 687                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 688                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 689                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 690                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 691                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 692                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 693                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 694                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 695                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 696                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 697                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 698                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 699                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 700                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 701                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 702                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 703                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 704                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 705                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 706                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 707                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 708                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 709                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 710                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 711                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 712                 >;
 713         };
 714
 715         pinctrl_ipu2_vdac: ipu2vdacgrp {
 716                 fsl,pins = <
 717                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 718                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 719                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 720                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 721                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 722                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 723                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 724                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 725                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 726                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 727                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 728                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 729                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 730                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 731                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 732                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 733                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 734                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 735                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 736                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 737                 >;
 738         };
 739
 740         pinctrl_mmc_cd: gpiommccdgrp {
 741                 fsl,pins = <
 742                          /* MMC1 CD */
 743                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 744                 >;
 745         };
 746
 747         pinctrl_pwm1: pwm1grp {
 748                 fsl,pins = <
 749                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 750                 >;
 751         };
 752
 753         pinctrl_pwm2: pwm2grp {
 754                 fsl,pins = <
 755                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 756                 >;
 757         };
 758
 759         pinctrl_pwm3: pwm3grp {
 760                 fsl,pins = <
 761                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 762                 >;
 763         };
 764
 765         pinctrl_pwm4: pwm4grp {
 766                 fsl,pins = <
 767                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 768                 >;
 769         };
 770
 771         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 772                 fsl,pins = <
 773                         /* USBH_EN */
 774                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 775                 >;
 776         };
 777
 778         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 779                 fsl,pins = <
 780                         /* USBH_HUB_EN */
 781                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 782                 >;
 783         };
 784
 785         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 786                 fsl,pins = <
 787                         /* USBO1 power en */
 788                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 789                 >;
 790         };
 791
 792         pinctrl_reset_moci: gpioresetmocigrp {
 793                 fsl,pins = <
 794                         /* RESET_MOCI control */
 795                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 796                 >;
 797         };
 798
 799         pinctrl_sd_cd: gpiosdcdgrp {
 800                 fsl,pins = <
 801                         /* SD1 CD */
 802                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 803                 >;
 804         };
 805
 806         pinctrl_spdif: spdifgrp {
 807                 fsl,pins = <
 808                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 809                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 810                 >;
 811         };
 812
 813         pinctrl_touch_int: gpiotouchintgrp {
 814                 fsl,pins = <
 815                         /* STMPE811 interrupt */
 816                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 817                 >;
 818         };
 819
 820         pinctrl_uart1_dce: uart1dcegrp {
 821                 fsl,pins = <
 822                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 823                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 824                 >;
 825         };
 826
 827         /* DTE mode */
 828         pinctrl_uart1_dte: uart1dtegrp {
 829                 fsl,pins = <
 830                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 831                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 832                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 833                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 834                 >;
 835         };
 836
 837         /* Additional DTR, DSR, DCD */
 838         pinctrl_uart1_ctrl: uart1ctrlgrp {
 839                 fsl,pins = <
 840                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 841                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 842                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 843                 >;
 844         };
 845
 846         pinctrl_uart2_dce: uart2dcegrp {
 847                 fsl,pins = <
 848                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 849                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 850                 >;
 851         };
 852
 853         /* DTE mode */
 854         pinctrl_uart2_dte: uart2dtegrp {
 855                 fsl,pins = <
 856                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 857                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 858                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 859                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 860                 >;
 861         };
 862
 863         pinctrl_uart4_dce: uart4dcegrp {
 864                 fsl,pins = <
 865                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 866                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 867                 >;
 868         };
 869
 870         /* DTE mode */
 871         pinctrl_uart4_dte: uart4dtegrp {
 872                 fsl,pins = <
 873                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 874                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 875                 >;
 876         };
 877
 878         pinctrl_uart5_dce: uart5dcegrp {
 879                 fsl,pins = <
 880                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 881                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 882                 >;
 883         };
 884
 885         /* DTE mode */
 886         pinctrl_uart5_dte: uart5dtegrp {
 887                 fsl,pins = <
 888                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 889                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 890                 >;
 891         };
 892
 893         pinctrl_usbotg: usbotggrp {
 894                 fsl,pins = <
 895                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 896                 >;
 897         };
 898
 899         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 900                 fsl,pins = <
 901                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 902                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 903                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 904                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 905                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 906                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 907                 >;
 908         };
 909
 910         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 911                 fsl,pins = <
 912                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 913                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 914                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 915                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 916                 >;
 917         };
 918
 919         pinctrl_usdhc2: usdhc2grp {
 920                 fsl,pins = <
 921                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 922                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 923                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 924                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 925                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 926                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 927                 >;
 928         };
 929
 930         pinctrl_usdhc3: usdhc3grp {
 931                 fsl,pins = <
 932                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 933                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 934                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 935                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 936                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 937                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 938                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 939                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 940                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 941                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 942                         /* eMMC reset */
 943                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 944                 >;
 945         };
 946 };