arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6qdl.dtsi"
  12 #include "imx6q-pinfunc.h"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 792000  1150000
  29                                 396000  950000
  30                         >;
  31                         clock-latency = <61036>; /* two CLK32 periods */
  32                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  33                                  <&clks 17>, <&clks 170>;
  34                         clock-names = "arm", "pll2_pfd2_396m", "step",
  35                                       "pll1_sw", "pll1_sys";
  36                         arm-supply = <&reg_arm>;
  37                         pu-supply = <&reg_pu>;
  38                         soc-supply = <&reg_soc>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                 };
  47
  48                 cpu@2 {
  49                         compatible = "arm,cortex-a9";
  50                         device_type = "cpu";
  51                         reg = <2>;
  52                         next-level-cache = <&L2>;
  53                 };
  54
  55                 cpu@3 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <3>;
  59                         next-level-cache = <&L2>;
  60                 };
  61         };
  62
  63         soc {
  64                 aips-bus@02000000 { /* AIPS1 */
  65                         spba-bus@02000000 {
  66                                 ecspi5: ecspi@02018000 {
  67                                         #address-cells = <1>;
  68                                         #size-cells = <0>;
  69                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  70                                         reg = <0x02018000 0x4000>;
  71                                         interrupts = <0 35 0x04>;
  72                                         clocks = <&clks 116>, <&clks 116>;
  73                                         clock-names = "ipg", "per";
  74                                         status = "disabled";
  75                                 };
  76                         };
  77
  78                         iomuxc: iomuxc@020e0000 {
  79                                 compatible = "fsl,imx6q-iomuxc";
  80                                 reg = <0x020e0000 0x4000>;
  81
  82                                 /* shared pinctrl settings */
  83                                 audmux {
  84                                         pinctrl_audmux_1: audmux-1 {
  85                                                 fsl,pins = <
  86                                                         MX6Q_PAD_SD2_DAT0__AUD4_RXD  0x80000000
  87                                                         MX6Q_PAD_SD2_DAT3__AUD4_TXC  0x80000000
  88                                                         MX6Q_PAD_SD2_DAT2__AUD4_TXD  0x80000000
  89                                                         MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
  90                                                 >;
  91                                         };
  92
  93                                         pinctrl_audmux_2: audmux-2 {
  94                                                 fsl,pins = <
  95                                                         MX6Q_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
  96                                                         MX6Q_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
  97                                                         MX6Q_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
  98                                                         MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
  99                                                 >;
 100                                         };
 101                                 };
 102
 103                                 ecspi1 {
 104                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 105                                                 fsl,pins = <
 106                                                         MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 107                                                         MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 108                                                         MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 109                                                 >;
 110                                         };
 111                                 };
 112
 113                                 ecspi3 {
 114                                         pinctrl_ecspi3_1: ecspi3grp-1 {
 115                                                 fsl,pins = <
 116                                                         MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
 117                                                         MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
 118                                                         MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
 119                                                 >;
 120                                         };
 121                                 };
 122
 123                                 enet {
 124                                         pinctrl_enet_1: enetgrp-1 {
 125                                                 fsl,pins = <
 126                                                         MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 127                                                         MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 128                                                         MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 129                                                         MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 130                                                         MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 131                                                         MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 132                                                         MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 133                                                         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 134                                                         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 135                                                         MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 136                                                         MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 137                                                         MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 138                                                         MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 139                                                         MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 140                                                         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 141                                                         MX6Q_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 142                                                 >;
 143                                         };
 144
 145                                         pinctrl_enet_2: enetgrp-2 {
 146                                                 fsl,pins = <
 147                                                         MX6Q_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
 148                                                         MX6Q_PAD_KEY_COL2__ENET_MDC         0x1b0b0
 149                                                         MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 150                                                         MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 151                                                         MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 152                                                         MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 153                                                         MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 154                                                         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 155                                                         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 156                                                         MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 157                                                         MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 158                                                         MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 159                                                         MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 160                                                         MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 161                                                         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 162                                                 >;
 163                                         };
 164
 165                                         pinctrl_enet_3: enetgrp-3 {
 166                                                 fsl,pins = <
 167                                                         MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 168                                                         MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 169                                                         MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 170                                                         MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 171                                                         MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 172                                                         MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 173                                                         MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 174                                                         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 175                                                         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 176                                                         MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 177                                                         MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 178                                                         MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 179                                                         MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 180                                                         MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 181                                                         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 182                                                         MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 183                                                 >;
 184                                         };
 185                                 };
 186
 187                                 gpmi-nand {
 188                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 189                                                 fsl,pins = <
 190                                                         MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 191                                                         MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 192                                                         MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 193                                                         MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
 194                                                         MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 195                                                         MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 196                                                         MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 197                                                         MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 198                                                         MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 199                                                         MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 200                                                         MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 201                                                         MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 202                                                         MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 203                                                         MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 204                                                         MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 205                                                         MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 206                                                         MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
 207                                                 >;
 208                                         };
 209                                 };
 210
 211                                 i2c1 {
 212                                         pinctrl_i2c1_1: i2c1grp-1 {
 213                                                 fsl,pins = <
 214                                                         MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 215                                                         MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 216                                                 >;
 217                                         };
 218
 219                                         pinctrl_i2c1_2: i2c1grp-2 {
 220                                                 fsl,pins = <
 221                                                         MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 222                                                         MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 223                                                 >;
 224                                         };
 225                                 };
 226
 227                                 i2c2 {
 228                                         pinctrl_i2c2_1: i2c2grp-1 {
 229                                                 fsl,pins = <
 230                                                         MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 231                                                         MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 232                                                 >;
 233                                         };
 234                                 };
 235
 236                                 i2c3 {
 237                                         pinctrl_i2c3_1: i2c3grp-1 {
 238                                                 fsl,pins = <
 239                                                         MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 240                                                         MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 241                                                 >;
 242                                         };
 243                                 };
 244
 245                                 uart1 {
 246                                         pinctrl_uart1_1: uart1grp-1 {
 247                                                 fsl,pins = <
 248                                                         MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 249                                                         MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 250                                                 >;
 251                                         };
 252                                 };
 253
 254                                 uart2 {
 255                                         pinctrl_uart2_1: uart2grp-1 {
 256                                                 fsl,pins = <
 257                                                         MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
 258                                                         MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 259                                                 >;
 260                                         };
 261                                 };
 262
 263                                 uart4 {
 264                                         pinctrl_uart4_1: uart4grp-1 {
 265                                                 fsl,pins = <
 266                                                         MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 267                                                         MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 268                                                 >;
 269                                         };
 270                                 };
 271
 272                                 usbotg {
 273                                         pinctrl_usbotg_1: usbotggrp-1 {
 274                                                 fsl,pins = <
 275                                                         MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
 276                                                 >;
 277                                         };
 278
 279                                         pinctrl_usbotg_2: usbotggrp-2 {
 280                                                 fsl,pins = <
 281                                                         MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 282                                                 >;
 283                                         };
 284                                 };
 285
 286                                 usdhc2 {
 287                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 288                                                 fsl,pins = <
 289                                                         MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
 290                                                         MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
 291                                                         MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
 292                                                         MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
 293                                                         MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
 294                                                         MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
 295                                                         MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
 296                                                         MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
 297                                                         MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
 298                                                         MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
 299                                                 >;
 300                                         };
 301
 302                                         pinctrl_usdhc2_2: usdhc2grp-2 {
 303                                                 fsl,pins = <
 304                                                         MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
 305                                                         MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
 306                                                         MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
 307                                                         MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
 308                                                         MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
 309                                                         MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
 310                                                 >;
 311                                         };
 312                                 };
 313
 314                                 usdhc3 {
 315                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 316                                                 fsl,pins = <
 317                                                         MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
 318                                                         MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
 319                                                         MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
 320                                                         MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
 321                                                         MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
 322                                                         MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
 323                                                         MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
 324                                                         MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
 325                                                         MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
 326                                                         MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
 327                                                 >;
 328                                         };
 329
 330                                         pinctrl_usdhc3_2: usdhc3grp-2 {
 331                                                 fsl,pins = <
 332                                                         MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
 333                                                         MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
 334                                                         MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
 335                                                         MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
 336                                                         MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
 337                                                         MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
 338                                                 >;
 339                                         };
 340                                 };
 341
 342                                 usdhc4 {
 343                                         pinctrl_usdhc4_1: usdhc4grp-1 {
 344                                                 fsl,pins = <
 345                                                         MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
 346                                                         MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
 347                                                         MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
 348                                                         MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
 349                                                         MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
 350                                                         MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
 351                                                         MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
 352                                                         MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
 353                                                         MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
 354                                                         MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
 355                                                 >;
 356                                         };
 357
 358                                         pinctrl_usdhc4_2: usdhc4grp-2 {
 359                                                 fsl,pins = <
 360                                                         MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
 361                                                         MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
 362                                                         MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
 363                                                         MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
 364                                                         MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
 365                                                         MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
 366                                                 >;
 367                                         };
 368                                 };
 369
 370                                 weim {
 371                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
 372                                                 fsl,pins = <
 373                                                         MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 374                                                 >;
 375                                         };
 376
 377                                         pinctrl_weim_nor_1: weimnorgrp-1 {
 378                                                 fsl,pins = <
 379                                                         MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
 380                                                         MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
 381                                                         MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 382                                                         /* data */
 383                                                         MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
 384                                                         MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
 385                                                         MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
 386                                                         MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
 387                                                         MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
 388                                                         MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
 389                                                         MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
 390                                                         MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
 391                                                         MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
 392                                                         MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
 393                                                         MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
 394                                                         MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
 395                                                         MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
 396                                                         MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
 397                                                         MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
 398                                                         MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
 399                                                         /* address */
 400                                                         MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
 401                                                         MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
 402                                                         MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
 403                                                         MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
 404                                                         MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
 405                                                         MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
 406                                                         MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
 407                                                         MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
 408                                                         MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
 409                                                         MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
 410                                                         MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
 411                                                         MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
 412                                                         MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
 413                                                         MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
 414                                                         MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
 415                                                         MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
 416                                                         MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
 417                                                         MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
 418                                                         MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
 419                                                         MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
 420                                                         MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
 421                                                         MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
 422                                                         MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
 423                                                         MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
 424                                                 >;
 425                                         };
 426
 427                                 };
 428                         };
 429                 };
 430
 431                 ipu2: ipu@02800000 {
 432                         #crtc-cells = <1>;
 433                         compatible = "fsl,imx6q-ipu";
 434                         reg = <0x02800000 0x400000>;
 435                         interrupts = <0 8 0x4 0 7 0x4>;
 436                         clocks = <&clks 133>, <&clks 134>, <&clks 137>;
 437                         clock-names = "bus", "di0", "di1";
 438                         resets = <&src 4>;
 439                 };
 440         };
 441 };
 442
 443 &ldb {
 444         clocks = <&clks 33>, <&clks 34>,
 445                  <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
 446                  <&clks 135>, <&clks 136>;
 447         clock-names = "di0_pll", "di1_pll",
 448                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 449                       "di0", "di1";
 450
 451         lvds-channel@0 {
 452                 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
 453         };
 454
 455         lvds-channel@1 {
 456                 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
 457         };
 458 };