arch/arm/boot/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         clocks = <&clks IMX6QDL_CLK_ARM>,
  42                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  43                                  <&clks IMX6QDL_CLK_STEP>,
  44                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  46                         clock-names = "arm", "pll2_pfd2_396m", "step",
  47                                       "pll1_sw", "pll1_sys";
  48                         arm-supply = <&reg_arm>;
  49                         pu-supply = <&reg_pu>;
  50                         soc-supply = <&reg_soc>;
  51                 };
  52
  53                 cpu@1 {
  54                         compatible = "arm,cortex-a9";
  55                         device_type = "cpu";
  56                         reg = <1>;
  57                         next-level-cache = <&L2>;
  58                 };
  59
  60                 cpu@2 {
  61                         compatible = "arm,cortex-a9";
  62                         device_type = "cpu";
  63                         reg = <2>;
  64                         next-level-cache = <&L2>;
  65                 };
  66
  67                 cpu@3 {
  68                         compatible = "arm,cortex-a9";
  69                         device_type = "cpu";
  70                         reg = <3>;
  71                         next-level-cache = <&L2>;
  72                 };
  73         };
  74
  75         soc {
  76                 ocram: sram@900000 {
  77                         compatible = "mmio-sram";
  78                         reg = <0x00900000 0x40000>;
  79                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  80                 };
  81
  82                 aips-bus@2000000 { /* AIPS1 */
  83                         spba-bus@2000000 {
  84                                 ecspi5: ecspi@2018000 {
  85                                         #address-cells = <1>;
  86                                         #size-cells = <0>;
  87                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  88                                         reg = <0x02018000 0x4000>;
  89                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  90                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
  91                                                  <&clks IMX6Q_CLK_ECSPI5>;
  92                                         clock-names = "ipg", "per";
  93                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
  94                                         dma-names = "rx", "tx";
  95                                         status = "disabled";
  96                                 };
  97                         };
  98
  99                         iomuxc: iomuxc@20e0000 {
 100                                 compatible = "fsl,imx6q-iomuxc";
 101                         };
 102                 };
 103
 104                 sata: sata@2200000 {
 105                         compatible = "fsl,imx6q-ahci";
 106                         reg = <0x02200000 0x4000>;
 107                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&clks IMX6QDL_CLK_SATA>,
 109                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 110                                  <&clks IMX6QDL_CLK_AHB>;
 111                         clock-names = "sata", "sata_ref", "ahb";
 112                         status = "disabled";
 113                 };
 114
 115                 gpu_vg: gpu@2204000 {
 116                         compatible = "vivante,gc";
 117                         reg = <0x02204000 0x4000>;
 118                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 120                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 121                         clock-names = "bus", "core";
 122                         power-domains = <&pd_pu>;
 123                 };
 124
 125                 ipu2: ipu@2800000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         compatible = "fsl,imx6q-ipu";
 129                         reg = <0x02800000 0x400000>;
 130                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 133                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 134                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 135                         clock-names = "bus", "di0", "di1";
 136                         resets = <&src 4>;
 137
 138                         ipu2_csi0: port@0 {
 139                                 reg = <0>;
 140
 141                                 ipu2_csi0_from_mipi_vc2: endpoint {
 142                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 143                                 };
 144                         };
 145
 146                         ipu2_csi1: port@1 {
 147                                 reg = <1>;
 148
 149                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 150                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 151                                 };
 152                         };
 153
 154                         ipu2_di0: port@2 {
 155                                 #address-cells = <1>;
 156                                 #size-cells = <0>;
 157                                 reg = <2>;
 158
 159                                 ipu2_di0_disp0: endpoint@0 {
 160                                         reg = <0>;
 161                                 };
 162
 163                                 ipu2_di0_hdmi: endpoint@1 {
 164                                         reg = <1>;
 165                                         remote-endpoint = <&hdmi_mux_2>;
 166                                 };
 167
 168                                 ipu2_di0_mipi: endpoint@2 {
 169                                         reg = <2>;
 170                                         remote-endpoint = <&mipi_mux_2>;
 171                                 };
 172
 173                                 ipu2_di0_lvds0: endpoint@3 {
 174                                         reg = <3>;
 175                                         remote-endpoint = <&lvds0_mux_2>;
 176                                 };
 177
 178                                 ipu2_di0_lvds1: endpoint@4 {
 179                                         reg = <4>;
 180                                         remote-endpoint = <&lvds1_mux_2>;
 181                                 };
 182                         };
 183
 184                         ipu2_di1: port@3 {
 185                                 #address-cells = <1>;
 186                                 #size-cells = <0>;
 187                                 reg = <3>;
 188
 189                                 ipu2_di1_hdmi: endpoint@1 {
 190                                         reg = <1>;
 191                                         remote-endpoint = <&hdmi_mux_3>;
 192                                 };
 193
 194                                 ipu2_di1_mipi: endpoint@2 {
 195                                         reg = <2>;
 196                                         remote-endpoint = <&mipi_mux_3>;
 197                                 };
 198
 199                                 ipu2_di1_lvds0: endpoint@3 {
 200                                         reg = <3>;
 201                                         remote-endpoint = <&lvds0_mux_3>;
 202                                 };
 203
 204                                 ipu2_di1_lvds1: endpoint@4 {
 205                                         reg = <4>;
 206                                         remote-endpoint = <&lvds1_mux_3>;
 207                                 };
 208                         };
 209                 };
 210         };
 211
 212         capture-subsystem {
 213                 compatible = "fsl,imx-capture-subsystem";
 214                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 215         };
 216
 217         display-subsystem {
 218                 compatible = "fsl,imx-display-subsystem";
 219                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 220         };
 221 };
 222
 223 &gpio1 {
 224         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 225                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 226                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 227                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 228                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 229                       <&iomuxc 22 116 10>;
 230 };
 231
 232 &gpio2 {
 233         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 234                       <&iomuxc 31  44  1>;
 235 };
 236
 237 &gpio3 {
 238         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 239 };
 240
 241 &gpio4 {
 242         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 243 };
 244
 245 &gpio5 {
 246         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 247                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 248 };
 249
 250 &gpio6 {
 251         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 252                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 253                       <&iomuxc 31  86 1>;
 254 };
 255
 256 &gpio7 {
 257         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 258 };
 259
 260 &gpr {
 261         ipu1_csi0_mux {
 262                 compatible = "video-mux";
 263                 mux-controls = <&mux 0>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266
 267                 port@0 {
 268                         reg = <0>;
 269
 270                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 271                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 272                         };
 273                 };
 274
 275                 port@1 {
 276                         reg = <1>;
 277
 278                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 279                         };
 280                 };
 281
 282                 port@2 {
 283                         reg = <2>;
 284
 285                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 286                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 287                         };
 288                 };
 289         };
 290
 291         ipu2_csi1_mux {
 292                 compatible = "video-mux";
 293                 mux-controls = <&mux 1>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296
 297                 port@0 {
 298                         reg = <0>;
 299
 300                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 301                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 302                         };
 303                 };
 304
 305                 port@1 {
 306                         reg = <1>;
 307
 308                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 309                         };
 310                 };
 311
 312                 port@2 {
 313                         reg = <2>;
 314
 315                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 316                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 317                         };
 318                 };
 319         };
 320 };
 321
 322 &hdmi {
 323         compatible = "fsl,imx6q-hdmi";
 324
 325         port@2 {
 326                 reg = <2>;
 327
 328                 hdmi_mux_2: endpoint {
 329                         remote-endpoint = <&ipu2_di0_hdmi>;
 330                 };
 331         };
 332
 333         port@3 {
 334                 reg = <3>;
 335
 336                 hdmi_mux_3: endpoint {
 337                         remote-endpoint = <&ipu2_di1_hdmi>;
 338                 };
 339         };
 340 };
 341
 342 &ipu1_csi1 {
 343         ipu1_csi1_from_mipi_vc1: endpoint {
 344                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 345         };
 346 };
 347
 348 &ldb {
 349         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 350                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 351                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 352                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 353         clock-names = "di0_pll", "di1_pll",
 354                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 355                       "di0", "di1";
 356
 357         lvds-channel@0 {
 358                 port@2 {
 359                         reg = <2>;
 360
 361                         lvds0_mux_2: endpoint {
 362                                 remote-endpoint = <&ipu2_di0_lvds0>;
 363                         };
 364                 };
 365
 366                 port@3 {
 367                         reg = <3>;
 368
 369                         lvds0_mux_3: endpoint {
 370                                 remote-endpoint = <&ipu2_di1_lvds0>;
 371                         };
 372                 };
 373         };
 374
 375         lvds-channel@1 {
 376                 port@2 {
 377                         reg = <2>;
 378
 379                         lvds1_mux_2: endpoint {
 380                                 remote-endpoint = <&ipu2_di0_lvds1>;
 381                         };
 382                 };
 383
 384                 port@3 {
 385                         reg = <3>;
 386
 387                         lvds1_mux_3: endpoint {
 388                                 remote-endpoint = <&ipu2_di1_lvds1>;
 389                         };
 390                 };
 391         };
 392 };
 393
 394 &mipi_csi {
 395         port@1 {
 396                 reg = <1>;
 397
 398                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 399                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 400                 };
 401         };
 402
 403         port@2 {
 404                 reg = <2>;
 405
 406                 mipi_vc1_to_ipu1_csi1: endpoint {
 407                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 408                 };
 409         };
 410
 411         port@3 {
 412                 reg = <3>;
 413
 414                 mipi_vc2_to_ipu2_csi0: endpoint {
 415                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 416                 };
 417         };
 418
 419         port@4 {
 420                 reg = <4>;
 421
 422                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 423                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 424                 };
 425         };
 426 };
 427
 428 &mipi_dsi {
 429         ports {
 430                 port@2 {
 431                         reg = <2>;
 432
 433                         mipi_mux_2: endpoint {
 434                                 remote-endpoint = <&ipu2_di0_mipi>;
 435                         };
 436                 };
 437
 438                 port@3 {
 439                         reg = <3>;
 440
 441                         mipi_mux_3: endpoint {
 442                                 remote-endpoint = <&ipu2_di1_mipi>;
 443                         };
 444                 };
 445         };
 446 };
 447
 448 &mux {
 449         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 450                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 451                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 452                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 453                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 454                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 455                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 456 };
 457
 458 &vpu {
 459         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 460 };