arch/arm/boot/dts/imx6q-udoo.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 /dts-v1/;
  13 #include "imx6q.dtsi"
  14
  15 / {
  16         model = "Udoo i.MX6 Quad Board";
  17         compatible = "udoo,imx6q-udoo", "fsl,imx6q";
  18
  19         memory {
  20                 reg = <0x10000000 0x40000000>;
  21         };
  22 };
  23
  24 &fec {
  25         pinctrl-names = "default";
  26         pinctrl-0 = <&pinctrl_enet>;
  27         phy-mode = "rgmii";
  28         status = "okay";
  29 };
  30
  31 &iomuxc {
  32         imx6q-udoo {
  33                 pinctrl_enet: enetgrp {
  34                         fsl,pins = <
  35                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
  36                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
  37                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
  38                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
  39                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
  40                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
  41                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
  42                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
  43                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
  44                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
  45                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
  46                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
  47                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
  48                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
  49                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
  50                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
  51                         >;
  52                 };
  53
  54                 pinctrl_uart2: uart2grp {
  55                         fsl,pins = <
  56                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
  57                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
  58                         >;
  59                 };
  60
  61                 pinctrl_usdhc3: usdhc3grp {
  62                         fsl,pins = <
  63                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
  64                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
  65                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
  66                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
  67                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
  68                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
  69                         >;
  70                 };
  71         };
  72 };
  73
  74 &sata {
  75         status = "okay";
  76 };
  77
  78 &uart2 {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_uart2>;
  81         status = "okay";
  82 };
  83
  84 &usdhc3 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_usdhc3>;
  87         non-removable;
  88         status = "okay";
  89 };