arch/arm/boot/dts/imx6q-tbs2910.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2014 Soeren Moch <smoch@web.de>
   4
   5 /dts-v1/;
   6
   7 #include "imx6q.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10
  11 / {
  12         model = "TBS2910 Matrix ARM mini PC";
  13         compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory@10000000 {
  20                 device_type = "memory";
  21                 reg = <0x10000000 0x80000000>;
  22         };
  23
  24         fan {
  25                 compatible = "gpio-fan";
  26                 pinctrl-names = "default";
  27                 pinctrl-0 = <&pinctrl_gpio_fan>;
  28                 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
  29                 gpio-fan,speed-map = <0    0
  30                                       3000 1>;
  31         };
  32
  33         ir_recv {
  34                 compatible = "gpio-ir-receiver";
  35                 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
  36                 pinctrl-names = "default";
  37                 pinctrl-0 = <&pinctrl_ir>;
  38         };
  39
  40         leds {
  41                 compatible = "gpio-leds";
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_gpio_leds>;
  44
  45                 blue {
  46                         label = "blue_status_led";
  47                         gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  48                         default-state = "keep";
  49                 };
  50         };
  51
  52         reg_2p5v: regulator-2p5v {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "2P5V";
  55                 regulator-min-microvolt = <2500000>;
  56                 regulator-max-microvolt = <2500000>;
  57         };
  58
  59         reg_3p3v: regulator-3p3v {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "3P3V";
  62                 regulator-min-microvolt = <3300000>;
  63                 regulator-max-microvolt = <3300000>;
  64         };
  65
  66         reg_5p0v: regulator-5p0v {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "5P0V";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71         };
  72
  73         sound-sgtl5000 {
  74                 audio-codec = <&sgtl5000>;
  75                 audio-routing =
  76                         "MIC_IN", "Mic Jack",
  77                         "Mic Jack", "Mic Bias",
  78                         "Headphone Jack", "HP_OUT";
  79                 compatible = "fsl,imx-audio-sgtl5000";
  80                 model = "On-board Codec";
  81                 mux-ext-port = <3>;
  82                 mux-int-port = <1>;
  83                 ssi-controller = <&ssi1>;
  84         };
  85
  86         sound-spdif {
  87                 compatible = "fsl,imx-audio-spdif";
  88                 model = "On-board SPDIF";
  89                 spdif-controller = <&spdif>;
  90                 spdif-out;
  91         };
  92 };
  93
  94 &audmux {
  95         status = "okay";
  96 };
  97
  98 &fec {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_enet>;
 101         phy-mode = "rgmii";
 102         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 103         status = "okay";
 104 };
 105
 106 &hdmi {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_hdmi>;
 109         ddc-i2c-bus = <&i2c2>;
 110         status = "okay";
 111 };
 112
 113 &i2c1 {
 114         clock-frequency = <100000>;
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_i2c1>;
 117         status = "okay";
 118
 119         sgtl5000: sgtl5000@a {
 120                 clocks = <&clks IMX6QDL_CLK_CKO>;
 121                 compatible = "fsl,sgtl5000";
 122                 pinctrl-names = "default";
 123                 pinctrl-0 = <&pinctrl_sgtl5000>;
 124                 reg = <0x0a>;
 125                 VDDA-supply = <&reg_2p5v>;
 126                 VDDIO-supply = <&reg_3p3v>;
 127         };
 128 };
 129
 130 &i2c2 {
 131         clock-frequency = <100000>;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_i2c2>;
 134         status = "okay";
 135 };
 136
 137 &i2c3 {
 138         clock-frequency = <100000>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_i2c3>;
 141         status = "okay";
 142
 143         rtc: ds1307@68 {
 144                 compatible = "dallas,ds1307";
 145                 reg = <0x68>;
 146         };
 147 };
 148
 149 &pcie {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_pcie>;
 152         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 153         status = "okay";
 154 };
 155
 156 &sata {
 157         fsl,transmit-level-mV = <1104>;
 158         fsl,transmit-boost-mdB = <3330>;
 159         fsl,transmit-atten-16ths = <16>;
 160         fsl,receive-eq-mdB = <3000>;
 161         status = "okay";
 162 };
 163
 164 &snvs_poweroff {
 165         status = "okay";
 166 };
 167
 168 &spdif {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_spdif>;
 171         status = "okay";
 172 };
 173
 174 &ssi1 {
 175         status = "okay";
 176 };
 177
 178 &uart1 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_uart1>;
 181         status = "okay";
 182 };
 183
 184 &uart2 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart2>;
 187         status = "okay";
 188 };
 189
 190 &usbh1 {
 191         vbus-supply = <&reg_5p0v>;
 192         status = "okay";
 193 };
 194
 195 &usbotg {
 196         vbus-supply = <&reg_5p0v>;
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_usbotg>;
 199         disable-over-current;
 200         status = "okay";
 201 };
 202
 203 &usdhc2 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_usdhc2>;
 206         bus-width = <4>;
 207         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 208         vmmc-supply = <&reg_3p3v>;
 209         vqmmc-supply = <&reg_3p3v>;
 210         voltage-ranges = <3300 3300>;
 211         no-1-8-v;
 212         status = "okay";
 213 };
 214
 215 &usdhc3 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_usdhc3>;
 218         bus-width = <4>;
 219         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 220         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 221         vmmc-supply = <&reg_3p3v>;
 222         vqmmc-supply = <&reg_3p3v>;
 223         voltage-ranges = <3300 3300>;
 224         no-1-8-v;
 225         status = "okay";
 226 };
 227
 228 &usdhc4 {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_usdhc4>;
 231         bus-width = <8>;
 232         vmmc-supply = <&reg_3p3v>;
 233         vqmmc-supply = <&reg_3p3v>;
 234         voltage-ranges = <3300 3300>;
 235         non-removable;
 236         no-1-8-v;
 237         status = "okay";
 238 };
 239
 240 &iomuxc {
 241         pinctrl_enet: enetgrp {
 242                 fsl,pins = <
 243                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 244                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 245                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
 246                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
 247                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
 248                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
 249                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
 250                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 251                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 252                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 253                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 254                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 255                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 256                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 257                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 258                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 259                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
 260                 >;
 261         };
 262
 263         pinctrl_gpio_fan: gpiofangrp {
 264                 fsl,pins = <
 265                         MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
 266                 >;
 267         };
 268
 269         pinctrl_gpio_leds: gpioledsgrp {
 270                 fsl,pins = <
 271                         MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
 272                 >;
 273         };
 274
 275         pinctrl_hdmi: hdmigrp {
 276                 fsl,pins = <
 277                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 278                 >;
 279         };
 280
 281         pinctrl_i2c1: i2c1grp {
 282                 fsl,pins = <
 283                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
 284                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
 285                 >;
 286         };
 287
 288         pinctrl_i2c2: i2c2grp {
 289                 fsl,pins = <
 290                         MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
 291                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
 292                 >;
 293         };
 294
 295         pinctrl_i2c3: i2c3grp {
 296                 fsl,pins = <
 297                         MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
 298                         MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
 299                 >;
 300         };
 301
 302         pinctrl_ir: irgrp {
 303                 fsl,pins = <
 304                         MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
 305                 >;
 306         };
 307
 308         pinctrl_pcie: pciegrp {
 309                 fsl,pins = <
 310                         MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
 311                 >;
 312         };
 313
 314         pinctrl_sgtl5000: sgtl5000grp {
 315                 fsl,pins = <
 316                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
 317                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
 318                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
 319                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
 320                         MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
 321                 >;
 322         };
 323
 324         pinctrl_spdif: spdifgrp {
 325                 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
 326                 >;
 327         };
 328
 329         pinctrl_uart1: uart1grp {
 330                 fsl,pins = <
 331                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
 332                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
 333                 >;
 334         };
 335
 336         pinctrl_uart2: uart2grp {
 337                 fsl,pins = <
 338                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
 339                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
 340                 >;
 341         };
 342
 343         pinctrl_usbotg: usbotggrp {
 344                 fsl,pins = <
 345                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
 346                 >;
 347         };
 348
 349         pinctrl_usdhc2: usdhc2grp {
 350                 fsl,pins = <
 351                         MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
 352                         MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
 353                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
 354                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
 355                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
 356                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
 357                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
 358                 >;
 359         };
 360
 361         pinctrl_usdhc3: usdhc3grp {
 362                 fsl,pins = <
 363                         MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
 364                         MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
 365                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
 366                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
 367                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
 368                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
 369                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
 370                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
 371                 >;
 372         };
 373
 374         pinctrl_usdhc4: usdhc4grp {
 375                 fsl,pins = <
 376                         MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
 377                         MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
 378                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
 379                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
 380                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
 381                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
 382                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
 383                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
 384                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
 385                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
 386                 >;
 387         };
 388 };