arch/arm/boot/dts/imx6q-pistachio.dts

   1 /*
   2  * Copyright (C) 2017 NutsBoard.Org
   3  *
   4  * Author: Wig Cheng <onlywig@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48 #include <dt-bindings/input/input.h>
  49 #include "imx6q.dtsi"
  50
  51 / {
  52         model = "NutsBoard i.MX6 Quad Pistachio board";
  53         compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q";
  54
  55         chosen {
  56                 stdout-path = &uart4;
  57         };
  58
  59         memory@10000000 {
  60                 device_type = "memory";
  61                 reg = <0x10000000 0x80000000>;
  62         };
  63
  64         reg_3p3v: regulator-3p3v {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "3P3V";
  67                 regulator-min-microvolt = <3300000>;
  68                 regulator-max-microvolt = <3300000>;
  69         };
  70
  71         reg_1p8v: regulator-1p8v {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "1P8V";
  74                 regulator-min-microvolt = <1800000>;
  75                 regulator-max-microvolt = <1800000>;
  76         };
  77
  78         wlan_en_reg: regulator-wlan_en {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "wlan-en-regulator";
  81                 regulator-min-microvolt = <1800000>;
  82                 regulator-max-microvolt = <1800000>;
  83                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  84                 startup-delay-us = <70000>;
  85                 enable-active-high;
  86         };
  87
  88         reg_usb_otg_vbus: regulator-usb_vbus {
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "usb_otg_vbus";
  91                 regulator-min-microvolt = <5000000>;
  92                 regulator-max-microvolt = <5000000>;
  93                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  94                 enable-active-high;
  95                 vin-supply = <&swbst_reg>;
  96         };
  97
  98         gpio-keys {
  99                 compatible = "gpio-keys";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_gpio_keys>;
 102
 103                 power {
 104                         label = "Power Button";
 105                         gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 106                         wakeup-source;
 107                         linux,code = <KEY_POWER>;
 108                 };
 109         };
 110
 111         sound {
 112                 compatible = "fsl,imx-sgtl5000",
 113                            "fsl,imx-audio-sgtl5000";
 114                 model = "audio-sgtl5000";
 115                 ssi-controller = <&ssi1>;
 116                 audio-codec = <&codec>;
 117                 audio-routing =
 118                         "MIC_IN", "Mic Jack",
 119                         "Mic Jack", "Mic Bias",
 120                         "Headphone Jack", "HP_OUT";
 121                 mux-int-port = <1>;
 122                 mux-ext-port = <3>;
 123         };
 124
 125         backlight_lvds: backlight-lvds {
 126                 compatible = "pwm-backlight";
 127                 pwms = <&pwm1 0 50000>;
 128                 brightness-levels = <
 129                         0  /*1  2  3  4  5  6*/  7  8  9
 130                         10 11 12 13 14 15 16 17 18 19
 131                         20 21 22 23 24 25 26 27 28 29
 132                         30 31 32 33 34 35 36 37 38 39
 133                         40 41 42 43 44 45 46 47 48 49
 134                         50 51 52 53 54 55 56 57 58 59
 135                         60 61 62 63 64 65 66 67 68 69
 136                         70 71 72 73 74 75 76 77 78 79
 137                         80 81 82 83 84 85 86 87 88 89
 138                         90 91 92 93 94 95 96 97 98 99
 139                         100
 140                 >;
 141                 default-brightness-level = <94>;
 142                 status = "okay";
 143         };
 144
 145         panel {
 146                 compatible = "hannstar,hsd100pxn1";
 147                 backlight = <&backlight_lvds>;
 148
 149                 port {
 150                         panel_in: endpoint {
 151                                 remote-endpoint = <&lvds0_out>;
 152                         };
 153                 };
 154         };
 155 };
 156
 157 &audmux {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_audmux>;
 160         status = "okay";
 161 };
 162
 163 &can2 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_flexcan2>;
 166         status = "okay";
 167 };
 168
 169 &clks {
 170         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 171                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 172         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 173                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 174 };
 175
 176 &fec {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_enet>;
 179         phy-mode = "rgmii";
 180         status = "okay";
 181 };
 182
 183 &hdmi {
 184         ddc-i2c-bus = <&i2c2>;
 185         status = "okay";
 186 };
 187
 188 &i2c1 {
 189         clock-frequency = <100000>;
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_i2c1>;
 192         status = "okay";
 193
 194         codec: sgtl5000@a {
 195                 compatible = "fsl,sgtl5000";
 196                 pinctrl-names = "default";
 197                 pinctrl-0 = <&pinctrl_i2c1_sgtl5000>;
 198                 reg = <0x0a>;
 199                 clocks = <&clks IMX6QDL_CLK_CKO>;
 200                 VDDA-supply = <&reg_1p8v>;
 201                 VDDIO-supply = <&reg_1p8v>;
 202         };
 203 };
 204
 205 &i2c2 {
 206         clock-frequency = <100000>;
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_i2c2>;
 209         status = "okay";
 210
 211         pmic: pfuze100@8 {
 212                 compatible = "fsl,pfuze100";
 213                 reg = <0x08>;
 214
 215                 regulators {
 216                         sw1a_reg: sw1ab {
 217                                 regulator-min-microvolt = <300000>;
 218                                 regulator-max-microvolt = <1875000>;
 219                                 regulator-boot-on;
 220                                 regulator-always-on;
 221                                 regulator-ramp-delay = <6250>;
 222                         };
 223
 224                         sw1c_reg: sw1c {
 225                                 regulator-min-microvolt = <300000>;
 226                                 regulator-max-microvolt = <1875000>;
 227                                 regulator-boot-on;
 228                                 regulator-always-on;
 229                                 regulator-ramp-delay = <6250>;
 230                         };
 231
 232                         sw2_reg: sw2 {
 233                                 regulator-min-microvolt = <800000>;
 234                                 regulator-max-microvolt = <3300000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                                 regulator-ramp-delay = <6250>;
 238                         };
 239
 240                         sw3a_reg: sw3a {
 241                                 regulator-min-microvolt = <400000>;
 242                                 regulator-max-microvolt = <1975000>;
 243                                 regulator-boot-on;
 244                                 regulator-always-on;
 245                         };
 246
 247                         sw3b_reg: sw3b {
 248                                 regulator-min-microvolt = <400000>;
 249                                 regulator-max-microvolt = <1975000>;
 250                                 regulator-boot-on;
 251                                 regulator-always-on;
 252                         };
 253
 254                         sw4_reg: sw4 {
 255                                 regulator-min-microvolt = <800000>;
 256                                 regulator-max-microvolt = <3300000>;
 257                         };
 258
 259                         swbst_reg: swbst {
 260                                 regulator-min-microvolt = <5000000>;
 261                                 regulator-max-microvolt = <5150000>;
 262                         };
 263
 264                         snvs_reg: vsnvs {
 265                                 regulator-min-microvolt = <1000000>;
 266                                 regulator-max-microvolt = <3000000>;
 267                                 regulator-boot-on;
 268                                 regulator-always-on;
 269                         };
 270
 271                         vref_reg: vrefddr {
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275
 276                         vgen1_reg: vgen1 {
 277                                 regulator-min-microvolt = <800000>;
 278                                 regulator-max-microvolt = <1550000>;
 279                         };
 280
 281                         vgen2_reg: vgen2 {
 282                                 regulator-min-microvolt = <800000>;
 283                                 regulator-max-microvolt = <1550000>;
 284                         };
 285
 286                         vgen3_reg: vgen3 {
 287                                 regulator-min-microvolt = <1800000>;
 288                                 regulator-max-microvolt = <3300000>;
 289                         };
 290
 291                         vgen4_reg: vgen4 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen5_reg: vgen5 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-always-on;
 301                         };
 302                         vgen6_reg: vgen6 {
 303                                 regulator-min-microvolt = <1800000>;
 304                                 regulator-max-microvolt = <3300000>;
 305                                 regulator-always-on;
 306                         };
 307                 };
 308         };
 309
 310         ar1021@4d {
 311                 compatible = "microchip,ar1021-i2c";
 312                 reg = <0x4d>;
 313                 interrupt-parent = <&gpio6>;
 314                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 315         };
 316 };
 317
 318 &i2c3 {
 319         clock-frequency = <100000>;
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_i2c3>;
 322         status = "okay";
 323 };
 324
 325 &iomuxc {
 326         pinctrl-names = "default";
 327
 328         pinctrl_hog: hoggrp {
 329                 fsl,pins = <
 330                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0  /*pcie power*/
 331                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x1b0b0   /*LCD power*/
 332                         MX6QDL_PAD_EIM_D16__GPIO3_IO16  0x1b0b0   /*backlight power*/
 333                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1 /*SD3 CD pin*/
 334                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/
 335                         MX6QDL_PAD_EIM_A16__GPIO2_IO22  0x1b0b0 /*touch reset*/
 336                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b01 /*touch irq*/
 337                         MX6QDL_PAD_GPIO_7__GPIO1_IO07    0x1b0b0/*backlight pwr*/
 338                         MX6QDL_PAD_GPIO_16__GPIO7_IO11  0x1b0b0 /*gpio 5V_1*/
 339                         MX6QDL_PAD_EIM_A19__GPIO2_IO19  0x1b0b0 /*gpio 5V_2*/
 340                         MX6QDL_PAD_EIM_A24__GPIO5_IO04  0x1b0b0 /*gpio 5V_3*/
 341                         MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0 /*gpio 5V_4*/
 342                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0 /*AUX_5V_EN*/
 343                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0 /*AUX_5VB_EN*/
 344                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0 /*AUX_3V3_EN*/
 345                         MX6QDL_PAD_EIM_D21__GPIO3_IO21  0x1b0b0 /*I2C expander pwr*/
 346                 >;
 347         };
 348
 349         pinctrl_audmux: audmuxgrp {
 350                 fsl,pins = <
 351                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 352                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 353                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 354                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 355                 >;
 356         };
 357
 358         pinctrl_ecspi1: ecspi1grp {
 359                 fsl,pins = <
 360                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 361                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 362                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 363                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 364                 >;
 365         };
 366
 367         pinctrl_enet: enetgrp {
 368                 fsl,pins = <
 369                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
 370                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 371                         /* AR8035 reset */
 372                         MX6QDL_PAD_EIM_A20__GPIO2_IO18          0x130b0
 373                         /* AR8035 interrupt */
 374                         MX6QDL_PAD_EIM_CS0__GPIO2_IO23          0x1b0b1
 375                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 376                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 377                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 378                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 379                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 380                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 381                         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 382                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1
 383                         /* AR8035 pin strapping: IO voltage: pull up */
 384                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 385                         /* AR8035 pin strapping: PHYADDR#0: pull down */
 386                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
 387                         /* AR8035 pin strapping: PHYADDR#1: pull down */
 388                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 389                         /* AR8035 pin strapping: MODE#1: pull up */
 390                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 391                         /* AR8035 pin strapping: MODE#3: pull up */
 392                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 393                         /* AR8035 pin strapping: MODE#0: pull down */
 394                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 395                 >;
 396         };
 397
 398         pinctrl_flexcan2: flexcan2grp {
 399                 fsl,pins = <
 400                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 401                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 402                 >;
 403         };
 404
 405         pinctrl_gpio_keys: gpio_keysgrp {
 406                 fsl,pins = <
 407                         MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
 408                 >;
 409         };
 410
 411         pinctrl_hdmi_cec: hdmicecgrp {
 412                 fsl,pins = <
 413                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
 414                 >;
 415         };
 416
 417         pinctrl_i2c1: i2c1grp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 420                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 421                 >;
 422         };
 423
 424         pinctrl_i2c2: i2c2grp {
 425                 fsl,pins = <
 426                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 427                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 428                 >;
 429         };
 430
 431         pinctrl_i2c3: i2c3grp {
 432                 fsl,pins = <
 433                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 434                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 435                 >;
 436         };
 437
 438         pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
 439                 fsl,pins = <
 440                         MX6QDL_PAD_GPIO_0__CCM_CLKO1                    0x000b0 /* sys_mclk */
 441                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x130b0 /*headphone det*/
 442                         MX6QDL_PAD_GPIO_8__GPIO1_IO08                   0x130b0 /*microphone det*/
 443                 >;
 444         };
 445
 446         pinctrl_pwm1: pwm1grp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_GPIO_9__PWM1_OUT         0x1b0b1
 449                 >;
 450         };
 451
 452         pinctrl_uart1: uart1grp {
 453                 fsl,pins = <
 454                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA    0x1b0b1
 455                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA    0x1b0b1
 456                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 457                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 458                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 459                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 460                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 461                 >;
 462         };
 463
 464         pinctrl_uart2: uart2grp {
 465                 fsl,pins = <
 466                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 467                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 468                         MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
 469                         MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
 470                 >;
 471         };
 472
 473         pinctrl_uart3: uart3grp {
 474                 fsl,pins = <
 475                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA       0x1b0b1
 476                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA       0x1b0b1
 477                         MX6QDL_PAD_EIM_D30__UART3_CTS_B         0x1b0b1
 478                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 479                 >;
 480         };
 481
 482         pinctrl_uart4: uart4grp {
 483                 fsl,pins = <
 484                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 485                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 486                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 487                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 488                 >;
 489         };
 490
 491         pinctrl_uart5: uart5grp {
 492                 fsl,pins = <
 493                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
 494                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
 495                         MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B      0x1b0b1
 496                         MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B      0x1b0b1
 497                         MX6QDL_PAD_EIM_A21__GPIO2_IO17           0x15059 /*BT_EN*/
 498                 >;
 499         };
 500
 501         pinctrl_usbotg: usbotggrp {
 502                 fsl,pins = <
 503                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 504                 >;
 505         };
 506
 507         pinctrl_usdhc1: usdhc1grp {
 508                 fsl,pins = <
 509                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17059
 510                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x10059
 511                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x17059
 512                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x17059
 513                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x17059
 514                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x17059
 515                         MX6QDL_PAD_NANDF_D0__SD1_DATA4          0x17059
 516                         MX6QDL_PAD_NANDF_D1__SD1_DATA5          0x17059
 517                         MX6QDL_PAD_NANDF_D2__SD1_DATA6          0x17059
 518                         MX6QDL_PAD_NANDF_D3__SD1_DATA7          0x17059
 519                 >;
 520         };
 521
 522         pinctrl_usdhc2: usdhc2grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 525                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 526                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 527                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 528                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 529                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 530                         MX6QDL_PAD_EIM_RW__GPIO2_IO26                   0x15059 /*WL_EN_LDO*/
 531                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24          0x15059 /*WL_EN*/
 532                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x15059 /*WL_IRQ*/
 533                 >;
 534         };
 535
 536         pinctrl_usdhc3: usdhc3grp {
 537                 fsl,pins = <
 538                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17071
 539                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10071
 540                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17071
 541                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17071
 542                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17071
 543                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17071
 544                 >;
 545         };
 546
 547         pinctrl_wdog: wdoggrp {
 548                 fsl,pins = <
 549                         MX6QDL_PAD_GPIO_1__WDOG2_B      0x1b0b00
 550                 >;
 551         };
 552 };
 553
 554 &ldb {
 555         status = "okay";
 556
 557         lvds-channel@1 {
 558                 fsl,data-mapping = "spwg";
 559                 fsl,data-width = <18>;
 560                 status = "okay";
 561
 562                 port@4 {
 563                         reg = <4>;
 564
 565                         lvds0_out: endpoint {
 566                                 remote-endpoint = <&panel_in>;
 567                         };
 568                 };
 569         };
 570 };
 571
 572 &pwm1 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pinctrl_pwm1>;
 575         status = "okay";
 576 };
 577
 578 &snvs_poweroff {
 579         status = "okay";
 580 };
 581
 582 &ssi1 {
 583         status = "okay";
 584 };
 585
 586 &uart1 {
 587         pinctrl-names = "default";
 588         pinctrl-0 = <&pinctrl_uart1>;
 589         uart-has-rtscts;
 590         fsl,dte-mode;
 591         status = "okay";
 592 };
 593
 594 &uart2 {
 595         pinctrl-names = "default";
 596         pinctrl-0 = <&pinctrl_uart2>;
 597         uart-has-rtscts;
 598         status = "okay";
 599 };
 600
 601 &uart3 {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&pinctrl_uart3>;
 604         uart-has-rtscts;
 605         status = "okay";
 606 };
 607
 608 &uart4 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_uart4>;
 611         uart-has-rtscts;
 612         status = "okay";
 613 };
 614
 615 &uart5 {
 616         pinctrl-names = "default";
 617         pinctrl-0 = <&pinctrl_uart5>;
 618         uart-has-rtscts;
 619         status = "okay";
 620 };
 621
 622 &usbotg {
 623         vbus-supply = <&reg_usb_otg_vbus>;
 624         pinctrl-names = "default";
 625         pinctrl-0 = <&pinctrl_usbotg>;
 626         disable-over-current;
 627         srp-disable;
 628         hnp-disable;
 629         adp-disable;
 630         status = "okay";
 631 };
 632
 633 &usbh1 {
 634         status = "okay";
 635 };
 636
 637 &usbphy1 {
 638         fsl,tx-d-cal = <0x5>;
 639 };
 640
 641 &usbphy2 {
 642         fsl,tx-d-cal = <0x5>;
 643 };
 644
 645 &usdhc1 {
 646         pinctrl-names = "default";
 647         pinctrl-0 = <&pinctrl_usdhc1>;
 648         bus-width = <8>;
 649         keep-power-in-suspend;
 650         vmmc-supply = <&reg_3p3v>;
 651         status = "okay";
 652 };
 653
 654 &usdhc2 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_usdhc2>;
 657         bus-width = <4>;
 658         vmmc-supply = <&wlan_en_reg>;
 659         no-1-8-v;
 660         keep-power-in-suspend;
 661         non-removable;
 662         cap-power-off-card;
 663         status = "okay";
 664
 665         #address-cells = <1>;
 666         #size-cells = <0>;
 667         wlcore: wlcore@2 {
 668                 compatible = "ti,wl1835";
 669                 reg = <2>;
 670                 interrupt-parent = <&gpio5>;
 671                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 672                 ref-clock-frequency = <38400000>;
 673                 tcxo-clock-frequency = <26000000>;
 674         };
 675 };
 676
 677 &usdhc3 {
 678         pinctrl-names = "default";
 679         pinctrl-0 = <&pinctrl_usdhc3>;
 680         bus-width = <4>;
 681         cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 682         no-1-8-v;
 683         keep-power-in-suspend;
 684         wakeup-source;
 685         status = "okay";
 686 };
 687
 688 &sata {
 689         status = "okay";
 690 };
 691
 692 &wdog1 {
 693         status = "okay";
 694 };