arch/arm/boot/dts/imx6q-mccmon6.dts

   1 /*
   2  * Copyright 2016-2017
   3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "imx6q.dtsi"
  14
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17
  18 / {
  19         model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
  20         compatible = "lwn,mccmon6", "fsl,imx6q";
  21
  22         memory {
  23                 reg = <0x10000000 0x80000000>;
  24         };
  25
  26         backlight_lvds: backlight {
  27                 compatible = "pwm-backlight";
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&pinctrl_backlight>;
  30                 pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
  31                 brightness-levels = <  0   1   2   3   4   5   6   7   8   9
  32                                       10  11  12  13  14  15  16  17  18  19
  33                                       20  21  22  23  24  25  26  27  28  29
  34                                       30  31  32  33  34  35  36  37  38  39
  35                                       40  41  42  43  44  45  46  47  48  49
  36                                       50  51  52  53  54  55  56  57  58  59
  37                                       60  61  62  63  64  65  66  67  68  69
  38                                       70  71  72  73  74  75  76  77  78  79
  39                                       80  81  82  83  84  85  86  87  88  89
  40                                       90  91  92  93  94  95  96  97  98  99
  41                                      100 101 102 103 104 105 106 107 108 109
  42                                      110 111 112 113 114 115 116 117 118 119
  43                                      120 121 122 123 124 125 126 127 128 129
  44                                      130 131 132 133 134 135 136 137 138 139
  45                                      140 141 142 143 144 145 146 147 148 149
  46                                      150 151 152 153 154 155 156 157 158 159
  47                                      160 161 162 163 164 165 166 167 168 169
  48                                      170 171 172 173 174 175 176 177 178 179
  49                                      180 181 182 183 184 185 186 187 188 189
  50                                      190 191 192 193 194 195 196 197 198 199
  51                                      200 201 202 203 204 205 206 207 208 209
  52                                      210 211 212 213 214 215 216 217 218 219
  53                                      220 221 222 223 224 225 226 227 228 229
  54                                      230 231 232 233 234 235 236 237 238 239
  55                                      240 241 242 243 244 245 246 247 248 249
  56                                      250 251 252 253 254 255>;
  57                 default-brightness-level = <50>;
  58                 enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  59         };
  60
  61         reg_lvds: regulator-lvds {
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "lvds_ppen";
  64                 regulator-min-microvolt = <3300000>;
  65                 regulator-max-microvolt = <3300000>;
  66                 regulator-boot-on;
  67                 pinctrl-names = "default";
  68                 pinctrl-0 = <&pinctrl_reg_lvds>;
  69                 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
  70                 enable-active-high;
  71         };
  72
  73         panel-lvds0 {
  74                 compatible = "innolux,g121x1-l03";
  75                 backlight = <&backlight_lvds>;
  76                 power-supply = <&reg_lvds>;
  77
  78                 port {
  79                         panel_in_lvds0: endpoint {
  80                                 remote-endpoint = <&lvds0_out>;
  81                         };
  82                 };
  83         };
  84 };
  85
  86 &ecspi3 {
  87         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
  90         status = "okay";
  91
  92         s25sl032p: flash@0 {
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 compatible = "jedec,spi-nor";
  96                 spi-max-frequency = <40000000>;
  97                 reg = <0>;
  98         };
  99 };
 100
 101 &fec {
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_enet>;
 104         phy-mode = "rgmii";
 105         phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 106         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 107                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 108         status = "okay";
 109 };
 110
 111 &i2c1 {
 112         clock-frequency = <100000>;
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_i2c1>;
 115         status = "okay";
 116 };
 117
 118 &i2c2 {
 119         clock-frequency = <100000>;
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_i2c2>;
 122         status = "okay";
 123
 124         pfuze100: pmic@08 {
 125                 compatible = "fsl,pfuze100";
 126                 reg = <0x08>;
 127
 128                 regulators {
 129                         sw1a_reg: sw1ab {
 130                                 regulator-min-microvolt = <300000>;
 131                                 regulator-max-microvolt = <1875000>;
 132                                 regulator-boot-on;
 133                                 regulator-always-on;
 134                                 regulator-ramp-delay = <6250>;
 135                         };
 136
 137                         sw1c_reg: sw1c {
 138                                 regulator-min-microvolt = <300000>;
 139                                 regulator-max-microvolt = <1875000>;
 140                                 regulator-boot-on;
 141                                 regulator-always-on;
 142                                 regulator-ramp-delay = <6250>;
 143                         };
 144
 145                         sw2_reg: sw2 {
 146                                 regulator-min-microvolt = <800000>;
 147                                 regulator-max-microvolt = <3950000>;
 148                                 regulator-boot-on;
 149                                 regulator-always-on;
 150                         };
 151
 152                         sw3a_reg: sw3a {
 153                                 regulator-min-microvolt = <400000>;
 154                                 regulator-max-microvolt = <1975000>;
 155                                 regulator-boot-on;
 156                                 regulator-always-on;
 157                         };
 158
 159                         sw3b_reg: sw3b {
 160                                 regulator-min-microvolt = <400000>;
 161                                 regulator-max-microvolt = <1975000>;
 162                                 regulator-boot-on;
 163                                 regulator-always-on;
 164                         };
 165
 166                         sw4_reg: sw4 {
 167                                 regulator-min-microvolt = <800000>;
 168                                 regulator-max-microvolt = <3300000>;
 169                         };
 170
 171                         swbst_reg: swbst {
 172                                 regulator-min-microvolt = <5000000>;
 173                                 regulator-max-microvolt = <5150000>;
 174                         };
 175
 176                         snvs_reg: vsnvs {
 177                                 regulator-min-microvolt = <1000000>;
 178                                 regulator-max-microvolt = <3000000>;
 179                                 regulator-boot-on;
 180                                 regulator-always-on;
 181                         };
 182
 183                         vref_reg: vrefddr {
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                         };
 187
 188                         vgen1_reg: vgen1 {
 189                                 regulator-min-microvolt = <800000>;
 190                                 regulator-max-microvolt = <1550000>;
 191                         };
 192
 193                         vgen2_reg: vgen2 {
 194                                 regulator-min-microvolt = <800000>;
 195                                 regulator-max-microvolt = <1550000>;
 196                         };
 197
 198                         vgen3_reg: vgen3 {
 199                                 regulator-min-microvolt = <1800000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                         };
 202
 203                         vgen4_reg: vgen4 {
 204                                 regulator-min-microvolt = <1800000>;
 205                                 regulator-max-microvolt = <3300000>;
 206                                 regulator-always-on;
 207                         };
 208
 209                         vgen5_reg: vgen5 {
 210                                 regulator-min-microvolt = <1800000>;
 211                                 regulator-max-microvolt = <3300000>;
 212                                 regulator-always-on;
 213                         };
 214
 215                         vgen6_reg: vgen6 {
 216                                 regulator-min-microvolt = <1800000>;
 217                                 regulator-max-microvolt = <3300000>;
 218                                 regulator-always-on;
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &ldb {
 225         status = "okay";
 226
 227         lvds0: lvds-channel@0 {
 228                 fsl,data-mapping = "spwg";
 229                 fsl,data-width = <24>;
 230                 status = "okay";
 231
 232                 port@4 {
 233                         reg = <4>;
 234
 235                         lvds0_out: endpoint {
 236                                 remote-endpoint = <&panel_in_lvds0>;
 237                         };
 238                 };
 239         };
 240 };
 241
 242 &pwm2 {
 243         #pwm-cells = <3>;
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_pwm2>;
 246         status = "okay";
 247 };
 248
 249 &uart1 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_uart1>;
 252         status = "okay";
 253 };
 254
 255 &uart4 {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_uart4>;
 258         uart-has-rtscts;
 259         status = "okay";
 260 };
 261
 262 &usdhc2 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_usdhc2>;
 265         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 266         bus-width = <4>;
 267         status = "okay";
 268 };
 269
 270 &usdhc3 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_usdhc3>;
 273         bus-width = <8>;
 274         non-removable;
 275         status = "okay";
 276 };
 277
 278 &weim {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 281         ranges = <0 0 0x08000000 0x08000000>;
 282         status = "okay";
 283
 284         nor@0,0 {
 285                 compatible = "cfi-flash";
 286                 reg = <0 0 0x02000000>;
 287                 #address-cells = <1>;
 288                 #size-cells = <1>;
 289                 bank-width = <2>;
 290                 use-advanced-sector-protection;
 291                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 292                                 0x0000c000 0x1404a38e 0x00000000>;
 293         };
 294 };
 295
 296 &iomuxc {
 297         pinctrl-names = "default";
 298
 299         pinctrl_backlight: dispgrp {
 300                 fsl,pins = <
 301                         /* BLEN_OUT */
 302                         MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x1b0b0
 303                 >;
 304         };
 305
 306         pinctrl_ecspi3: ecspi3grp {
 307                 fsl,pins = <
 308                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 309                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 310                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 311                 >;
 312         };
 313
 314         pinctrl_ecspi3_cs: ecspi3csgrp {
 315                 fsl,pins = <
 316                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
 317                 >;
 318         };
 319
 320         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
 321                 fsl,pins = <
 322                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
 323                 >;
 324         };
 325
 326         pinctrl_enet: enetgrp {
 327                 fsl,pins = <
 328                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 329                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 330                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 331                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 332                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 333                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 334                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 335                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 336                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 337                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 338                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 339                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 340                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 341                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 342                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 343                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
 344                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 345                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
 346                 >;
 347         };
 348
 349         pinctrl_i2c1: i2c1grp {
 350                 fsl,pins = <
 351                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
 352                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
 353                 >;
 354         };
 355
 356         pinctrl_i2c2: i2c2grp {
 357                 fsl,pins = <
 358                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 359                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 360                 >;
 361         };
 362
 363         pinctrl_pwm2: pwm2grp {
 364                 fsl,pins = <
 365                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 366                 >;
 367         };
 368
 369         pinctrl_reg_lvds: reqlvdsgrp {
 370                 fsl,pins = <
 371                         /* LVDS_PPEN_OUT */
 372                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x1b0b0
 373                 >;
 374         };
 375
 376         pinctrl_uart1: uart1grp {
 377                 fsl,pins = <
 378                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 379                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 380                 >;
 381         };
 382
 383         pinctrl_uart4: uart4grp {
 384                 fsl,pins = <
 385                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 386                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 387                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 388                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 389                 >;
 390         };
 391
 392         pinctrl_usdhc2: usdhc2grp {
 393                 fsl,pins = <
 394                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 395                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 396                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 397                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 398                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 399                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 400                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b1
 401                 >;
 402         };
 403
 404         pinctrl_usdhc3: usdhc3grp {
 405                 fsl,pins = <
 406                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 407                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 408                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 409                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 410                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 411                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 412                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 413                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 414                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 415                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 416                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x17059
 417                 >;
 418         };
 419
 420         pinctrl_weim_cs0: weimcs0grp {
 421                 fsl,pins = <
 422                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 423                 >;
 424         };
 425
 426         pinctrl_weim_nor: weimnorgrp {
 427                 fsl,pins = <
 428                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 429                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 430                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 431                         MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 432                         MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 433                         MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 434                         MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 435                         MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 436                         MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 437                         MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 438                         MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 439                         MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 440                         MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 441                         MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 442                         MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 443                         MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 444                         MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 445                         MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 446                         MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 447                         MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 448                         MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 449                         MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 450                         MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 451                         MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 452                         MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 453                         MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 454                         MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 455                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 456                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 457                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 458                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 459                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 460                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 461                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 462                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 463                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 464                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 465                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 466                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 467                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 468                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 469                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 470                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 471                 >;
 472         };
 473 };