Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6q-mccmon6.dts
1 /*
2  * Copyright 2016-2017
3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  */
10
11 /dts-v1/;
12
13 #include "imx6q.dtsi"
14
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pwm/pwm.h>
17
18 / {
19         model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
20         compatible = "lwn,mccmon6", "fsl,imx6q";
21
22         memory@10000000 {
23                 device_type = "memory";
24                 reg = <0x10000000 0x80000000>;
25         };
26
27         backlight_lvds: backlight {
28                 compatible = "pwm-backlight";
29                 pinctrl-names = "default";
30                 pinctrl-0 = <&pinctrl_backlight>;
31                 pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
32                 brightness-levels = <  0   1   2   3   4   5   6   7   8   9
33                                       10  11  12  13  14  15  16  17  18  19
34                                       20  21  22  23  24  25  26  27  28  29
35                                       30  31  32  33  34  35  36  37  38  39
36                                       40  41  42  43  44  45  46  47  48  49
37                                       50  51  52  53  54  55  56  57  58  59
38                                       60  61  62  63  64  65  66  67  68  69
39                                       70  71  72  73  74  75  76  77  78  79
40                                       80  81  82  83  84  85  86  87  88  89
41                                       90  91  92  93  94  95  96  97  98  99
42                                      100 101 102 103 104 105 106 107 108 109
43                                      110 111 112 113 114 115 116 117 118 119
44                                      120 121 122 123 124 125 126 127 128 129
45                                      130 131 132 133 134 135 136 137 138 139
46                                      140 141 142 143 144 145 146 147 148 149
47                                      150 151 152 153 154 155 156 157 158 159
48                                      160 161 162 163 164 165 166 167 168 169
49                                      170 171 172 173 174 175 176 177 178 179
50                                      180 181 182 183 184 185 186 187 188 189
51                                      190 191 192 193 194 195 196 197 198 199
52                                      200 201 202 203 204 205 206 207 208 209
53                                      210 211 212 213 214 215 216 217 218 219
54                                      220 221 222 223 224 225 226 227 228 229
55                                      230 231 232 233 234 235 236 237 238 239
56                                      240 241 242 243 244 245 246 247 248 249
57                                      250 251 252 253 254 255>;
58                 default-brightness-level = <50>;
59                 enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
60         };
61
62         reg_lvds: regulator-lvds {
63                 compatible = "regulator-fixed";
64                 regulator-name = "lvds_ppen";
65                 regulator-min-microvolt = <3300000>;
66                 regulator-max-microvolt = <3300000>;
67                 regulator-boot-on;
68                 pinctrl-names = "default";
69                 pinctrl-0 = <&pinctrl_reg_lvds>;
70                 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
71                 enable-active-high;
72         };
73
74         panel-lvds0 {
75                 compatible = "innolux,g121x1-l03";
76                 backlight = <&backlight_lvds>;
77                 power-supply = <&reg_lvds>;
78
79                 port {
80                         panel_in_lvds0: endpoint {
81                                 remote-endpoint = <&lvds0_out>;
82                         };
83                 };
84         };
85 };
86
87 &ecspi3 {
88         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
89         pinctrl-names = "default";
90         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
91         status = "okay";
92
93         s25sl032p: flash@0 {
94                 #address-cells = <1>;
95                 #size-cells = <1>;
96                 compatible = "jedec,spi-nor";
97                 spi-max-frequency = <40000000>;
98                 reg = <0>;
99         };
100 };
101
102 &fec {
103         pinctrl-names = "default";
104         pinctrl-0 = <&pinctrl_enet>;
105         phy-mode = "rgmii";
106         phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
107         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
108                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
109         status = "okay";
110 };
111
112 &i2c1 {
113         clock-frequency = <100000>;
114         pinctrl-names = "default";
115         pinctrl-0 = <&pinctrl_i2c1>;
116         status = "okay";
117 };
118
119 &i2c2 {
120         clock-frequency = <100000>;
121         pinctrl-names = "default";
122         pinctrl-0 = <&pinctrl_i2c2>;
123         status = "okay";
124
125         pfuze100: pmic@8 {
126                 compatible = "fsl,pfuze100";
127                 reg = <0x08>;
128
129                 regulators {
130                         sw1a_reg: sw1ab {
131                                 regulator-min-microvolt = <300000>;
132                                 regulator-max-microvolt = <1875000>;
133                                 regulator-boot-on;
134                                 regulator-always-on;
135                                 regulator-ramp-delay = <6250>;
136                         };
137
138                         sw1c_reg: sw1c {
139                                 regulator-min-microvolt = <300000>;
140                                 regulator-max-microvolt = <1875000>;
141                                 regulator-boot-on;
142                                 regulator-always-on;
143                                 regulator-ramp-delay = <6250>;
144                         };
145
146                         sw2_reg: sw2 {
147                                 regulator-min-microvolt = <800000>;
148                                 regulator-max-microvolt = <3950000>;
149                                 regulator-boot-on;
150                                 regulator-always-on;
151                         };
152
153                         sw3a_reg: sw3a {
154                                 regulator-min-microvolt = <400000>;
155                                 regulator-max-microvolt = <1975000>;
156                                 regulator-boot-on;
157                                 regulator-always-on;
158                         };
159
160                         sw3b_reg: sw3b {
161                                 regulator-min-microvolt = <400000>;
162                                 regulator-max-microvolt = <1975000>;
163                                 regulator-boot-on;
164                                 regulator-always-on;
165                         };
166
167                         sw4_reg: sw4 {
168                                 regulator-min-microvolt = <800000>;
169                                 regulator-max-microvolt = <3300000>;
170                         };
171
172                         swbst_reg: swbst {
173                                 regulator-min-microvolt = <5000000>;
174                                 regulator-max-microvolt = <5150000>;
175                         };
176
177                         snvs_reg: vsnvs {
178                                 regulator-min-microvolt = <1000000>;
179                                 regulator-max-microvolt = <3000000>;
180                                 regulator-boot-on;
181                                 regulator-always-on;
182                         };
183
184                         vref_reg: vrefddr {
185                                 regulator-boot-on;
186                                 regulator-always-on;
187                         };
188
189                         vgen1_reg: vgen1 {
190                                 regulator-min-microvolt = <800000>;
191                                 regulator-max-microvolt = <1550000>;
192                         };
193
194                         vgen2_reg: vgen2 {
195                                 regulator-min-microvolt = <800000>;
196                                 regulator-max-microvolt = <1550000>;
197                         };
198
199                         vgen3_reg: vgen3 {
200                                 regulator-min-microvolt = <1800000>;
201                                 regulator-max-microvolt = <3300000>;
202                         };
203
204                         vgen4_reg: vgen4 {
205                                 regulator-min-microvolt = <1800000>;
206                                 regulator-max-microvolt = <3300000>;
207                                 regulator-always-on;
208                         };
209
210                         vgen5_reg: vgen5 {
211                                 regulator-min-microvolt = <1800000>;
212                                 regulator-max-microvolt = <3300000>;
213                                 regulator-always-on;
214                         };
215
216                         vgen6_reg: vgen6 {
217                                 regulator-min-microvolt = <1800000>;
218                                 regulator-max-microvolt = <3300000>;
219                                 regulator-always-on;
220                         };
221                 };
222         };
223 };
224
225 &ldb {
226         status = "okay";
227
228         lvds0: lvds-channel@0 {
229                 fsl,data-mapping = "spwg";
230                 fsl,data-width = <24>;
231                 status = "okay";
232
233                 port@4 {
234                         reg = <4>;
235
236                         lvds0_out: endpoint {
237                                 remote-endpoint = <&panel_in_lvds0>;
238                         };
239                 };
240         };
241 };
242
243 &pwm2 {
244         #pwm-cells = <3>;
245         pinctrl-names = "default";
246         pinctrl-0 = <&pinctrl_pwm2>;
247         status = "okay";
248 };
249
250 &uart1 {
251         pinctrl-names = "default";
252         pinctrl-0 = <&pinctrl_uart1>;
253         status = "okay";
254 };
255
256 &uart4 {
257         pinctrl-names = "default";
258         pinctrl-0 = <&pinctrl_uart4>;
259         uart-has-rtscts;
260         status = "okay";
261 };
262
263 &usdhc2 {
264         pinctrl-names = "default";
265         pinctrl-0 = <&pinctrl_usdhc2>;
266         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
267         bus-width = <4>;
268         status = "okay";
269 };
270
271 &usdhc3 {
272         pinctrl-names = "default";
273         pinctrl-0 = <&pinctrl_usdhc3>;
274         bus-width = <8>;
275         non-removable;
276         status = "okay";
277 };
278
279 &weim {
280         pinctrl-names = "default";
281         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
282         ranges = <0 0 0x08000000 0x08000000>;
283         status = "okay";
284
285         nor@0,0 {
286                 compatible = "cfi-flash";
287                 reg = <0 0 0x02000000>;
288                 #address-cells = <1>;
289                 #size-cells = <1>;
290                 bank-width = <2>;
291                 use-advanced-sector-protection;
292                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
293                                 0x0000c000 0x1404a38e 0x00000000>;
294         };
295 };
296
297 &iomuxc {
298         pinctrl-names = "default";
299
300         pinctrl_backlight: dispgrp {
301                 fsl,pins = <
302                         /* BLEN_OUT */
303                         MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x1b0b0
304                 >;
305         };
306
307         pinctrl_ecspi3: ecspi3grp {
308                 fsl,pins = <
309                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
310                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
311                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
312                 >;
313         };
314
315         pinctrl_ecspi3_cs: ecspi3csgrp {
316                 fsl,pins = <
317                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
318                 >;
319         };
320
321         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
322                 fsl,pins = <
323                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
324                 >;
325         };
326
327         pinctrl_enet: enetgrp {
328                 fsl,pins = <
329                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
330                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
331                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
332                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
333                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
334                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
335                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
336                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
337                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
338                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
339                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
340                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
341                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
342                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
343                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
344                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
345                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
346                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
347                 >;
348         };
349
350         pinctrl_i2c1: i2c1grp {
351                 fsl,pins = <
352                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
353                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
354                 >;
355         };
356
357         pinctrl_i2c2: i2c2grp {
358                 fsl,pins = <
359                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
360                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
361                 >;
362         };
363
364         pinctrl_pwm2: pwm2grp {
365                 fsl,pins = <
366                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
367                 >;
368         };
369
370         pinctrl_reg_lvds: reqlvdsgrp {
371                 fsl,pins = <
372                         /* LVDS_PPEN_OUT */
373                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x1b0b0
374                 >;
375         };
376
377         pinctrl_uart1: uart1grp {
378                 fsl,pins = <
379                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
380                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
381                 >;
382         };
383
384         pinctrl_uart4: uart4grp {
385                 fsl,pins = <
386                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
387                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
388                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
389                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
390                 >;
391         };
392
393         pinctrl_usdhc2: usdhc2grp {
394                 fsl,pins = <
395                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
396                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
397                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
398                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
399                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
400                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
401                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b1
402                 >;
403         };
404
405         pinctrl_usdhc3: usdhc3grp {
406                 fsl,pins = <
407                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
408                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
409                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
410                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
411                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
412                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
413                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
414                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
415                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
416                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
417                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x17059
418                 >;
419         };
420
421         pinctrl_weim_cs0: weimcs0grp {
422                 fsl,pins = <
423                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
424                 >;
425         };
426
427         pinctrl_weim_nor: weimnorgrp {
428                 fsl,pins = <
429                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
430                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
431                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
432                         MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
433                         MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
434                         MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
435                         MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
436                         MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
437                         MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
438                         MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
439                         MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
440                         MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
441                         MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
442                         MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
443                         MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
444                         MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
445                         MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
446                         MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
447                         MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
448                         MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
449                         MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
450                         MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
451                         MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
452                         MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
453                         MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
454                         MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
455                         MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
456                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
457                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
458                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
459                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
460                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
461                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
462                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
463                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
464                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
465                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
466                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
467                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
468                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
469                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
470                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
471                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
472                 >;
473         };
474 };