Linux 5.4-rc7
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6q-gw53xx.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2013 Gateworks Corporation
4  */
5
6 /dts-v1/;
7 #include "imx6q.dtsi"
8 #include "imx6qdl-gw53xx.dtsi"
9
10 / {
11         model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
12         compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
13 };
14
15 &i2c3 {
16         adv7180: camera@20 {
17                 compatible = "adi,adv7180";
18                 pinctrl-names = "default";
19                 pinctrl-0 = <&pinctrl_adv7180>;
20                 reg = <0x20>;
21                 powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
22                 interrupt-parent = <&gpio3>;
23                 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
24
25                 port {
26                         adv7180_to_ipu2_csi1_mux: endpoint {
27                                 remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
28                                 bus-width = <8>;
29                         };
30                 };
31         };
32 };
33
34 &ipu2_csi1_from_ipu2_csi1_mux {
35         bus-width = <8>;
36 };
37
38 &ipu2_csi1_mux_from_parallel_sensor {
39         remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
40         bus-width = <8>;
41 };
42
43 &ipu2_csi1 {
44         pinctrl-names = "default";
45         pinctrl-0 = <&pinctrl_ipu2_csi1>;
46 };
47
48 &sata {
49         status = "okay";
50 };
51
52 &iomuxc {
53         pinctrl_adv7180: adv7180grp {
54                 fsl,pins = <
55                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
56                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
57                 >;
58         };
59
60         pinctrl_ipu2_csi1: ipu2_csi1grp {
61                 fsl,pins = <
62                         MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
63                         MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
64                         MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
65                         MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
66                         MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
67                         MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
68                         MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
69                         MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
70                         MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
71                         MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
72                         MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
73                 >;
74         };
75 };