arch/arm/boot/dts/imx6dl-yapp4-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2015-2018 Y Soft Corporation, a.s.
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/pwm/pwm.h>
   8
   9 / {
  10         backlight: backlight {
  11                 compatible = "pwm-backlight";
  12                 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
  13                 brightness-levels = <0 32 64 128 255>;
  14                 default-brightness-level = <32>;
  15                 num-interpolated-steps = <8>;
  16                 power-supply = <&sw2_reg>;
  17                 status = "disabled";
  18         };
  19
  20         lcd_display: display {
  21                 compatible = "fsl,imx-parallel-display";
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 interface-pix-fmt = "rgb24";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_ipu1>;
  27                 status = "disabled";
  28
  29                 port@0 {
  30                         reg = <0>;
  31
  32                         lcd_display_in: endpoint {
  33                                 remote-endpoint = <&ipu1_di0_disp0>;
  34                         };
  35                 };
  36
  37                 port@1 {
  38                         reg = <1>;
  39
  40                         lcd_display_out: endpoint {
  41                                 remote-endpoint = <&lcd_panel_in>;
  42                         };
  43                 };
  44         };
  45
  46         panel: panel {
  47                 compatible = "dataimage,scf0700c48ggu18";
  48                 power-supply = <&sw2_reg>;
  49                 status = "disabled";
  50
  51                 port {
  52                         lcd_panel_in: endpoint {
  53                                 remote-endpoint = <&lcd_display_out>;
  54                         };
  55                 };
  56         };
  57
  58         reg_pcie: regulator-pcie {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_pcie_reg>;
  62                 regulator-name = "MPCIE_3V3";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67                 status = "disabled";
  68         };
  69
  70         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  71                 compatible = "regulator-fixed";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
  74                 regulator-name = "usb_h1_vbus";
  75                 regulator-min-microvolt = <5000000>;
  76                 regulator-max-microvolt = <5000000>;
  77                 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  78                 enable-active-high;
  79                 status = "disabled";
  80         };
  81
  82         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  83                 compatible = "regulator-fixed";
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
  86                 regulator-name = "usb_otg_vbus";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91                 status = "okay";
  92         };
  93 };
  94
  95 &fec {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_enet>;
  98         phy-mode = "rgmii-id";
  99         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 100         phy-reset-duration = <20>;
 101         phy-supply = <&sw2_reg>;
 102         phy-handle = <&ethphy0>;
 103         status = "okay";
 104
 105         mdio {
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108
 109                 phy_port2: phy@1 {
 110                         reg = <1>;
 111                 };
 112
 113                 phy_port3: phy@2 {
 114                         reg = <2>;
 115                 };
 116
 117                 switch@0 {
 118                         compatible = "qca,qca8334";
 119                         reg = <0>;
 120
 121                         switch_ports: ports {
 122                                 #address-cells = <1>;
 123                                 #size-cells = <0>;
 124
 125                                 ethphy0: port@0 {
 126                                         reg = <0>;
 127                                         label = "cpu";
 128                                         phy-mode = "rgmii";
 129                                         ethernet = <&fec>;
 130
 131                                         fixed-link {
 132                                                 speed = <1000>;
 133                                                 full-duplex;
 134                                         };
 135                                 };
 136
 137                                 port@2 {
 138                                         reg = <2>;
 139                                         label = "eth2";
 140                                         phy-handle = <&phy_port2>;
 141                                 };
 142
 143                                 port@3 {
 144                                         reg = <3>;
 145                                         label = "eth1";
 146                                         phy-handle = <&phy_port3>;
 147                                 };
 148                         };
 149                 };
 150         };
 151 };
 152
 153 &hdmi {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_hdmi_cec>;
 156         ddc-i2c-bus = <&i2c2>;
 157         status = "disabled";
 158 };
 159
 160 &i2c2 {
 161         clock-frequency = <100000>;
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_i2c2>;
 164         status = "okay";
 165
 166         pmic@8 {
 167                 compatible = "fsl,pfuze200";
 168                 pinctrl-names = "default";
 169                 pinctrl-0 = <&pinctrl_pmic>;
 170                 reg = <0x8>;
 171
 172                 regulators {
 173                         sw1a_reg: sw1ab {
 174                                 regulator-min-microvolt = <300000>;
 175                                 regulator-max-microvolt = <1875000>;
 176                                 regulator-boot-on;
 177                                 regulator-always-on;
 178                                 regulator-ramp-delay = <6250>;
 179                         };
 180
 181                         sw2_reg: sw2 {
 182                                 regulator-min-microvolt = <800000>;
 183                                 regulator-max-microvolt = <3300000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                         };
 187
 188                         sw3a_reg: sw3a {
 189                                 regulator-min-microvolt = <400000>;
 190                                 regulator-max-microvolt = <1975000>;
 191                                 regulator-boot-on;
 192                                 regulator-always-on;
 193                         };
 194
 195                         sw3b_reg: sw3b {
 196                                 regulator-min-microvolt = <400000>;
 197                                 regulator-max-microvolt = <1975000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         swbst_reg: swbst {
 203                                 regulator-min-microvolt = <5000000>;
 204                                 regulator-max-microvolt = <5150000>;
 205                         };
 206
 207                         vgen1_reg: vgen1 {
 208                                 regulator-min-microvolt = <800000>;
 209                                 regulator-max-microvolt = <1550000>;
 210                         };
 211
 212                         vgen2_reg: vgen2 {
 213                                 regulator-min-microvolt = <800000>;
 214                                 regulator-max-microvolt = <1550000>;
 215                         };
 216
 217                         vgen3_reg: vgen3 {
 218                                 regulator-min-microvolt = <1800000>;
 219                                 regulator-max-microvolt = <3300000>;
 220                                 regulator-always-on;
 221                         };
 222
 223                         vgen4_reg: vgen4 {
 224                                 regulator-min-microvolt = <1800000>;
 225                                 regulator-max-microvolt = <3300000>;
 226                                 regulator-always-on;
 227                         };
 228
 229                         vgen5_reg: vgen5 {
 230                                 regulator-min-microvolt = <1800000>;
 231                                 regulator-max-microvolt = <3300000>;
 232                                 regulator-always-on;
 233                         };
 234
 235                         vgen6_reg: vgen6 {
 236                                 regulator-min-microvolt = <1800000>;
 237                                 regulator-max-microvolt = <3300000>;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vref_reg: vrefddr {
 242                                 regulator-boot-on;
 243                                 regulator-always-on;
 244                         };
 245
 246                         vsnvs_reg: vsnvs {
 247                                 regulator-min-microvolt = <1000000>;
 248                                 regulator-max-microvolt = <3000000>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                         };
 252                 };
 253         };
 254
 255         leds: led-controller@30 {
 256                 compatible = "ti,lp5562";
 257                 reg = <0x30>;
 258                 clock-mode = /bits/ 8 <1>;
 259                 status = "disabled";
 260
 261                 chan0 {
 262                         chan-name = "R";
 263                         led-cur = /bits/ 8 <0x20>;
 264                         max-cur = /bits/ 8 <0x60>;
 265                 };
 266
 267                 chan1 {
 268                         chan-name = "G";
 269                         led-cur = /bits/ 8 <0x20>;
 270                         max-cur = /bits/ 8 <0x60>;
 271                 };
 272
 273                 chan2 {
 274                         chan-name = "B";
 275                         led-cur = /bits/ 8 <0x20>;
 276                         max-cur = /bits/ 8 <0x60>;
 277                 };
 278
 279                 chan3 {
 280                         chan-name = "W";
 281                         led-cur = /bits/ 8 <0x0>;
 282                         max-cur = /bits/ 8 <0x0>;
 283                 };
 284         };
 285
 286         eeprom@57 {
 287                 compatible = "atmel,24c128";
 288                 reg = <0x57>;
 289                 pagesize = <64>;
 290                 status = "okay";
 291         };
 292
 293         touchscreen: touchscreen@5c {
 294                 compatible = "pixcir,pixcir_tangoc";
 295                 reg = <0x5c>;
 296                 pinctrl-0 = <&pinctrl_touch>;
 297                 interrupt-parent = <&gpio4>;
 298                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 299                 attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
 300                 reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 301                 touchscreen-size-x = <800>;
 302                 touchscreen-size-y = <480>;
 303                 status = "disabled";
 304         };
 305 };
 306
 307 &i2c3 {
 308         clock-frequency = <100000>;
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_i2c3>;
 311         status = "disabled";
 312
 313         oled: oled@3d {
 314                 compatible = "solomon,ssd1305fb-i2c";
 315                 reg = <0x3d>;
 316                 solomon,height = <64>;
 317                 solomon,width = <128>;
 318                 solomon,page-offset = <0>;
 319                 solomon,prechargep2 = <15>;
 320                 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
 321                 vbat-supply = <&sw2_reg>;
 322                 status = "disabled";
 323         };
 324
 325         gpio_oled: gpio@41 {
 326                 compatible = "nxp,pca9536";
 327                 gpio-controller;
 328                 #gpio-cells = <2>;
 329                 reg = <0x41>;
 330                 vcc-supply = <&sw2_reg>;
 331                 status = "disabled";
 332         };
 333 };
 334
 335 &iomuxc {
 336         pinctrl_enet: enetgrp {
 337                 fsl,pins = <
 338                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b020
 339                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b020
 340                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b020
 341                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b020
 342                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b020
 343                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b020
 344                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b020
 345                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b020
 346                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b020
 347                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b020
 348                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b020
 349                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b020
 350                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b020
 351                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b020
 352                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b010
 353                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b010
 354                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b098
 355                 >;
 356         };
 357
 358         pinctrl_hdmi_cec: hdmicecgrp {
 359                 fsl,pins = <
 360                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1b898
 361                 >;
 362         };
 363
 364         pinctrl_i2c2: i2c2grp {
 365                 fsl,pins = <
 366                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b899
 367                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b899
 368                 >;
 369         };
 370
 371         pinctrl_i2c3: i2c3grp {
 372                 fsl,pins = <
 373                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b899
 374                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b899
 375                 >;
 376         };
 377
 378         pinctrl_ipu1: ipu1grp {
 379                 fsl,pins = <
 380                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
 381                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
 382                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
 383                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
 384                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
 385                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
 386                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
 387                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
 388                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
 389                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
 390                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
 391                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
 392                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
 393                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
 394                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
 395                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
 396                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
 397                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
 398                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
 399                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
 400                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
 401                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
 402                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
 403                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
 404                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
 405                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
 406                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
 407                 >;
 408         };
 409
 410         pinctrl_pcie: pciegrp {
 411                 fsl,pins = <
 412                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b098
 413                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b098
 414                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b098
 415                 >;
 416         };
 417
 418         pinctrl_pcie_reg: pciereggrp {
 419                 fsl,pins = <
 420                         MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b098
 421                 >;
 422         };
 423
 424         pinctrl_pmic: pmicgrp {
 425                 fsl,pins = <
 426                         MX6QDL_PAD_GPIO_18__GPIO7_IO13  0x1b098
 427                 >;
 428         };
 429
 430         pinctrl_pwm1: pwm1grp {
 431                 fsl,pins = <
 432                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x8
 433                 >;
 434         };
 435
 436         pinctrl_touch: touchgrp {
 437                 fsl,pins = <
 438                         MX6QDL_PAD_GPIO_19__GPIO4_IO05  0x1b098
 439                         MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b098
 440                 >;
 441         };
 442
 443         pinctrl_uart1: uart1grp {
 444                 fsl,pins = <
 445                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0a8
 446                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0a8
 447                 >;
 448         };
 449
 450         pinctrl_usbh1: usbh1grp {
 451                 fsl,pins = <
 452                         MX6QDL_PAD_EIM_D30__USB_H1_OC   0x1b098
 453                 >;
 454         };
 455
 456         pinctrl_usbh1_vbus: usbh1-vbus {
 457                 fsl,pins = <
 458                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x98
 459                 >;
 460         };
 461
 462         pinctrl_usbotg: usbotggrp {
 463                 fsl,pins = <
 464                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x1b098
 465                         MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b098
 466                 >;
 467         };
 468
 469         pinctrl_usbotg_vbus: usbotg-vbus {
 470                 fsl,pins = <
 471                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x98
 472                 >;
 473         };
 474
 475         pinctrl_usdhc3: usdhc3grp {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_EIM_A16__GPIO2_IO22  0x1b018
 478                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b018
 479                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 480                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 481                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 482                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 483                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 484                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 485                 >;
 486         };
 487
 488         pinctrl_usdhc4: usdhc4grp {
 489                 fsl,pins = <
 490                         MX6QDL_PAD_SD4_CMD__SD4_CMD     0x1f069
 491                         MX6QDL_PAD_SD4_CLK__SD4_CLK     0x10069
 492                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0  0x17069
 493                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1  0x17069
 494                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2  0x17069
 495                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3  0x17069
 496                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4  0x17069
 497                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5  0x17069
 498                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6  0x17069
 499                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7  0x17069
 500                 >;
 501         };
 502
 503         pinctrl_wdog: wdoggrp {
 504                 fsl,pins = <
 505                         MX6QDL_PAD_GPIO_1__WDOG2_B      0x1b0b0
 506                 >;
 507         };
 508 };
 509
 510 &ipu1_di0_disp0 {
 511         remote-endpoint = <&lcd_display_in>;
 512 };
 513
 514 &pcie {
 515         pinctrl-names = "default";
 516         pinctrl-0 = <&pinctrl_pcie>;
 517         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 518         vpcie-supply = <&reg_pcie>;
 519         status = "disabled";
 520 };
 521
 522 &pwm1 {
 523         #pwm-cells = <3>;
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_pwm1>;
 526         status = "disabled";
 527 };
 528
 529 &uart1 {
 530         pinctrl-names = "default";
 531         pinctrl-0 = <&pinctrl_uart1>;
 532         status = "okay";
 533 };
 534
 535 &usbh1 {
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&pinctrl_usbh1>;
 538         vbus-supply = <&reg_usb_h1_vbus>;
 539         status = "disabled";
 540 };
 541
 542 &usbotg {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&pinctrl_usbotg>;
 545         vbus-supply = <&reg_usb_otg_vbus>;
 546         srp-disable;
 547         hnp-disable;
 548         adp-disable;
 549         status = "okay";
 550 };
 551
 552 &usbphy1 {
 553         fsl,tx-d-cal = <106>;
 554         status = "okay";
 555 };
 556
 557 &usbphy2 {
 558         fsl,tx-d-cal = <109>;
 559         status = "disabled";
 560 };
 561
 562 &usdhc3 {
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&pinctrl_usdhc3>;
 565         bus-width = <4>;
 566         cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
 567         wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
 568         no-1-8-v;
 569         keep-power-in-suspend;
 570         wakeup-source;
 571         vmmc-supply = <&sw2_reg>;
 572         status = "disabled";
 573 };
 574
 575 &usdhc4 {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&pinctrl_usdhc4>;
 578         bus-width = <8>;
 579         non-removable;
 580         no-1-8-v;
 581         keep-power-in-suspend;
 582         vmmc-supply = <&sw2_reg>;
 583         status = "okay";
 584 };
 585
 586 &wdog1 {
 587         status = "disabled";
 588 };
 589
 590 &wdog2 {
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&pinctrl_wdog>;
 593         fsl,ext-reset-output;
 594         status = "okay";
 595 };