arch/arm/boot/dts/imx6dl-riotboard.dts

   1 /*
   2  * Copyright 2014 Iain Paton <ipaton0@gmail.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 /dts-v1/;
  11 #include "imx6dl.dtsi"
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         model = "RIoTboard i.MX6S";
  16         compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
  17
  18         memory@10000000 {
  19                 reg = <0x10000000 0x40000000>;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial1:115200n8";
  24         };
  25
  26         leds {
  27                 compatible = "gpio-leds";
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&pinctrl_led>;
  30
  31                 led0: user1 {
  32                         label = "user1";
  33                         gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
  34                         default-state = "on";
  35                         linux,default-trigger = "heartbeat";
  36                 };
  37
  38                 led1: user2 {
  39                         label = "user2";
  40                         gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
  41                         default-state = "off";
  42                 };
  43         };
  44
  45         sound {
  46                 compatible = "fsl,imx-audio-sgtl5000";
  47                 model = "imx6-riotboard-sgtl5000";
  48                 ssi-controller = <&ssi1>;
  49                 audio-codec = <&codec>;
  50                 audio-routing =
  51                         "MIC_IN", "Mic Jack",
  52                         "Mic Jack", "Mic Bias",
  53                         "Headphone Jack", "HP_OUT";
  54                         mux-int-port = <1>;
  55                         mux-ext-port = <3>;
  56         };
  57
  58         reg_2p5v: regulator-2p5v {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "2P5V";
  61                 regulator-min-microvolt = <2500000>;
  62                 regulator-max-microvolt = <2500000>;
  63         };
  64
  65         reg_3p3v: regulator-3p3v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "3P3V";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70         };
  71
  72         reg_usb_otg_vbus: regulator-usbotgvbus {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "usb_otg_vbus";
  75                 regulator-min-microvolt = <5000000>;
  76                 regulator-max-microvolt = <5000000>;
  77                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  78         };
  79 };
  80
  81 &audmux {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_audmux>;
  84         status = "okay";
  85 };
  86
  87 &clks {
  88         fsl,pmic-stby-poweroff;
  89 };
  90
  91 &fec {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_enet>;
  94         phy-mode = "rgmii";
  95         phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  96         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  97                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  98         fsl,err006687-workaround-present;
  99         status = "okay";
 100 };
 101
 102 &gpio1 {
 103         gpio-line-names =
 104                 "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
 105                         "I2C3_SDA", "I2C4_SCL",
 106                 "I2C4_SDA", "", "", "", "", "", "", "",
 107                 "", "PWM3", "", "", "", "", "", "",
 108                 "", "", "", "", "", "", "", "";
 109 };
 110
 111 &gpio3 {
 112         gpio-line-names =
 113                 "", "", "", "", "", "", "", "",
 114                 "", "", "", "", "", "", "", "",
 115                 "", "", "", "", "", "", "USB_OTG_VBUS", "",
 116                 "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
 117 };
 118
 119 &gpio4 {
 120         gpio-line-names =
 121                 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
 122                 "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
 123                 "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
 124                         "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
 125                 "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
 126                         "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
 127 };
 128
 129 &gpio5 {
 130         gpio-line-names =
 131                 "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
 132                         "GPIO5_07",
 133                 "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
 134                         "CSPI2_CS0", "CSPI2_CLK", "", "",
 135                 "", "", "", "", "", "", "", "",
 136                 "", "", "", "", "", "", "", "";
 137 };
 138
 139 &gpio7 {
 140         gpio-line-names =
 141                 "SD3_CD", "SD3_WP", "", "", "", "", "", "",
 142                 "", "", "", "", "", "", "", "",
 143                 "", "", "", "", "", "", "", "",
 144                 "", "", "", "", "", "", "", "";
 145 };
 146
 147 &hdmi {
 148         ddc-i2c-bus = <&i2c2>;
 149         status = "okay";
 150 };
 151
 152 &i2c1 {
 153         clock-frequency = <100000>;
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_i2c1>;
 156         status = "okay";
 157
 158         codec: sgtl5000@a {
 159                 compatible = "fsl,sgtl5000";
 160                 reg = <0x0a>;
 161                 clocks = <&clks IMX6QDL_CLK_CKO>;
 162                 VDDA-supply = <&reg_2p5v>;
 163                 VDDIO-supply = <&reg_3p3v>;
 164         };
 165
 166         pmic: pf0100@8 {
 167                 compatible = "fsl,pfuze100";
 168                 reg = <0x08>;
 169                 interrupt-parent = <&gpio5>;
 170                 interrupts = <16 8>;
 171                 fsl,pmic-stby-poweroff;
 172
 173                 regulators {
 174                         reg_vddcore: sw1ab {                            /* VDDARM_IN */
 175                                 regulator-min-microvolt = <300000>;
 176                                 regulator-max-microvolt = <1875000>;
 177                                 regulator-always-on;
 178                         };
 179
 180                         reg_vddsoc: sw1c {                              /* VDDSOC_IN */
 181                                 regulator-min-microvolt = <300000>;
 182                                 regulator-max-microvolt = <1875000>;
 183                                 regulator-always-on;
 184                         };
 185
 186                         reg_gen_3v3: sw2 {                              /* VDDHIGH_IN */
 187                                 regulator-min-microvolt = <800000>;
 188                                 regulator-max-microvolt = <3300000>;
 189                                 regulator-always-on;
 190                         };
 191
 192                         reg_ddr_1v5a: sw3a {                            /* NVCC_DRAM, NVCC_RGMII */
 193                                 regulator-min-microvolt = <400000>;
 194                                 regulator-max-microvolt = <1975000>;
 195                                 regulator-always-on;
 196                         };
 197
 198                         reg_ddr_1v5b: sw3b {                            /* NVCC_DRAM, NVCC_RGMII */
 199                                 regulator-min-microvolt = <400000>;
 200                                 regulator-max-microvolt = <1975000>;
 201                                 regulator-always-on;
 202                         };
 203
 204                         reg_ddr_vtt: sw4 {                              /* MIPI conn */
 205                                 regulator-min-microvolt = <400000>;
 206                                 regulator-max-microvolt = <1975000>;
 207                                 regulator-always-on;
 208                         };
 209
 210                         reg_5v_600mA: swbst {                           /* not used */
 211                                 regulator-min-microvolt = <5000000>;
 212                                 regulator-max-microvolt = <5150000>;
 213                         };
 214
 215                         reg_snvs_3v: vsnvs {                            /* VDD_SNVS_IN */
 216                                 regulator-min-microvolt = <1500000>;
 217                                 regulator-max-microvolt = <3000000>;
 218                                 regulator-always-on;
 219                         };
 220
 221                         vref_reg: vrefddr {                             /* VREF_DDR */
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225
 226                         reg_vgen1_1v5: vgen1 {                          /* not used */
 227                                 regulator-min-microvolt = <800000>;
 228                                 regulator-max-microvolt = <1550000>;
 229                         };
 230
 231                         reg_vgen2_1v2_eth: vgen2 {                      /* pcie ? */
 232                                 regulator-min-microvolt = <800000>;
 233                                 regulator-max-microvolt = <1550000>;
 234                                 regulator-always-on;
 235                         };
 236
 237                         reg_vgen3_2v8: vgen3 {                          /* not used */
 238                                 regulator-min-microvolt = <1800000>;
 239                                 regulator-max-microvolt = <3300000>;
 240                         };
 241                         reg_vgen4_1v8: vgen4 {                          /* NVCC_SD3 */
 242                                 regulator-min-microvolt = <1800000>;
 243                                 regulator-max-microvolt = <3300000>;
 244                                 regulator-always-on;
 245                         };
 246
 247                         reg_vgen5_2v5_sgtl: vgen5 {                     /* Pwr LED & 5V0_delayed enable */
 248                                 regulator-min-microvolt = <1800000>;
 249                                 regulator-max-microvolt = <3300000>;
 250                                 regulator-always-on;
 251                         };
 252
 253                         reg_vgen6_3v3: vgen6 {                          /* #V#_DELAYED enable, MIPI */
 254                                 regulator-min-microvolt = <1800000>;
 255                                 regulator-max-microvolt = <3300000>;
 256                                 regulator-always-on;
 257                         };
 258                 };
 259         };
 260 };
 261
 262 &i2c2 {
 263         clock-frequency = <100000>;
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_i2c2>;
 266         status = "okay";
 267 };
 268
 269 &i2c4 {
 270         clock-frequency = <100000>;
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_i2c4>;
 273         clocks = <&clks 116>;
 274         status = "okay";
 275 };
 276
 277 &pwm1 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_pwm1>;
 280         status = "okay";
 281 };
 282
 283 &pwm2 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_pwm2>;
 286         status = "okay";
 287 };
 288
 289 &pwm3 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_pwm3>;
 292         status = "okay";
 293 };
 294
 295 &pwm4 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_pwm4>;
 298         status = "okay";
 299 };
 300
 301 &ssi1 {
 302         status = "okay";
 303 };
 304
 305 &uart1 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_uart1>;
 308         status = "okay";
 309 };
 310
 311 &uart2 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_uart2>;
 314         status = "okay";
 315 };
 316
 317 &uart3 {
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_uart3>;
 320         status = "okay";
 321 };
 322
 323 &uart4 {
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_uart4>;
 326         status = "okay";
 327 };
 328
 329 &uart5 {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_uart5>;
 332         status = "okay";
 333 };
 334
 335 &usbh1 {
 336         dr_mode = "host";
 337         disable-over-current;
 338         status = "okay";
 339 };
 340
 341 &usbotg {
 342         vbus-supply = <&reg_usb_otg_vbus>;
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_usbotg>;
 345         disable-over-current;
 346         dr_mode = "otg";
 347         status = "okay";
 348 };
 349
 350 &usdhc2 {
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_usdhc2>;
 353         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 354         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 355         vmmc-supply = <&reg_3p3v>;
 356         status = "okay";
 357 };
 358
 359 &usdhc3 {
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&pinctrl_usdhc3>;
 362         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 363         wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 364         vmmc-supply = <&reg_3p3v>;
 365         status = "okay";
 366 };
 367
 368 &usdhc4 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_usdhc4>;
 371         vmmc-supply = <&reg_3p3v>;
 372         non-removable;
 373         status = "okay";
 374 };
 375
 376 &iomuxc {
 377         pinctrl-names = "default";
 378
 379         imx6-riotboard {
 380                 pinctrl_audmux: audmuxgrp {
 381                         fsl,pins = <
 382                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 383                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 384                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 385                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 386                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0         /* CAM_MCLK */
 387                         >;
 388                 };
 389
 390                 pinctrl_ecspi1: ecspi1grp {
 391                         fsl,pins = <
 392                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 393                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 394                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 395                                 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x000b1         /* CS0 */
 396                         >;
 397                 };
 398
 399                 pinctrl_ecspi2: ecspi2grp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x000b1         /* CS1 */
 402                                 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI     0x100b1
 403                                 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO     0x100b1
 404                                 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000b1         /* CS0 */
 405                                 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x100b1
 406                         >;
 407                 };
 408
 409                 pinctrl_ecspi3: ecspi3grp {
 410                         fsl,pins = <
 411                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 412                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 413                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 414                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x000b1         /* CS0 */
 415                                 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25       0x000b1         /* CS1 */
 416                         >;
 417                 };
 418
 419                 pinctrl_enet: enetgrp {
 420                         fsl,pins = <
 421                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 422                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 423                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 424                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 425                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 426                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 427                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 428                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 429                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 430                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030         /* AR8035 pin strapping: IO voltage: pull up */
 431                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030         /* AR8035 pin strapping: PHYADDR#0: pull down */
 432                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030         /* AR8035 pin strapping: PHYADDR#1: pull down */
 433                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030         /* AR8035 pin strapping: MODE#1: pull up */
 434                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030         /* AR8035 pin strapping: MODE#3: pull up */
 435                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0         /* AR8035 pin strapping: MODE#0: pull down */
 436                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8      /* GPIO16 -> AR8035 25MHz */
 437                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x130b0         /* RGMII_nRST */
 438                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x180b0         /* AR8035 interrupt */
 439                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 440                         >;
 441                 };
 442
 443                 pinctrl_i2c1: i2c1grp {
 444                         fsl,pins = <
 445                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 446                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 447                         >;
 448                 };
 449
 450                 pinctrl_i2c2: i2c2grp {
 451                         fsl,pins = <
 452                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 453                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 454                         >;
 455                 };
 456
 457                 pinctrl_i2c3: i2c3grp {
 458                         fsl,pins = <
 459                                 MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
 460                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 461                         >;
 462                 };
 463
 464                 pinctrl_i2c4: i2c4grp {
 465                         fsl,pins = <
 466                                 MX6QDL_PAD_GPIO_7__I2C4_SCL             0x4001b8b1
 467                                 MX6QDL_PAD_GPIO_8__I2C4_SDA             0x4001b8b1
 468                         >;
 469                 };
 470
 471                 pinctrl_led: ledgrp {
 472                         fsl,pins = <
 473                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* user led0 */
 474                                 MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x1b0b1 /* user led1 */
 475                         >;
 476                 };
 477
 478                 pinctrl_pwm1: pwm1grp {
 479                         fsl,pins = <
 480                                 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT         0x1b0b1
 481                         >;
 482                 };
 483
 484                 pinctrl_pwm2: pwm2grp {
 485                         fsl,pins = <
 486                                 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT         0x1b0b1
 487                         >;
 488                 };
 489
 490                 pinctrl_pwm3: pwm3grp {
 491                         fsl,pins = <
 492                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 493                         >;
 494                 };
 495
 496                 pinctrl_pwm4: pwm4grp {
 497                         fsl,pins = <
 498                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 499                         >;
 500                 };
 501
 502                 pinctrl_uart1: uart1grp {
 503                         fsl,pins = <
 504                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 505                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 506                         >;
 507                 };
 508
 509                 pinctrl_uart2: uart2grp {
 510                         fsl,pins = <
 511                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 512                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 513                         >;
 514                 };
 515
 516                 pinctrl_uart3: uart3grp {
 517                         fsl,pins = <
 518                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 519                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 520                         >;
 521                 };
 522
 523                 pinctrl_uart4: uart4grp {
 524                         fsl,pins = <
 525                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 526                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 527                         >;
 528                 };
 529
 530                 pinctrl_uart5: uart5grp {
 531                         fsl,pins = <
 532                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 533                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 534                         >;
 535                 };
 536
 537                 pinctrl_usbotg: usbotggrp {
 538                         fsl,pins = <
 539                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 540                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
 541                                 MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b0b0
 542                         >;
 543                 };
 544
 545                 pinctrl_usdhc2: usdhc2grp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 548                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 549                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 550                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 551                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 552                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 553                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* SD2 CD */
 554                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1f0b0 /* SD2 WP */
 555                         >;
 556                 };
 557
 558                 pinctrl_usdhc3: usdhc3grp {
 559                         fsl,pins = <
 560                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 561                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 562                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 563                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 564                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 565                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 566                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0 /* SD3 CD */
 567                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1f0b0 /* SD3 WP */
 568                         >;
 569                 };
 570
 571                 pinctrl_usdhc4: usdhc4grp {
 572                         fsl,pins = <
 573                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 574                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 575                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 576                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 577                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 578                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 579                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x17059 /* SD4 RST (eMMC) */
 580                         >;
 581                 };
 582         };
 583 };