Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6-logicpd-baseboard.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (C) 2019 Logic PD, Inc.
4
5 / {
6         keyboard {
7                 compatible = "gpio-keys";
8
9                 btn0 {
10                         gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
11                         label = "btn0";
12                         linux,code = <KEY_WAKEUP>;
13                         debounce-interval = <10>;
14                         wakeup-source;
15                 };
16
17                 btn1 {
18                         gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
19                         label = "btn1";
20                         linux,code = <KEY_WAKEUP>;
21                         debounce-interval = <10>;
22                         wakeup-source;
23                 };
24
25                 btn2 {
26                         gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
27                         label = "btn2";
28                         linux,code = <KEY_WAKEUP>;
29                         debounce-interval = <10>;
30                         wakeup-source;
31                 };
32
33                 btn3 {
34                         gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
35                         label = "btn3";
36                         linux,code = <KEY_WAKEUP>;
37                         debounce-interval = <10>;
38                         wakeup-source;
39                 };
40
41         };
42
43         leds {
44                 compatible = "gpio-leds";
45
46                 gen-led0 {
47                         label = "led0";
48                         pinctrl-names = "default";
49                         pinctrl-0 = <&pinctrl_led0>;
50                         gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
51                         linux,default-trigger = "cpu0";
52                 };
53
54                 gen-led1 {
55                         label = "led1";
56                         gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
57                 };
58
59                 gen-led2 {
60                         label = "led2";
61                         gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
62                         linux,default-trigger = "heartbeat";
63                 };
64
65                 gen-led3 {
66                         label = "led3";
67                         gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
68                         linux,default-trigger = "default-on";
69                 };
70         };
71
72         reg_usb_otg_vbus: regulator-otg-vbus {
73                 pinctrl-names = "default";
74                 pinctrl-0 = <&pinctrl_reg_usb_otg>;
75                 compatible = "regulator-fixed";
76                 regulator-name = "usb_otg_vbus";
77                 regulator-min-microvolt = <5000000>;
78                 regulator-max-microvolt = <5000000>;
79                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
80                 enable-active-high;
81         };
82
83         reg_usb_h1_vbus: regulator-usb-h1-vbus {
84                 pinctrl-names = "default";
85                 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
86                 compatible = "regulator-fixed";
87                 regulator-name = "usb_h1_vbus";
88                 regulator-min-microvolt = <5000000>;
89                 regulator-max-microvolt = <5000000>;
90                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
91                 startup-delay-us = <70000>;
92                 enable-active-high;
93         };
94
95         reg_3v3: regulator-3v3 {
96                 pinctrl-names = "default";
97                 pinctrl-0 = <&pinctrl_reg_3v3>;
98                 compatible = "regulator-fixed";
99                 regulator-name = "reg_3v3";
100                 regulator-min-microvolt = <3300000>;
101                 regulator-max-microvolt = <3300000>;
102                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
103                 startup-delay-us = <70000>;
104                 enable-active-high;
105                 regulator-always-on;
106         };
107
108         reg_enet: regulator-ethernet {
109                 pinctrl-names = "default";
110                 pinctrl-0 = <&pinctrl_reg_enet>;
111                 compatible = "regulator-fixed";
112                 regulator-name = "ethernet-supply";
113                 regulator-min-microvolt = <3300000>;
114                 regulator-max-microvolt = <3300000>;
115                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
116                 startup-delay-us = <70000>;
117                 enable-active-high;
118                 vin-supply = <&sw4_reg>;
119         };
120
121         reg_audio: regulator-audio {
122                 pinctrl-names = "default";
123                 pinctrl-0 = <&pinctrl_reg_audio>;
124                 compatible = "regulator-fixed";
125                 regulator-name = "3v3_aud";
126                 regulator-min-microvolt = <3300000>;
127                 regulator-max-microvolt = <3300000>;
128                 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
129                 enable-active-high;
130                 vin-supply = <&reg_3v3>;
131         };
132
133         reg_hdmi: regulator-hdmi {
134                 pinctrl-names = "default";
135                 pinctrl-0 = <&pinctrl_reg_hdmi>;
136                 compatible = "regulator-fixed";
137                 regulator-name = "hdmi-supply";
138                 regulator-min-microvolt = <3300000>;
139                 regulator-max-microvolt = <3300000>;
140                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
141                 enable-active-high;
142                 vin-supply = <&reg_3v3>;
143         };
144
145         reg_uart3: regulator-uart3 {
146                 pinctrl-names = "default";
147                 pinctrl-0 = <&pinctrl_reg_uart3>;
148                 compatible = "regulator-fixed";
149                 regulator-name = "uart3-supply";
150                 gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
151                 enable-active-high;
152                 regulator-always-on;
153                 vin-supply = <&reg_3v3>;
154         };
155
156         reg_1v8: regulator-1v8 {
157                 pinctrl-names = "default";
158                 pinctrl-0 = <&pinctrl_reg_1v8>;
159                 compatible = "regulator-fixed";
160                 regulator-name = "1v8-supply";
161                 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
162                 enable-active-high;
163                 regulator-always-on;
164                 vin-supply = <&reg_3v3>;
165         };
166
167         reg_pcie: regulator-pcie {
168                 compatible = "regulator-fixed";
169                 pinctrl-names = "default";
170                 pinctrl-0 = <&pinctrl_reg_pcie>;
171                 regulator-name = "mpcie_3v3";
172                 regulator-min-microvolt = <3300000>;
173                 regulator-max-microvolt = <3300000>;
174                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
175                 enable-active-high;
176         };
177
178         reg_mipi: regulator-mipi {
179                 compatible = "regulator-fixed";
180                 pinctrl-names = "default";
181                 pinctrl-0 = <&pinctrl_reg_mipi>;
182                 regulator-name = "mipi_pwr_en";
183                 regulator-min-microvolt = <2800000>;
184                 regulator-max-microvolt = <2800000>;
185                 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
186                 enable-active-high;
187         };
188
189         sound {
190                 compatible = "fsl,imx-audio-wm8962";
191                 model = "wm8962-audio";
192                 ssi-controller = <&ssi2>;
193                 audio-codec = <&wm8962>;
194                 audio-routing =
195                         "Headphone Jack", "HPOUTL",
196                         "Headphone Jack", "HPOUTR",
197                         "Ext Spk", "SPKOUTL",
198                         "Ext Spk", "SPKOUTR",
199                         "AMIC", "MICBIAS",
200                         "IN3R", "AMIC";
201                 mux-int-port = <2>;
202                 mux-ext-port = <4>;
203         };
204 };
205
206 &audmux {
207         pinctrl-names = "default";
208         pinctrl-0 = <&pinctrl_audmux>;
209         status = "okay";
210 };
211
212 &ecspi1 {
213         pinctrl-names = "default";
214         pinctrl-0 = <&pinctrl_ecspi1>;
215         status = "disabled";
216 };
217
218 &fec {
219         pinctrl-names = "default";
220         pinctrl-0 = <&pinctrl_enet>;
221         phy-mode = "rgmii-id";
222         phy-reset-duration = <10>;
223         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
224         phy-supply = <&reg_enet>;
225         interrupt-parent = <&gpio1>;
226         interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
227         status = "okay";
228 };
229
230 &i2c1 {
231         pinctrl-names = "default";
232         pinctrl-0 = <&pinctrl_i2c1>;
233         clock-frequency = <400000>;
234         status = "okay";
235
236         wm8962: audio-codec@1a {
237                 compatible = "wlf,wm8962";
238                 reg = <0x1a>;
239                 clocks = <&clks IMX6QDL_CLK_CKO>;
240                 clock-names = "xclk";
241                 DCVDD-supply = <&reg_audio>;
242                 DBVDD-supply = <&reg_audio>;
243                 AVDD-supply = <&reg_audio>;
244                 CPVDD-supply = <&reg_audio>;
245                 MICVDD-supply = <&reg_audio>;
246                 PLLVDD-supply = <&reg_audio>;
247                 SPKVDD1-supply = <&reg_audio>;
248                 SPKVDD2-supply = <&reg_audio>;
249                 gpio-cfg = <
250                         0x0000 /* 0:Default */
251                         0x0000 /* 1:Default */
252                         0x0000 /* 2:FN_DMICCLK */
253                         0x0000 /* 3:Default */
254                         0x0000 /* 4:FN_DMICCDAT */
255                         0x0000 /* 5:Default */
256                 >;
257         };
258 };
259
260 &i2c3 {
261         ov5640: camera@10 {
262                 compatible = "ovti,ov5640";
263                 pinctrl-names = "default";
264                 pinctrl-0 = <&pinctrl_ov5640>;
265                 reg = <0x10>;
266                 clocks = <&clks IMX6QDL_CLK_CKO>;
267                 clock-names = "xclk";
268                 DOVDD-supply = <&reg_mipi>;
269                 AVDD-supply = <&reg_mipi>;
270                 DVDD-supply = <&reg_mipi>;
271                 reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
272                 powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
273
274                 port {
275                         ov5640_to_mipi_csi2: endpoint {
276                                 remote-endpoint = <&mipi_csi2_in>;
277                                 clock-lanes = <0>;
278                                 data-lanes = <1 2>;
279                         };
280                 };
281         };
282
283         pcf8575: gpio@20 {
284                 pinctrl-names = "default";
285                 pinctrl-0 = <&pinctrl_pcf8574>;
286                 compatible = "nxp,pcf8575";
287                 reg = <0x20>;
288                 interrupt-parent = <&gpio6>;
289                 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
290                 gpio-controller;
291                 #gpio-cells = <2>;
292                 interrupt-controller;
293                 #interrupt-cells = <2>;
294                 lines-initial-states = <0x0710>;
295                 wakeup-source;
296         };
297 };
298
299 &ipu1_csi1_from_mipi_vc1 {
300         clock-lanes = <0>;
301         data-lanes = <1 2>;
302 };
303
304 &mipi_csi {
305         status = "okay";
306
307         port@0 {
308                 reg = <0>;
309
310                 mipi_csi2_in: endpoint {
311                         remote-endpoint = <&ov5640_to_mipi_csi2>;
312                         clock-lanes = <0>;
313                         data-lanes = <1 2>;
314                 };
315         };
316 };
317
318 &pcie {
319         pinctrl-names = "default";
320         pinctrl-0 = <&pinctrl_pcie>;
321         reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
322         vpcie-supply = <&reg_pcie>;
323         status = "okay";
324 };
325
326 &pwm3 {
327         pinctrl-names = "default";
328         pinctrl-0 = <&pinctrl_pwm3>;
329 };
330
331 &ssi2 {
332         status = "okay";
333 };
334
335 &uart3 {
336         pinctrl-names = "default";
337         pinctrl-0 = <&pinctrl_uart3>;
338         status = "okay";
339 };
340
341 &usbh1 {
342         vbus-supply = <&reg_usb_h1_vbus>;
343         status = "okay";
344 };
345
346 &usbotg {
347         vbus-supply = <&reg_usb_otg_vbus>;
348         pinctrl-names = "default";
349         pinctrl-0 = <&pinctrl_usbotg>;
350         disable-over-current;
351         dr_mode = "otg";
352         status = "okay";
353 };
354
355 &usdhc2 {
356         pinctrl-names = "default";
357         pinctrl-0 = <&pinctrl_usdhc2>;
358         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
359         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
360         vmmc-supply = <&reg_3v3>;
361         no-1-8-v;
362         keep-power-in-suspend;
363         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
364         status = "okay";
365 };
366
367 &iomuxc {
368         pinctrl_audmux: audmuxgrp {
369                 fsl,pins = <
370                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
371                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
372                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
373                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
374                 >;
375         };
376
377         pinctrl_ecspi1: ecspi1grp {
378                 fsl,pins = <
379                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
380                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
381                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
382                         MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0         0x100b1
383                 >;
384         };
385
386         pinctrl_enet: enetgrp {
387                 fsl,pins = <
388                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
389                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
390                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
391                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
392                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
393                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
394                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
395                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
396                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
397                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
398                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
399                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
400                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
401                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
402                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
403                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
404                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0 /* ENET_INT */
405                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x1b0b0 /* ETHR_nRST */
406                 >;
407         };
408
409         pinctrl_i2c1: i2c1grp {
410                 fsl,pins = <
411                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
412                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
413                 >;
414         };
415
416         pinctrl_led0: led0grp {
417             fsl,pins = <
418                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
419             >;
420         };
421
422         pinctrl_ov5640: ov5640grp {
423                 fsl,pins = <
424                         MX6QDL_PAD_EIM_D26__GPIO3_IO26  0x1b0b1
425                         MX6QDL_PAD_EIM_D27__GPIO3_IO27  0x1b0b1
426                 >;
427         };
428
429         pinctrl_pcf8574: pcf8575grp {
430                 fsl,pins = <
431                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
432                 >;
433         };
434
435         pinctrl_pcie: pciegrp {
436                 fsl,pins = <
437                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
438                         MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
439                 >;
440         };
441
442         pinctrl_pwm3: pwm3grp {
443             fsl,pins = <
444                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
445             >;
446         };
447
448         pinctrl_reg_1v8: reg1v8grp {
449             fsl,pins = <
450                 MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
451             >;
452         };
453
454         pinctrl_reg_3v3: reg3v3grp {
455             fsl,pins = <
456                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b0
457             >;
458         };
459
460         pinctrl_reg_audio: reg-audiogrp {
461                 fsl,pins = <
462                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
463                 >;
464         };
465
466         pinctrl_reg_enet: reg-enetgrp {
467                 fsl,pins = <
468                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x1b0b0
469                 >;
470         };
471
472         pinctrl_reg_hdmi: reg-hdmigrp {
473                 fsl,pins = <
474                         MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x1b0b0
475                 >;
476         };
477
478         pinctrl_reg_mipi: reg-mipigrp {
479                 fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
480         };
481
482         pinctrl_reg_pcie: reg-pciegrp {
483                 fsl,pins = <
484                         MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
485                         >;
486         };
487
488         pinctrl_reg_uart3: reguart3grp {
489             fsl,pins = <
490                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
491             >;
492         };
493
494         pinctrl_reg_usb_h1_vbus: usbh1grp {
495                 fsl,pins = <
496                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
497                 >;
498         };
499
500         pinctrl_reg_usb_otg: reg-usb-otggrp {
501                 fsl,pins = <
502                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
503                 >;
504         };
505
506         pinctrl_uart3: uart3grp {
507                 fsl,pins = <
508                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
509                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
510                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
511                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B         0x1b0b1
512                 >;
513         };
514
515         pinctrl_usbotg: usbotggrp {
516                 fsl,pins = <
517                         MX6QDL_PAD_GPIO_1__USB_OTG_ID   0xd17059
518                 >;
519         };
520
521         pinctrl_usdhc2: usdhc2grp {
522                 fsl,pins = <
523                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
524                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17069
525                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
526                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17069
527                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17069
528                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17069
529                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17069
530                 >;
531         };
532
533         pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
534                 fsl,pins = <
535                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
536                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
537                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
538                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
539                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
540                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
541                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
542                 >;
543         };
544
545         pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
546                 fsl,pins = <
547                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
548                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
549                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
550                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
551                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
552                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
553                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
554                 >;
555         };
556
557 };