arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "imx53-pinfunc.h"
  14 #include <dt-bindings/clock/imx5-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22         /*
  23          * The decompressor and also some bootloaders rely on a
  24          * pre-existing /chosen node to be available to insert the
  25          * command line and merge other ATAGS info.
  26          * Also for U-Boot there must be a pre-existing /memory node.
  27          */
  28         chosen {};
  29         memory { device_type = "memory"; reg = <0 0>; };
  30
  31         aliases {
  32                 ethernet0 = &fec;
  33                 gpio0 = &gpio1;
  34                 gpio1 = &gpio2;
  35                 gpio2 = &gpio3;
  36                 gpio3 = &gpio4;
  37                 gpio4 = &gpio5;
  38                 gpio5 = &gpio6;
  39                 gpio6 = &gpio7;
  40                 i2c0 = &i2c1;
  41                 i2c1 = &i2c2;
  42                 i2c2 = &i2c3;
  43                 mmc0 = &esdhc1;
  44                 mmc1 = &esdhc2;
  45                 mmc2 = &esdhc3;
  46                 mmc3 = &esdhc4;
  47                 serial0 = &uart1;
  48                 serial1 = &uart2;
  49                 serial2 = &uart3;
  50                 serial3 = &uart4;
  51                 serial4 = &uart5;
  52                 spi0 = &ecspi1;
  53                 spi1 = &ecspi2;
  54                 spi2 = &cspi;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 cpu0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a8";
  63                         reg = <0x0>;
  64                         clocks = <&clks IMX5_CLK_ARM>;
  65                         clock-latency = <61036>;
  66                         voltage-tolerance = <5>;
  67                         operating-points = <
  68                                 /* kHz */
  69                                  166666  850000
  70                                  400000  900000
  71                                  800000 1050000
  72                                 1000000 1200000
  73                                 1200000 1300000
  74                         >;
  75                 };
  76         };
  77
  78         display-subsystem {
  79                 compatible = "fsl,imx-display-subsystem";
  80                 ports = <&ipu_di0>, <&ipu_di1>;
  81         };
  82
  83         tzic: tz-interrupt-controller@fffc000 {
  84                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  85                 interrupt-controller;
  86                 #interrupt-cells = <1>;
  87                 reg = <0x0fffc000 0x4000>;
  88         };
  89
  90         clocks {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 ckil {
  95                         compatible = "fsl,imx-ckil", "fixed-clock";
  96                         #clock-cells = <0>;
  97                         clock-frequency = <32768>;
  98                 };
  99
 100                 ckih1 {
 101                         compatible = "fsl,imx-ckih1", "fixed-clock";
 102                         #clock-cells = <0>;
 103                         clock-frequency = <22579200>;
 104                 };
 105
 106                 ckih2 {
 107                         compatible = "fsl,imx-ckih2", "fixed-clock";
 108                         #clock-cells = <0>;
 109                         clock-frequency = <0>;
 110                 };
 111
 112                 osc {
 113                         compatible = "fsl,imx-osc", "fixed-clock";
 114                         #clock-cells = <0>;
 115                         clock-frequency = <24000000>;
 116                 };
 117         };
 118
 119         pmu {
 120                 compatible = "arm,cortex-a8-pmu";
 121                 interrupt-parent = <&tzic>;
 122                 interrupts = <77>;
 123         };
 124
 125         usbphy0: usbphy-0 {
 126                 compatible = "usb-nop-xceiv";
 127                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 128                 clock-names = "main_clk";
 129                 #phy-cells = <0>;
 130                 status = "okay";
 131         };
 132
 133         usbphy1: usbphy-1 {
 134                 compatible = "usb-nop-xceiv";
 135                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 136                 clock-names = "main_clk";
 137                 #phy-cells = <0>;
 138                 status = "okay";
 139         };
 140
 141         soc {
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 compatible = "simple-bus";
 145                 interrupt-parent = <&tzic>;
 146                 ranges;
 147
 148                 sata: sata@10000000 {
 149                         compatible = "fsl,imx53-ahci";
 150                         reg = <0x10000000 0x1000>;
 151                         interrupts = <28>;
 152                         clocks = <&clks IMX5_CLK_SATA_GATE>,
 153                                  <&clks IMX5_CLK_SATA_REF>,
 154                                  <&clks IMX5_CLK_AHB>;
 155                         clock-names = "sata", "sata_ref", "ahb";
 156                         status = "disabled";
 157                 };
 158
 159                 ipu: ipu@18000000 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         compatible = "fsl,imx53-ipu";
 163                         reg = <0x18000000 0x08000000>;
 164                         interrupts = <11 10>;
 165                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 166                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 167                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 168                         clock-names = "bus", "di0", "di1";
 169                         resets = <&src 2>;
 170
 171                         ipu_csi0: port@0 {
 172                                 reg = <0>;
 173                         };
 174
 175                         ipu_csi1: port@1 {
 176                                 reg = <1>;
 177                         };
 178
 179                         ipu_di0: port@2 {
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 reg = <2>;
 183
 184                                 ipu_di0_disp0: endpoint@0 {
 185                                         reg = <0>;
 186                                 };
 187
 188                                 ipu_di0_lvds0: endpoint@1 {
 189                                         reg = <1>;
 190                                         remote-endpoint = <&lvds0_in>;
 191                                 };
 192                         };
 193
 194                         ipu_di1: port@3 {
 195                                 #address-cells = <1>;
 196                                 #size-cells = <0>;
 197                                 reg = <3>;
 198
 199                                 ipu_di1_disp1: endpoint@0 {
 200                                         reg = <0>;
 201                                 };
 202
 203                                 ipu_di1_lvds1: endpoint@1 {
 204                                         reg = <1>;
 205                                         remote-endpoint = <&lvds1_in>;
 206                                 };
 207
 208                                 ipu_di1_tve: endpoint@2 {
 209                                         reg = <2>;
 210                                         remote-endpoint = <&tve_in>;
 211                                 };
 212                         };
 213                 };
 214
 215                 aips@50000000 { /* AIPS1 */
 216                         compatible = "fsl,aips-bus", "simple-bus";
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219                         reg = <0x50000000 0x10000000>;
 220                         ranges;
 221
 222                         spba@50000000 {
 223                                 compatible = "fsl,spba-bus", "simple-bus";
 224                                 #address-cells = <1>;
 225                                 #size-cells = <1>;
 226                                 reg = <0x50000000 0x40000>;
 227                                 ranges;
 228
 229                                 esdhc1: esdhc@50004000 {
 230                                         compatible = "fsl,imx53-esdhc";
 231                                         reg = <0x50004000 0x4000>;
 232                                         interrupts = <1>;
 233                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 234                                                  <&clks IMX5_CLK_DUMMY>,
 235                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 236                                         clock-names = "ipg", "ahb", "per";
 237                                         bus-width = <4>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 esdhc2: esdhc@50008000 {
 242                                         compatible = "fsl,imx53-esdhc";
 243                                         reg = <0x50008000 0x4000>;
 244                                         interrupts = <2>;
 245                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 246                                                  <&clks IMX5_CLK_DUMMY>,
 247                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 248                                         clock-names = "ipg", "ahb", "per";
 249                                         bus-width = <4>;
 250                                         status = "disabled";
 251                                 };
 252
 253                                 uart3: serial@5000c000 {
 254                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 255                                         reg = <0x5000c000 0x4000>;
 256                                         interrupts = <33>;
 257                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 258                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 259                                         clock-names = "ipg", "per";
 260                                         dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
 261                                         dma-names = "rx", "tx";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 ecspi1: ecspi@50010000 {
 266                                         #address-cells = <1>;
 267                                         #size-cells = <0>;
 268                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 269                                         reg = <0x50010000 0x4000>;
 270                                         interrupts = <36>;
 271                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 272                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 273                                         clock-names = "ipg", "per";
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ssi2: ssi@50014000 {
 278                                         #sound-dai-cells = <0>;
 279                                         compatible = "fsl,imx53-ssi",
 280                                                         "fsl,imx51-ssi",
 281                                                         "fsl,imx21-ssi";
 282                                         reg = <0x50014000 0x4000>;
 283                                         interrupts = <30>;
 284                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 285                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 286                                         clock-names = "ipg", "baud";
 287                                         dmas = <&sdma 24 1 0>,
 288                                                <&sdma 25 1 0>;
 289                                         dma-names = "rx", "tx";
 290                                         fsl,fifo-depth = <15>;
 291                                         status = "disabled";
 292                                 };
 293
 294                                 esdhc3: esdhc@50020000 {
 295                                         compatible = "fsl,imx53-esdhc";
 296                                         reg = <0x50020000 0x4000>;
 297                                         interrupts = <3>;
 298                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 299                                                  <&clks IMX5_CLK_DUMMY>,
 300                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 301                                         clock-names = "ipg", "ahb", "per";
 302                                         bus-width = <4>;
 303                                         status = "disabled";
 304                                 };
 305
 306                                 esdhc4: esdhc@50024000 {
 307                                         compatible = "fsl,imx53-esdhc";
 308                                         reg = <0x50024000 0x4000>;
 309                                         interrupts = <4>;
 310                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 311                                                  <&clks IMX5_CLK_DUMMY>,
 312                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 313                                         clock-names = "ipg", "ahb", "per";
 314                                         bus-width = <4>;
 315                                         status = "disabled";
 316                                 };
 317                         };
 318
 319                         aipstz1: bridge@53f00000 {
 320                                 compatible = "fsl,imx53-aipstz";
 321                                 reg = <0x53f00000 0x60>;
 322                         };
 323
 324                         usbotg: usb@53f80000 {
 325                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 326                                 reg = <0x53f80000 0x0200>;
 327                                 interrupts = <18>;
 328                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 329                                 fsl,usbmisc = <&usbmisc 0>;
 330                                 fsl,usbphy = <&usbphy0>;
 331                                 status = "disabled";
 332                         };
 333
 334                         usbh1: usb@53f80200 {
 335                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 336                                 reg = <0x53f80200 0x0200>;
 337                                 interrupts = <14>;
 338                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 339                                 fsl,usbmisc = <&usbmisc 1>;
 340                                 fsl,usbphy = <&usbphy1>;
 341                                 dr_mode = "host";
 342                                 status = "disabled";
 343                         };
 344
 345                         usbh2: usb@53f80400 {
 346                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 347                                 reg = <0x53f80400 0x0200>;
 348                                 interrupts = <16>;
 349                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 350                                 fsl,usbmisc = <&usbmisc 2>;
 351                                 dr_mode = "host";
 352                                 status = "disabled";
 353                         };
 354
 355                         usbh3: usb@53f80600 {
 356                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 357                                 reg = <0x53f80600 0x0200>;
 358                                 interrupts = <17>;
 359                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 360                                 fsl,usbmisc = <&usbmisc 3>;
 361                                 dr_mode = "host";
 362                                 status = "disabled";
 363                         };
 364
 365                         usbmisc: usbmisc@53f80800 {
 366                                 #index-cells = <1>;
 367                                 compatible = "fsl,imx53-usbmisc";
 368                                 reg = <0x53f80800 0x200>;
 369                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 370                         };
 371
 372                         gpio1: gpio@53f84000 {
 373                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 374                                 reg = <0x53f84000 0x4000>;
 375                                 interrupts = <50 51>;
 376                                 gpio-controller;
 377                                 #gpio-cells = <2>;
 378                                 interrupt-controller;
 379                                 #interrupt-cells = <2>;
 380                         };
 381
 382                         gpio2: gpio@53f88000 {
 383                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 384                                 reg = <0x53f88000 0x4000>;
 385                                 interrupts = <52 53>;
 386                                 gpio-controller;
 387                                 #gpio-cells = <2>;
 388                                 interrupt-controller;
 389                                 #interrupt-cells = <2>;
 390                         };
 391
 392                         gpio3: gpio@53f8c000 {
 393                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 394                                 reg = <0x53f8c000 0x4000>;
 395                                 interrupts = <54 55>;
 396                                 gpio-controller;
 397                                 #gpio-cells = <2>;
 398                                 interrupt-controller;
 399                                 #interrupt-cells = <2>;
 400                         };
 401
 402                         gpio4: gpio@53f90000 {
 403                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 404                                 reg = <0x53f90000 0x4000>;
 405                                 interrupts = <56 57>;
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                         };
 411
 412                         kpp: kpp@53f94000 {
 413                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 414                                 reg = <0x53f94000 0x4000>;
 415                                 interrupts = <60>;
 416                                 clocks = <&clks IMX5_CLK_DUMMY>;
 417                                 status = "disabled";
 418                         };
 419
 420                         wdog1: wdog@53f98000 {
 421                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 422                                 reg = <0x53f98000 0x4000>;
 423                                 interrupts = <58>;
 424                                 clocks = <&clks IMX5_CLK_DUMMY>;
 425                         };
 426
 427                         wdog2: wdog@53f9c000 {
 428                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 429                                 reg = <0x53f9c000 0x4000>;
 430                                 interrupts = <59>;
 431                                 clocks = <&clks IMX5_CLK_DUMMY>;
 432                                 status = "disabled";
 433                         };
 434
 435                         gpt: timer@53fa0000 {
 436                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 437                                 reg = <0x53fa0000 0x4000>;
 438                                 interrupts = <39>;
 439                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 440                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 441                                 clock-names = "ipg", "per";
 442                         };
 443
 444                         srtc: rtc@53fa4000 {
 445                                 compatible = "fsl,imx53-rtc";
 446                                 reg = <0x53fa4000 0x4000>;
 447                                 interrupts = <24>;
 448                                 clocks = <&clks IMX5_CLK_SRTC_GATE>;
 449                         };
 450
 451                         iomuxc: iomuxc@53fa8000 {
 452                                 compatible = "fsl,imx53-iomuxc";
 453                                 reg = <0x53fa8000 0x4000>;
 454                         };
 455
 456                         gpr: iomuxc-gpr@53fa8000 {
 457                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 458                                 reg = <0x53fa8000 0xc>;
 459                         };
 460
 461                         ldb: ldb@53fa8008 {
 462                                 #address-cells = <1>;
 463                                 #size-cells = <0>;
 464                                 compatible = "fsl,imx53-ldb";
 465                                 reg = <0x53fa8008 0x4>;
 466                                 gpr = <&gpr>;
 467                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 468                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 469                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 470                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 471                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 472                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 473                                 clock-names = "di0_pll", "di1_pll",
 474                                               "di0_sel", "di1_sel",
 475                                               "di0", "di1";
 476                                 status = "disabled";
 477
 478                                 lvds-channel@0 {
 479                                         #address-cells = <1>;
 480                                         #size-cells = <0>;
 481                                         reg = <0>;
 482                                         status = "disabled";
 483
 484                                         port@0 {
 485                                                 reg = <0>;
 486
 487                                                 lvds0_in: endpoint {
 488                                                         remote-endpoint = <&ipu_di0_lvds0>;
 489                                                 };
 490                                         };
 491                                 };
 492
 493                                 lvds-channel@1 {
 494                                         #address-cells = <1>;
 495                                         #size-cells = <0>;
 496                                         reg = <1>;
 497                                         status = "disabled";
 498
 499                                         port@1 {
 500                                                 reg = <1>;
 501
 502                                                 lvds1_in: endpoint {
 503                                                         remote-endpoint = <&ipu_di1_lvds1>;
 504                                                 };
 505                                         };
 506                                 };
 507                         };
 508
 509                         pwm1: pwm@53fb4000 {
 510                                 #pwm-cells = <2>;
 511                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 512                                 reg = <0x53fb4000 0x4000>;
 513                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 514                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 515                                 clock-names = "ipg", "per";
 516                                 interrupts = <61>;
 517                         };
 518
 519                         pwm2: pwm@53fb8000 {
 520                                 #pwm-cells = <2>;
 521                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 522                                 reg = <0x53fb8000 0x4000>;
 523                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 524                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 525                                 clock-names = "ipg", "per";
 526                                 interrupts = <94>;
 527                         };
 528
 529                         uart1: serial@53fbc000 {
 530                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 531                                 reg = <0x53fbc000 0x4000>;
 532                                 interrupts = <31>;
 533                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 534                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 535                                 clock-names = "ipg", "per";
 536                                 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
 537                                 dma-names = "rx", "tx";
 538                                 status = "disabled";
 539                         };
 540
 541                         uart2: serial@53fc0000 {
 542                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 543                                 reg = <0x53fc0000 0x4000>;
 544                                 interrupts = <32>;
 545                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 546                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 547                                 clock-names = "ipg", "per";
 548                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
 549                                 dma-names = "rx", "tx";
 550                                 status = "disabled";
 551                         };
 552
 553                         can1: can@53fc8000 {
 554                                 compatible = "fsl,imx53-flexcan";
 555                                 reg = <0x53fc8000 0x4000>;
 556                                 interrupts = <82>;
 557                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 558                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 559                                 clock-names = "ipg", "per";
 560                                 status = "disabled";
 561                         };
 562
 563                         can2: can@53fcc000 {
 564                                 compatible = "fsl,imx53-flexcan";
 565                                 reg = <0x53fcc000 0x4000>;
 566                                 interrupts = <83>;
 567                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 568                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 569                                 clock-names = "ipg", "per";
 570                                 status = "disabled";
 571                         };
 572
 573                         src: src@53fd0000 {
 574                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 575                                 reg = <0x53fd0000 0x4000>;
 576                                 #reset-cells = <1>;
 577                         };
 578
 579                         clks: ccm@53fd4000{
 580                                 compatible = "fsl,imx53-ccm";
 581                                 reg = <0x53fd4000 0x4000>;
 582                                 interrupts = <0 71 0x04 0 72 0x04>;
 583                                 #clock-cells = <1>;
 584                         };
 585
 586                         gpio5: gpio@53fdc000 {
 587                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 588                                 reg = <0x53fdc000 0x4000>;
 589                                 interrupts = <103 104>;
 590                                 gpio-controller;
 591                                 #gpio-cells = <2>;
 592                                 interrupt-controller;
 593                                 #interrupt-cells = <2>;
 594                         };
 595
 596                         gpio6: gpio@53fe0000 {
 597                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 598                                 reg = <0x53fe0000 0x4000>;
 599                                 interrupts = <105 106>;
 600                                 gpio-controller;
 601                                 #gpio-cells = <2>;
 602                                 interrupt-controller;
 603                                 #interrupt-cells = <2>;
 604                         };
 605
 606                         gpio7: gpio@53fe4000 {
 607                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 608                                 reg = <0x53fe4000 0x4000>;
 609                                 interrupts = <107 108>;
 610                                 gpio-controller;
 611                                 #gpio-cells = <2>;
 612                                 interrupt-controller;
 613                                 #interrupt-cells = <2>;
 614                         };
 615
 616                         i2c3: i2c@53fec000 {
 617                                 #address-cells = <1>;
 618                                 #size-cells = <0>;
 619                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 620                                 reg = <0x53fec000 0x4000>;
 621                                 interrupts = <64>;
 622                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 623                                 status = "disabled";
 624                         };
 625
 626                         uart4: serial@53ff0000 {
 627                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 628                                 reg = <0x53ff0000 0x4000>;
 629                                 interrupts = <13>;
 630                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 631                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 632                                 clock-names = "ipg", "per";
 633                                 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
 634                                 dma-names = "rx", "tx";
 635                                 status = "disabled";
 636                         };
 637                 };
 638
 639                 aips@60000000 { /* AIPS2 */
 640                         compatible = "fsl,aips-bus", "simple-bus";
 641                         #address-cells = <1>;
 642                         #size-cells = <1>;
 643                         reg = <0x60000000 0x10000000>;
 644                         ranges;
 645
 646                         aipstz2: bridge@63f00000 {
 647                                 compatible = "fsl,imx53-aipstz";
 648                                 reg = <0x63f00000 0x60>;
 649                         };
 650
 651                         iim: iim@63f98000 {
 652                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 653                                 reg = <0x63f98000 0x4000>;
 654                                 interrupts = <69>;
 655                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 656                         };
 657
 658                         uart5: serial@63f90000 {
 659                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 660                                 reg = <0x63f90000 0x4000>;
 661                                 interrupts = <86>;
 662                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 663                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 664                                 clock-names = "ipg", "per";
 665                                 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
 666                                 dma-names = "rx", "tx";
 667                                 status = "disabled";
 668                         };
 669
 670                         owire: owire@63fa4000 {
 671                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 672                                 reg = <0x63fa4000 0x4000>;
 673                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 674                                 status = "disabled";
 675                         };
 676
 677                         ecspi2: ecspi@63fac000 {
 678                                 #address-cells = <1>;
 679                                 #size-cells = <0>;
 680                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 681                                 reg = <0x63fac000 0x4000>;
 682                                 interrupts = <37>;
 683                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 684                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 685                                 clock-names = "ipg", "per";
 686                                 status = "disabled";
 687                         };
 688
 689                         sdma: sdma@63fb0000 {
 690                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 691                                 reg = <0x63fb0000 0x4000>;
 692                                 interrupts = <6>;
 693                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 694                                          <&clks IMX5_CLK_SDMA_GATE>;
 695                                 clock-names = "ipg", "ahb";
 696                                 #dma-cells = <3>;
 697                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 698                         };
 699
 700                         cspi: cspi@63fc0000 {
 701                                 #address-cells = <1>;
 702                                 #size-cells = <0>;
 703                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 704                                 reg = <0x63fc0000 0x4000>;
 705                                 interrupts = <38>;
 706                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 707                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 708                                 clock-names = "ipg", "per";
 709                                 status = "disabled";
 710                         };
 711
 712                         i2c2: i2c@63fc4000 {
 713                                 #address-cells = <1>;
 714                                 #size-cells = <0>;
 715                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 716                                 reg = <0x63fc4000 0x4000>;
 717                                 interrupts = <63>;
 718                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 719                                 status = "disabled";
 720                         };
 721
 722                         i2c1: i2c@63fc8000 {
 723                                 #address-cells = <1>;
 724                                 #size-cells = <0>;
 725                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 726                                 reg = <0x63fc8000 0x4000>;
 727                                 interrupts = <62>;
 728                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 729                                 status = "disabled";
 730                         };
 731
 732                         ssi1: ssi@63fcc000 {
 733                                 #sound-dai-cells = <0>;
 734                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 735                                                 "fsl,imx21-ssi";
 736                                 reg = <0x63fcc000 0x4000>;
 737                                 interrupts = <29>;
 738                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 739                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 740                                 clock-names = "ipg", "baud";
 741                                 dmas = <&sdma 28 0 0>,
 742                                        <&sdma 29 0 0>;
 743                                 dma-names = "rx", "tx";
 744                                 fsl,fifo-depth = <15>;
 745                                 status = "disabled";
 746                         };
 747
 748                         audmux: audmux@63fd0000 {
 749                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 750                                 reg = <0x63fd0000 0x4000>;
 751                                 status = "disabled";
 752                         };
 753
 754                         nfc: nand@63fdb000 {
 755                                 compatible = "fsl,imx53-nand";
 756                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 757                                 interrupts = <8>;
 758                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 759                                 status = "disabled";
 760                         };
 761
 762                         ssi3: ssi@63fe8000 {
 763                                 #sound-dai-cells = <0>;
 764                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 765                                                 "fsl,imx21-ssi";
 766                                 reg = <0x63fe8000 0x4000>;
 767                                 interrupts = <96>;
 768                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 769                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 770                                 clock-names = "ipg", "baud";
 771                                 dmas = <&sdma 46 0 0>,
 772                                        <&sdma 47 0 0>;
 773                                 dma-names = "rx", "tx";
 774                                 fsl,fifo-depth = <15>;
 775                                 status = "disabled";
 776                         };
 777
 778                         fec: ethernet@63fec000 {
 779                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 780                                 reg = <0x63fec000 0x4000>;
 781                                 interrupts = <87>;
 782                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 783                                          <&clks IMX5_CLK_FEC_GATE>,
 784                                          <&clks IMX5_CLK_FEC_GATE>;
 785                                 clock-names = "ipg", "ahb", "ptp";
 786                                 status = "disabled";
 787                         };
 788
 789                         tve: tve@63ff0000 {
 790                                 compatible = "fsl,imx53-tve";
 791                                 reg = <0x63ff0000 0x1000>;
 792                                 interrupts = <92>;
 793                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 794                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 795                                 clock-names = "tve", "di_sel";
 796                                 status = "disabled";
 797
 798                                 port {
 799                                         tve_in: endpoint {
 800                                                 remote-endpoint = <&ipu_di1_tve>;
 801                                         };
 802                                 };
 803                         };
 804
 805                         vpu: vpu@63ff4000 {
 806                                 compatible = "fsl,imx53-vpu", "cnm,coda7541";
 807                                 reg = <0x63ff4000 0x1000>;
 808                                 interrupts = <9>;
 809                                 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
 810                                          <&clks IMX5_CLK_VPU_GATE>;
 811                                 clock-names = "per", "ahb";
 812                                 resets = <&src 1>;
 813                                 iram = <&ocram>;
 814                         };
 815
 816                         sahara: crypto@63ff8000 {
 817                                 compatible = "fsl,imx53-sahara";
 818                                 reg = <0x63ff8000 0x4000>;
 819                                 interrupts = <19 20>;
 820                                 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
 821                                          <&clks IMX5_CLK_SAHARA_IPG_GATE>;
 822                                 clock-names = "ipg", "ahb";
 823                         };
 824                 };
 825
 826                 ocram: sram@f8000000 {
 827                         compatible = "mmio-sram";
 828                         reg = <0xf8000000 0x20000>;
 829                         clocks = <&clks IMX5_CLK_OCRAM>;
 830                 };
 831         };
 832 };