arch/arm/boot/dts/imx51.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include "imx51-pinfunc.h"
   7 #include <dt-bindings/clock/imx5-clock.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         /*
  16          * The decompressor and also some bootloaders rely on a
  17          * pre-existing /chosen node to be available to insert the
  18          * command line and merge other ATAGS info.
  19          * Also for U-Boot there must be a pre-existing /memory node.
  20          */
  21         chosen {};
  22         memory { device_type = "memory"; };
  23
  24         aliases {
  25                 ethernet0 = &fec;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 mmc0 = &esdhc1;
  33                 mmc1 = &esdhc2;
  34                 mmc2 = &esdhc3;
  35                 mmc3 = &esdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &cspi;
  42         };
  43
  44         tzic: tz-interrupt-controller@e0000000 {
  45                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <1>;
  48                 reg = <0xe0000000 0x4000>;
  49         };
  50
  51         clocks {
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         #clock-cells = <0>;
  55                         clock-frequency = <32768>;
  56                 };
  57
  58                 ckih1 {
  59                         compatible = "fsl,imx-ckih1", "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-frequency = <0>;
  62                 };
  63
  64                 ckih2 {
  65                         compatible = "fsl,imx-ckih2", "fixed-clock";
  66                         #clock-cells = <0>;
  67                         clock-frequency = <0>;
  68                 };
  69
  70                 osc {
  71                         compatible = "fsl,imx-osc", "fixed-clock";
  72                         #clock-cells = <0>;
  73                         clock-frequency = <24000000>;
  74                 };
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80                 cpu: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a8";
  83                         reg = <0>;
  84                         clock-latency = <62500>;
  85                         clocks = <&clks IMX5_CLK_CPU_PODF>;
  86                         clock-names = "cpu";
  87                         operating-points = <
  88                                 166000  1000000
  89                                 600000  1050000
  90                                 800000  1100000
  91                         >;
  92                         voltage-tolerance = <5>;
  93                 };
  94         };
  95
  96         pmu: pmu {
  97                 compatible = "arm,cortex-a8-pmu";
  98                 interrupt-parent = <&tzic>;
  99                 interrupts = <77>;
 100         };
 101
 102         usbphy0: usbphy0 {
 103                 compatible = "usb-nop-xceiv";
 104                 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
 105                 clock-names = "main_clk";
 106                 #phy-cells = <0>;
 107         };
 108
 109         display-subsystem {
 110                 compatible = "fsl,imx-display-subsystem";
 111                 ports = <&ipu_di0>, <&ipu_di1>;
 112         };
 113
 114         soc {
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 compatible = "simple-bus";
 118                 interrupt-parent = <&tzic>;
 119                 ranges;
 120
 121                 iram: iram@1ffe0000 {
 122                         compatible = "mmio-sram";
 123                         reg = <0x1ffe0000 0x20000>;
 124                 };
 125
 126                 ipu: ipu@40000000 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         compatible = "fsl,imx51-ipu";
 130                         reg = <0x40000000 0x20000000>;
 131                         interrupts = <11 10>;
 132                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 133                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 134                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 135                         clock-names = "bus", "di0", "di1";
 136                         resets = <&src 2>;
 137
 138                         ipu_di0: port@2 {
 139                                 reg = <2>;
 140
 141                                 ipu_di0_disp1: endpoint {
 142                                 };
 143                         };
 144
 145                         ipu_di1: port@3 {
 146                                 reg = <3>;
 147
 148                                 ipu_di1_disp2: endpoint {
 149                                 };
 150                         };
 151                 };
 152
 153                 aips@70000000 { /* AIPS1 */
 154                         compatible = "fsl,aips-bus", "simple-bus";
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         reg = <0x70000000 0x10000000>;
 158                         ranges;
 159
 160                         spba@70000000 {
 161                                 compatible = "fsl,spba-bus", "simple-bus";
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164                                 reg = <0x70000000 0x40000>;
 165                                 ranges;
 166
 167                                 esdhc1: esdhc@70004000 {
 168                                         compatible = "fsl,imx51-esdhc";
 169                                         reg = <0x70004000 0x4000>;
 170                                         interrupts = <1>;
 171                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 172                                                  <&clks IMX5_CLK_DUMMY>,
 173                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 174                                         clock-names = "ipg", "ahb", "per";
 175                                         status = "disabled";
 176                                 };
 177
 178                                 esdhc2: esdhc@70008000 {
 179                                         compatible = "fsl,imx51-esdhc";
 180                                         reg = <0x70008000 0x4000>;
 181                                         interrupts = <2>;
 182                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 183                                                  <&clks IMX5_CLK_DUMMY>,
 184                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 185                                         clock-names = "ipg", "ahb", "per";
 186                                         bus-width = <4>;
 187                                         status = "disabled";
 188                                 };
 189
 190                                 uart3: serial@7000c000 {
 191                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 192                                         reg = <0x7000c000 0x4000>;
 193                                         interrupts = <33>;
 194                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 195                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 196                                         clock-names = "ipg", "per";
 197                                         status = "disabled";
 198                                 };
 199
 200                                 ecspi1: spi@70010000 {
 201                                         #address-cells = <1>;
 202                                         #size-cells = <0>;
 203                                         compatible = "fsl,imx51-ecspi";
 204                                         reg = <0x70010000 0x4000>;
 205                                         interrupts = <36>;
 206                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 207                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 208                                         clock-names = "ipg", "per";
 209                                         status = "disabled";
 210                                 };
 211
 212                                 ssi2: ssi@70014000 {
 213                                         #sound-dai-cells = <0>;
 214                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 215                                         reg = <0x70014000 0x4000>;
 216                                         interrupts = <30>;
 217                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 218                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 219                                         clock-names = "ipg", "baud";
 220                                         dmas = <&sdma 24 1 0>,
 221                                                <&sdma 25 1 0>;
 222                                         dma-names = "rx", "tx";
 223                                         fsl,fifo-depth = <15>;
 224                                         status = "disabled";
 225                                 };
 226
 227                                 esdhc3: esdhc@70020000 {
 228                                         compatible = "fsl,imx51-esdhc";
 229                                         reg = <0x70020000 0x4000>;
 230                                         interrupts = <3>;
 231                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 232                                                  <&clks IMX5_CLK_DUMMY>,
 233                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 234                                         clock-names = "ipg", "ahb", "per";
 235                                         bus-width = <4>;
 236                                         status = "disabled";
 237                                 };
 238
 239                                 esdhc4: esdhc@70024000 {
 240                                         compatible = "fsl,imx51-esdhc";
 241                                         reg = <0x70024000 0x4000>;
 242                                         interrupts = <4>;
 243                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 244                                                  <&clks IMX5_CLK_DUMMY>,
 245                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 246                                         clock-names = "ipg", "ahb", "per";
 247                                         bus-width = <4>;
 248                                         status = "disabled";
 249                                 };
 250                         };
 251
 252                         aipstz1: bridge@73f00000 {
 253                                 compatible = "fsl,imx51-aipstz";
 254                                 reg = <0x73f00000 0x60>;
 255                         };
 256
 257                         usbotg: usb@73f80000 {
 258                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 259                                 reg = <0x73f80000 0x0200>;
 260                                 interrupts = <18>;
 261                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 262                                 fsl,usbmisc = <&usbmisc 0>;
 263                                 fsl,usbphy = <&usbphy0>;
 264                                 status = "disabled";
 265                         };
 266
 267                         usbh1: usb@73f80200 {
 268                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 269                                 reg = <0x73f80200 0x0200>;
 270                                 interrupts = <14>;
 271                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 272                                 fsl,usbmisc = <&usbmisc 1>;
 273                                 dr_mode = "host";
 274                                 status = "disabled";
 275                         };
 276
 277                         usbh2: usb@73f80400 {
 278                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 279                                 reg = <0x73f80400 0x0200>;
 280                                 interrupts = <16>;
 281                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 282                                 fsl,usbmisc = <&usbmisc 2>;
 283                                 dr_mode = "host";
 284                                 status = "disabled";
 285                         };
 286
 287                         usbh3: usb@73f80600 {
 288                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 289                                 reg = <0x73f80600 0x0200>;
 290                                 interrupts = <17>;
 291                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 292                                 fsl,usbmisc = <&usbmisc 3>;
 293                                 dr_mode = "host";
 294                                 status = "disabled";
 295                         };
 296
 297                         usbmisc: usbmisc@73f80800 {
 298                                 #index-cells = <1>;
 299                                 compatible = "fsl,imx51-usbmisc";
 300                                 reg = <0x73f80800 0x200>;
 301                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 302                         };
 303
 304                         gpio1: gpio@73f84000 {
 305                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 306                                 reg = <0x73f84000 0x4000>;
 307                                 interrupts = <50 51>;
 308                                 gpio-controller;
 309                                 #gpio-cells = <2>;
 310                                 interrupt-controller;
 311                                 #interrupt-cells = <2>;
 312                         };
 313
 314                         gpio2: gpio@73f88000 {
 315                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 316                                 reg = <0x73f88000 0x4000>;
 317                                 interrupts = <52 53>;
 318                                 gpio-controller;
 319                                 #gpio-cells = <2>;
 320                                 interrupt-controller;
 321                                 #interrupt-cells = <2>;
 322                         };
 323
 324                         gpio3: gpio@73f8c000 {
 325                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 326                                 reg = <0x73f8c000 0x4000>;
 327                                 interrupts = <54 55>;
 328                                 gpio-controller;
 329                                 #gpio-cells = <2>;
 330                                 interrupt-controller;
 331                                 #interrupt-cells = <2>;
 332                         };
 333
 334                         gpio4: gpio@73f90000 {
 335                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 336                                 reg = <0x73f90000 0x4000>;
 337                                 interrupts = <56 57>;
 338                                 gpio-controller;
 339                                 #gpio-cells = <2>;
 340                                 interrupt-controller;
 341                                 #interrupt-cells = <2>;
 342                         };
 343
 344                         kpp: kpp@73f94000 {
 345                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 346                                 reg = <0x73f94000 0x4000>;
 347                                 interrupts = <60>;
 348                                 clocks = <&clks IMX5_CLK_DUMMY>;
 349                                 status = "disabled";
 350                         };
 351
 352                         wdog1: wdog@73f98000 {
 353                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 354                                 reg = <0x73f98000 0x4000>;
 355                                 interrupts = <58>;
 356                                 clocks = <&clks IMX5_CLK_DUMMY>;
 357                         };
 358
 359                         wdog2: wdog@73f9c000 {
 360                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 361                                 reg = <0x73f9c000 0x4000>;
 362                                 interrupts = <59>;
 363                                 clocks = <&clks IMX5_CLK_DUMMY>;
 364                                 status = "disabled";
 365                         };
 366
 367                         gpt: timer@73fa0000 {
 368                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 369                                 reg = <0x73fa0000 0x4000>;
 370                                 interrupts = <39>;
 371                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 372                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 373                                 clock-names = "ipg", "per";
 374                         };
 375
 376                         iomuxc: iomuxc@73fa8000 {
 377                                 compatible = "fsl,imx51-iomuxc";
 378                                 reg = <0x73fa8000 0x4000>;
 379                         };
 380
 381                         pwm1: pwm@73fb4000 {
 382                                 #pwm-cells = <2>;
 383                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 384                                 reg = <0x73fb4000 0x4000>;
 385                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 386                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 387                                 clock-names = "ipg", "per";
 388                                 interrupts = <61>;
 389                         };
 390
 391                         pwm2: pwm@73fb8000 {
 392                                 #pwm-cells = <2>;
 393                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 394                                 reg = <0x73fb8000 0x4000>;
 395                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 396                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 397                                 clock-names = "ipg", "per";
 398                                 interrupts = <94>;
 399                         };
 400
 401                         uart1: serial@73fbc000 {
 402                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 403                                 reg = <0x73fbc000 0x4000>;
 404                                 interrupts = <31>;
 405                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 406                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 407                                 clock-names = "ipg", "per";
 408                                 status = "disabled";
 409                         };
 410
 411                         uart2: serial@73fc0000 {
 412                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 413                                 reg = <0x73fc0000 0x4000>;
 414                                 interrupts = <32>;
 415                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 416                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 417                                 clock-names = "ipg", "per";
 418                                 status = "disabled";
 419                         };
 420
 421                         src: src@73fd0000 {
 422                                 compatible = "fsl,imx51-src";
 423                                 reg = <0x73fd0000 0x4000>;
 424                                 #reset-cells = <1>;
 425                         };
 426
 427                         clks: ccm@73fd4000{
 428                                 compatible = "fsl,imx51-ccm";
 429                                 reg = <0x73fd4000 0x4000>;
 430                                 interrupts = <0 71 0x04 0 72 0x04>;
 431                                 #clock-cells = <1>;
 432                         };
 433                 };
 434
 435                 aips@80000000 { /* AIPS2 */
 436                         compatible = "fsl,aips-bus", "simple-bus";
 437                         #address-cells = <1>;
 438                         #size-cells = <1>;
 439                         reg = <0x80000000 0x10000000>;
 440                         ranges;
 441
 442                         aipstz2: bridge@83f00000 {
 443                                 compatible = "fsl,imx51-aipstz";
 444                                 reg = <0x83f00000 0x60>;
 445                         };
 446
 447                         iim: iim@83f98000 {
 448                                 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
 449                                 reg = <0x83f98000 0x4000>;
 450                                 interrupts = <69>;
 451                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 452                         };
 453
 454                         tigerp: tigerp@83fa0000 {
 455                                 compatible = "fsl,imx51-tigerp";
 456                                 reg = <0x83fa0000 0x28>;
 457                         };
 458
 459                         owire: owire@83fa4000 {
 460                                 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
 461                                 reg = <0x83fa4000 0x4000>;
 462                                 interrupts = <88>;
 463                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 464                                 status = "disabled";
 465                         };
 466
 467                         ecspi2: spi@83fac000 {
 468                                 #address-cells = <1>;
 469                                 #size-cells = <0>;
 470                                 compatible = "fsl,imx51-ecspi";
 471                                 reg = <0x83fac000 0x4000>;
 472                                 interrupts = <37>;
 473                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 474                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 475                                 clock-names = "ipg", "per";
 476                                 status = "disabled";
 477                         };
 478
 479                         sdma: sdma@83fb0000 {
 480                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 481                                 reg = <0x83fb0000 0x4000>;
 482                                 interrupts = <6>;
 483                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 484                                          <&clks IMX5_CLK_SDMA_GATE>;
 485                                 clock-names = "ipg", "ahb";
 486                                 #dma-cells = <3>;
 487                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 488                         };
 489
 490                         cspi: spi@83fc0000 {
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 494                                 reg = <0x83fc0000 0x4000>;
 495                                 interrupts = <38>;
 496                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 497                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 498                                 clock-names = "ipg", "per";
 499                                 status = "disabled";
 500                         };
 501
 502                         i2c2: i2c@83fc4000 {
 503                                 #address-cells = <1>;
 504                                 #size-cells = <0>;
 505                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 506                                 reg = <0x83fc4000 0x4000>;
 507                                 interrupts = <63>;
 508                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 509                                 status = "disabled";
 510                         };
 511
 512                         i2c1: i2c@83fc8000 {
 513                                 #address-cells = <1>;
 514                                 #size-cells = <0>;
 515                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 516                                 reg = <0x83fc8000 0x4000>;
 517                                 interrupts = <62>;
 518                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 519                                 status = "disabled";
 520                         };
 521
 522                         ssi1: ssi@83fcc000 {
 523                                 #sound-dai-cells = <0>;
 524                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 525                                 reg = <0x83fcc000 0x4000>;
 526                                 interrupts = <29>;
 527                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 528                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 529                                 clock-names = "ipg", "baud";
 530                                 dmas = <&sdma 28 0 0>,
 531                                        <&sdma 29 0 0>;
 532                                 dma-names = "rx", "tx";
 533                                 fsl,fifo-depth = <15>;
 534                                 status = "disabled";
 535                         };
 536
 537                         audmux: audmux@83fd0000 {
 538                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 539                                 reg = <0x83fd0000 0x4000>;
 540                                 clocks = <&clks IMX5_CLK_DUMMY>;
 541                                 clock-names = "audmux";
 542                                 status = "disabled";
 543                         };
 544
 545                         m4if: m4if@83fd8000 {
 546                                 compatible = "fsl,imx51-m4if";
 547                                 reg = <0x83fd8000 0x1000>;
 548                         };
 549
 550                         weim: weim@83fda000 {
 551                                 #address-cells = <2>;
 552                                 #size-cells = <1>;
 553                                 compatible = "fsl,imx51-weim";
 554                                 reg = <0x83fda000 0x1000>;
 555                                 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
 556                                 ranges = <
 557                                         0 0 0xb0000000 0x08000000
 558                                         1 0 0xb8000000 0x08000000
 559                                         2 0 0xc0000000 0x08000000
 560                                         3 0 0xc8000000 0x04000000
 561                                         4 0 0xcc000000 0x02000000
 562                                         5 0 0xce000000 0x02000000
 563                                 >;
 564                                 status = "disabled";
 565                         };
 566
 567                         nfc: nand@83fdb000 {
 568                                 #address-cells = <1>;
 569                                 #size-cells = <1>;
 570                                 compatible = "fsl,imx51-nand";
 571                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 572                                 interrupts = <8>;
 573                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 574                                 status = "disabled";
 575                         };
 576
 577                         pata: pata@83fe0000 {
 578                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 579                                 reg = <0x83fe0000 0x4000>;
 580                                 interrupts = <70>;
 581                                 clocks = <&clks IMX5_CLK_PATA_GATE>;
 582                                 status = "disabled";
 583                         };
 584
 585                         ssi3: ssi@83fe8000 {
 586                                 #sound-dai-cells = <0>;
 587                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 588                                 reg = <0x83fe8000 0x4000>;
 589                                 interrupts = <96>;
 590                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 591                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 592                                 clock-names = "ipg", "baud";
 593                                 dmas = <&sdma 46 0 0>,
 594                                        <&sdma 47 0 0>;
 595                                 dma-names = "rx", "tx";
 596                                 fsl,fifo-depth = <15>;
 597                                 status = "disabled";
 598                         };
 599
 600                         fec: ethernet@83fec000 {
 601                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 602                                 reg = <0x83fec000 0x4000>;
 603                                 interrupts = <87>;
 604                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 605                                          <&clks IMX5_CLK_FEC_GATE>,
 606                                          <&clks IMX5_CLK_FEC_GATE>;
 607                                 clock-names = "ipg", "ahb", "ptp";
 608                                 status = "disabled";
 609                         };
 610
 611                         vpu: vpu@83ff4000 {
 612                                 compatible = "fsl,imx51-vpu", "cnm,codahx4";
 613                                 reg = <0x83ff4000 0x1000>;
 614                                 interrupts = <9>;
 615                                 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
 616                                          <&clks IMX5_CLK_VPU_GATE>;
 617                                 clock-names = "per", "ahb";
 618                                 resets = <&src 1>;
 619                                 iram = <&iram>;
 620                         };
 621
 622                         sahara: crypto@83ff8000 {
 623                                 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
 624                                 reg = <0x83ff8000 0x4000>;
 625                                 interrupts = <19 20>;
 626                                 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
 627                                          <&clks IMX5_CLK_SAHARA_IPG_GATE>;
 628                                 clock-names = "ipg", "ahb";
 629                         };
 630                 };
 631         };
 632 };