Merge tag 'v3.15-rc1' into perf/urgent
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx51.dtsi
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  * Copyright 2011 Linaro Ltd.
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19
20 / {
21         aliases {
22                 gpio0 = &gpio1;
23                 gpio1 = &gpio2;
24                 gpio2 = &gpio3;
25                 gpio3 = &gpio4;
26                 i2c0 = &i2c1;
27                 i2c1 = &i2c2;
28                 mmc0 = &esdhc1;
29                 mmc1 = &esdhc2;
30                 mmc2 = &esdhc3;
31                 mmc3 = &esdhc4;
32                 serial0 = &uart1;
33                 serial1 = &uart2;
34                 serial2 = &uart3;
35                 spi0 = &ecspi1;
36                 spi1 = &ecspi2;
37                 spi2 = &cspi;
38         };
39
40         tzic: tz-interrupt-controller@e0000000 {
41                 compatible = "fsl,imx51-tzic", "fsl,tzic";
42                 interrupt-controller;
43                 #interrupt-cells = <1>;
44                 reg = <0xe0000000 0x4000>;
45         };
46
47         clocks {
48                 #address-cells = <1>;
49                 #size-cells = <0>;
50
51                 ckil {
52                         compatible = "fsl,imx-ckil", "fixed-clock";
53                         clock-frequency = <32768>;
54                 };
55
56                 ckih1 {
57                         compatible = "fsl,imx-ckih1", "fixed-clock";
58                         clock-frequency = <0>;
59                 };
60
61                 ckih2 {
62                         compatible = "fsl,imx-ckih2", "fixed-clock";
63                         clock-frequency = <0>;
64                 };
65
66                 osc {
67                         compatible = "fsl,imx-osc", "fixed-clock";
68                         clock-frequency = <24000000>;
69                 };
70         };
71
72         cpus {
73                 #address-cells = <1>;
74                 #size-cells = <0>;
75                 cpu: cpu@0 {
76                         device_type = "cpu";
77                         compatible = "arm,cortex-a8";
78                         reg = <0>;
79                         clock-latency = <62500>;
80                         clocks = <&clks IMX5_CLK_CPU_PODF>;
81                         clock-names = "cpu";
82                         operating-points = <
83                                 166000  1000000
84                                 600000  1050000
85                                 800000  1100000
86                         >;
87                         voltage-tolerance = <5>;
88                 };
89         };
90
91         usbphy {
92                 #address-cells = <1>;
93                 #size-cells = <0>;
94                 compatible = "simple-bus";
95
96                 usbphy0: usbphy@0 {
97                         compatible = "usb-nop-xceiv";
98                         reg = <0>;
99                         clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
100                         clock-names = "main_clk";
101                 };
102         };
103
104         display-subsystem {
105                 compatible = "fsl,imx-display-subsystem";
106                 ports = <&ipu_di0>, <&ipu_di1>;
107         };
108
109         soc {
110                 #address-cells = <1>;
111                 #size-cells = <1>;
112                 compatible = "simple-bus";
113                 interrupt-parent = <&tzic>;
114                 ranges;
115
116                 iram: iram@1ffe0000 {
117                         compatible = "mmio-sram";
118                         reg = <0x1ffe0000 0x20000>;
119                 };
120
121                 ipu: ipu@40000000 {
122                         #address-cells = <1>;
123                         #size-cells = <0>;
124                         compatible = "fsl,imx51-ipu";
125                         reg = <0x40000000 0x20000000>;
126                         interrupts = <11 10>;
127                         clocks = <&clks IMX5_CLK_IPU_GATE>,
128                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
129                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
130                         clock-names = "bus", "di0", "di1";
131                         resets = <&src 2>;
132
133                         ipu_di0: port@2 {
134                                 reg = <2>;
135
136                                 ipu_di0_disp0: endpoint {
137                                 };
138                         };
139
140                         ipu_di1: port@3 {
141                                 reg = <3>;
142
143                                 ipu_di1_disp1: endpoint {
144                                 };
145                         };
146                 };
147
148                 aips@70000000 { /* AIPS1 */
149                         compatible = "fsl,aips-bus", "simple-bus";
150                         #address-cells = <1>;
151                         #size-cells = <1>;
152                         reg = <0x70000000 0x10000000>;
153                         ranges;
154
155                         spba@70000000 {
156                                 compatible = "fsl,spba-bus", "simple-bus";
157                                 #address-cells = <1>;
158                                 #size-cells = <1>;
159                                 reg = <0x70000000 0x40000>;
160                                 ranges;
161
162                                 esdhc1: esdhc@70004000 {
163                                         compatible = "fsl,imx51-esdhc";
164                                         reg = <0x70004000 0x4000>;
165                                         interrupts = <1>;
166                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
167                                                  <&clks IMX5_CLK_DUMMY>,
168                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
169                                         clock-names = "ipg", "ahb", "per";
170                                         status = "disabled";
171                                 };
172
173                                 esdhc2: esdhc@70008000 {
174                                         compatible = "fsl,imx51-esdhc";
175                                         reg = <0x70008000 0x4000>;
176                                         interrupts = <2>;
177                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
178                                                  <&clks IMX5_CLK_DUMMY>,
179                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
180                                         clock-names = "ipg", "ahb", "per";
181                                         bus-width = <4>;
182                                         status = "disabled";
183                                 };
184
185                                 uart3: serial@7000c000 {
186                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
187                                         reg = <0x7000c000 0x4000>;
188                                         interrupts = <33>;
189                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
190                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
191                                         clock-names = "ipg", "per";
192                                         status = "disabled";
193                                 };
194
195                                 ecspi1: ecspi@70010000 {
196                                         #address-cells = <1>;
197                                         #size-cells = <0>;
198                                         compatible = "fsl,imx51-ecspi";
199                                         reg = <0x70010000 0x4000>;
200                                         interrupts = <36>;
201                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
202                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
203                                         clock-names = "ipg", "per";
204                                         status = "disabled";
205                                 };
206
207                                 ssi2: ssi@70014000 {
208                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
209                                         reg = <0x70014000 0x4000>;
210                                         interrupts = <30>;
211                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
212                                         dmas = <&sdma 24 1 0>,
213                                                <&sdma 25 1 0>;
214                                         dma-names = "rx", "tx";
215                                         fsl,fifo-depth = <15>;
216                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
217                                         status = "disabled";
218                                 };
219
220                                 esdhc3: esdhc@70020000 {
221                                         compatible = "fsl,imx51-esdhc";
222                                         reg = <0x70020000 0x4000>;
223                                         interrupts = <3>;
224                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
225                                                  <&clks IMX5_CLK_DUMMY>,
226                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
227                                         clock-names = "ipg", "ahb", "per";
228                                         bus-width = <4>;
229                                         status = "disabled";
230                                 };
231
232                                 esdhc4: esdhc@70024000 {
233                                         compatible = "fsl,imx51-esdhc";
234                                         reg = <0x70024000 0x4000>;
235                                         interrupts = <4>;
236                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
237                                                  <&clks IMX5_CLK_DUMMY>,
238                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
239                                         clock-names = "ipg", "ahb", "per";
240                                         bus-width = <4>;
241                                         status = "disabled";
242                                 };
243                         };
244
245                         usbotg: usb@73f80000 {
246                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
247                                 reg = <0x73f80000 0x0200>;
248                                 interrupts = <18>;
249                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
250                                 fsl,usbmisc = <&usbmisc 0>;
251                                 fsl,usbphy = <&usbphy0>;
252                                 status = "disabled";
253                         };
254
255                         usbh1: usb@73f80200 {
256                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
257                                 reg = <0x73f80200 0x0200>;
258                                 interrupts = <14>;
259                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
260                                 fsl,usbmisc = <&usbmisc 1>;
261                                 status = "disabled";
262                         };
263
264                         usbh2: usb@73f80400 {
265                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
266                                 reg = <0x73f80400 0x0200>;
267                                 interrupts = <16>;
268                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
269                                 fsl,usbmisc = <&usbmisc 2>;
270                                 status = "disabled";
271                         };
272
273                         usbh3: usb@73f80600 {
274                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
275                                 reg = <0x73f80600 0x0200>;
276                                 interrupts = <17>;
277                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
278                                 fsl,usbmisc = <&usbmisc 3>;
279                                 status = "disabled";
280                         };
281
282                         usbmisc: usbmisc@73f80800 {
283                                 #index-cells = <1>;
284                                 compatible = "fsl,imx51-usbmisc";
285                                 reg = <0x73f80800 0x200>;
286                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
287                         };
288
289                         gpio1: gpio@73f84000 {
290                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
291                                 reg = <0x73f84000 0x4000>;
292                                 interrupts = <50 51>;
293                                 gpio-controller;
294                                 #gpio-cells = <2>;
295                                 interrupt-controller;
296                                 #interrupt-cells = <2>;
297                         };
298
299                         gpio2: gpio@73f88000 {
300                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
301                                 reg = <0x73f88000 0x4000>;
302                                 interrupts = <52 53>;
303                                 gpio-controller;
304                                 #gpio-cells = <2>;
305                                 interrupt-controller;
306                                 #interrupt-cells = <2>;
307                         };
308
309                         gpio3: gpio@73f8c000 {
310                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
311                                 reg = <0x73f8c000 0x4000>;
312                                 interrupts = <54 55>;
313                                 gpio-controller;
314                                 #gpio-cells = <2>;
315                                 interrupt-controller;
316                                 #interrupt-cells = <2>;
317                         };
318
319                         gpio4: gpio@73f90000 {
320                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
321                                 reg = <0x73f90000 0x4000>;
322                                 interrupts = <56 57>;
323                                 gpio-controller;
324                                 #gpio-cells = <2>;
325                                 interrupt-controller;
326                                 #interrupt-cells = <2>;
327                         };
328
329                         kpp: kpp@73f94000 {
330                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
331                                 reg = <0x73f94000 0x4000>;
332                                 interrupts = <60>;
333                                 clocks = <&clks IMX5_CLK_DUMMY>;
334                                 status = "disabled";
335                         };
336
337                         wdog1: wdog@73f98000 {
338                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
339                                 reg = <0x73f98000 0x4000>;
340                                 interrupts = <58>;
341                                 clocks = <&clks IMX5_CLK_DUMMY>;
342                         };
343
344                         wdog2: wdog@73f9c000 {
345                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
346                                 reg = <0x73f9c000 0x4000>;
347                                 interrupts = <59>;
348                                 clocks = <&clks IMX5_CLK_DUMMY>;
349                                 status = "disabled";
350                         };
351
352                         gpt: timer@73fa0000 {
353                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
354                                 reg = <0x73fa0000 0x4000>;
355                                 interrupts = <39>;
356                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
357                                          <&clks IMX5_CLK_GPT_HF_GATE>;
358                                 clock-names = "ipg", "per";
359                         };
360
361                         iomuxc: iomuxc@73fa8000 {
362                                 compatible = "fsl,imx51-iomuxc";
363                                 reg = <0x73fa8000 0x4000>;
364                         };
365
366                         pwm1: pwm@73fb4000 {
367                                 #pwm-cells = <2>;
368                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
369                                 reg = <0x73fb4000 0x4000>;
370                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
371                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
372                                 clock-names = "ipg", "per";
373                                 interrupts = <61>;
374                         };
375
376                         pwm2: pwm@73fb8000 {
377                                 #pwm-cells = <2>;
378                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
379                                 reg = <0x73fb8000 0x4000>;
380                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
381                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
382                                 clock-names = "ipg", "per";
383                                 interrupts = <94>;
384                         };
385
386                         uart1: serial@73fbc000 {
387                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
388                                 reg = <0x73fbc000 0x4000>;
389                                 interrupts = <31>;
390                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
391                                          <&clks IMX5_CLK_UART1_PER_GATE>;
392                                 clock-names = "ipg", "per";
393                                 status = "disabled";
394                         };
395
396                         uart2: serial@73fc0000 {
397                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
398                                 reg = <0x73fc0000 0x4000>;
399                                 interrupts = <32>;
400                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
401                                          <&clks IMX5_CLK_UART2_PER_GATE>;
402                                 clock-names = "ipg", "per";
403                                 status = "disabled";
404                         };
405
406                         src: src@73fd0000 {
407                                 compatible = "fsl,imx51-src";
408                                 reg = <0x73fd0000 0x4000>;
409                                 #reset-cells = <1>;
410                         };
411
412                         clks: ccm@73fd4000{
413                                 compatible = "fsl,imx51-ccm";
414                                 reg = <0x73fd4000 0x4000>;
415                                 interrupts = <0 71 0x04 0 72 0x04>;
416                                 #clock-cells = <1>;
417                         };
418                 };
419
420                 aips@80000000 { /* AIPS2 */
421                         compatible = "fsl,aips-bus", "simple-bus";
422                         #address-cells = <1>;
423                         #size-cells = <1>;
424                         reg = <0x80000000 0x10000000>;
425                         ranges;
426
427                         iim: iim@83f98000 {
428                                 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
429                                 reg = <0x83f98000 0x4000>;
430                                 interrupts = <69>;
431                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
432                         };
433
434                         owire: owire@83fa4000 {
435                                 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
436                                 reg = <0x83fa4000 0x4000>;
437                                 interrupts = <88>;
438                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
439                                 status = "disabled";
440                         };
441
442                         ecspi2: ecspi@83fac000 {
443                                 #address-cells = <1>;
444                                 #size-cells = <0>;
445                                 compatible = "fsl,imx51-ecspi";
446                                 reg = <0x83fac000 0x4000>;
447                                 interrupts = <37>;
448                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
449                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
450                                 clock-names = "ipg", "per";
451                                 status = "disabled";
452                         };
453
454                         sdma: sdma@83fb0000 {
455                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
456                                 reg = <0x83fb0000 0x4000>;
457                                 interrupts = <6>;
458                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
459                                          <&clks IMX5_CLK_SDMA_GATE>;
460                                 clock-names = "ipg", "ahb";
461                                 #dma-cells = <3>;
462                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
463                         };
464
465                         cspi: cspi@83fc0000 {
466                                 #address-cells = <1>;
467                                 #size-cells = <0>;
468                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
469                                 reg = <0x83fc0000 0x4000>;
470                                 interrupts = <38>;
471                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
472                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
473                                 clock-names = "ipg", "per";
474                                 status = "disabled";
475                         };
476
477                         i2c2: i2c@83fc4000 {
478                                 #address-cells = <1>;
479                                 #size-cells = <0>;
480                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
481                                 reg = <0x83fc4000 0x4000>;
482                                 interrupts = <63>;
483                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
484                                 status = "disabled";
485                         };
486
487                         i2c1: i2c@83fc8000 {
488                                 #address-cells = <1>;
489                                 #size-cells = <0>;
490                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
491                                 reg = <0x83fc8000 0x4000>;
492                                 interrupts = <62>;
493                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
494                                 status = "disabled";
495                         };
496
497                         ssi1: ssi@83fcc000 {
498                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
499                                 reg = <0x83fcc000 0x4000>;
500                                 interrupts = <29>;
501                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
502                                 dmas = <&sdma 28 0 0>,
503                                        <&sdma 29 0 0>;
504                                 dma-names = "rx", "tx";
505                                 fsl,fifo-depth = <15>;
506                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
507                                 status = "disabled";
508                         };
509
510                         audmux: audmux@83fd0000 {
511                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
512                                 reg = <0x83fd0000 0x4000>;
513                                 clocks = <&clks IMX5_CLK_DUMMY>;
514                                 clock-names = "audmux";
515                                 status = "disabled";
516                         };
517
518                         weim: weim@83fda000 {
519                                 #address-cells = <2>;
520                                 #size-cells = <1>;
521                                 compatible = "fsl,imx51-weim";
522                                 reg = <0x83fda000 0x1000>;
523                                 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
524                                 ranges = <
525                                         0 0 0xb0000000 0x08000000
526                                         1 0 0xb8000000 0x08000000
527                                         2 0 0xc0000000 0x08000000
528                                         3 0 0xc8000000 0x04000000
529                                         4 0 0xcc000000 0x02000000
530                                         5 0 0xce000000 0x02000000
531                                 >;
532                                 status = "disabled";
533                         };
534
535                         nfc: nand@83fdb000 {
536                                 compatible = "fsl,imx51-nand";
537                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
538                                 interrupts = <8>;
539                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
540                                 status = "disabled";
541                         };
542
543                         pata: pata@83fe0000 {
544                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
545                                 reg = <0x83fe0000 0x4000>;
546                                 interrupts = <70>;
547                                 clocks = <&clks IMX5_CLK_PATA_GATE>;
548                                 status = "disabled";
549                         };
550
551                         ssi3: ssi@83fe8000 {
552                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
553                                 reg = <0x83fe8000 0x4000>;
554                                 interrupts = <96>;
555                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
556                                 dmas = <&sdma 46 0 0>,
557                                        <&sdma 47 0 0>;
558                                 dma-names = "rx", "tx";
559                                 fsl,fifo-depth = <15>;
560                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
561                                 status = "disabled";
562                         };
563
564                         fec: ethernet@83fec000 {
565                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
566                                 reg = <0x83fec000 0x4000>;
567                                 interrupts = <87>;
568                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
569                                          <&clks IMX5_CLK_FEC_GATE>,
570                                          <&clks IMX5_CLK_FEC_GATE>;
571                                 clock-names = "ipg", "ahb", "ptp";
572                                 status = "disabled";
573                         };
574                 };
575         };
576 };