Merge branch 'spi-4.20' into spi-4.21 for bcm stuff.
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx51-zii-rdu1.dts
1 /*
2  * Copyright (C) 2017 Zodiac Inflight Innovations
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License
11  *     version 2 as published by the Free Software Foundation.
12  *
13  *     This file is distributed in the hope that it will be useful,
14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *     GNU General Public License for more details.
17  *
18  * Or, alternatively,
19  *
20  *  b) Permission is hereby granted, free of charge, to any person
21  *     obtaining a copy of this software and associated documentation
22  *     files (the "Software"), to deal in the Software without
23  *     restriction, including without limitation the rights to use,
24  *     copy, modify, merge, publish, distribute, sublicense, and/or
25  *     sell copies of the Software, and to permit persons to whom the
26  *     Software is furnished to do so, subject to the following
27  *     conditions:
28  *
29  *     The above copyright notice and this permission notice shall be
30  *     included in all copies or substantial portions of the Software.
31  *
32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39  *     OTHER DEALINGS IN THE SOFTWARE.
40  */
41
42 /dts-v1/;
43 #include "imx51.dtsi"
44 #include <dt-bindings/sound/fsl-imx-audmux.h>
45
46 / {
47         model = "ZII RDU1 Board";
48         compatible = "zii,imx51-rdu1", "fsl,imx51";
49
50         chosen {
51                 stdout-path = &uart1;
52         };
53
54         /* Will be filled by the bootloader */
55         memory@90000000 {
56                 reg = <0x90000000 0>;
57         };
58
59         aliases {
60                 mdio-gpio0 = &mdio_gpio;
61                 rtc0 = &ds1341;
62         };
63
64         clk_26M_osc: 26M_osc {
65                 compatible = "fixed-clock";
66                 #clock-cells = <0>;
67                 clock-frequency = <26000000>;
68         };
69
70         clk_26M_osc_gate: 26M_gate {
71                 compatible = "gpio-gate-clock";
72                 pinctrl-names = "default";
73                 pinctrl-0 = <&pinctrl_clk26mhz>;
74                 clocks = <&clk_26M_osc>;
75                 #clock-cells = <0>;
76                 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
77         };
78
79         clk_26M_usb: usbhost_gate {
80                 compatible = "gpio-gate-clock";
81                 pinctrl-names = "default";
82                 pinctrl-0 = <&pinctrl_usbgate26mhz>;
83                 clocks = <&clk_26M_osc_gate>;
84                 #clock-cells = <0>;
85                 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
86         };
87
88         clk_26M_snd: snd_gate {
89                 compatible = "gpio-gate-clock";
90                 pinctrl-names = "default";
91                 pinctrl-0 = <&pinctrl_sndgate26mhz>;
92                 clocks = <&clk_26M_osc_gate>;
93                 #clock-cells = <0>;
94                 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
95         };
96
97         reg_5p0v_main: regulator-5p0v-main {
98                 compatible = "regulator-fixed";
99                 regulator-name = "5V_MAIN";
100                 regulator-min-microvolt = <5000000>;
101                 regulator-max-microvolt = <5000000>;
102                 regulator-always-on;
103         };
104
105         reg_3p3v: regulator-3p3v {
106                 compatible = "regulator-fixed";
107                 regulator-name = "3.3V";
108                 regulator-min-microvolt = <3300000>;
109                 regulator-max-microvolt = <3300000>;
110                 regulator-always-on;
111         };
112
113         disp0 {
114                 compatible = "fsl,imx-parallel-display";
115                 pinctrl-names = "default";
116                 pinctrl-0 = <&pinctrl_ipu_disp1>;
117
118                 #address-cells = <1>;
119                 #size-cells = <0>;
120
121                 port@0 {
122                         reg = <0>;
123
124                         display_in: endpoint {
125                                 remote-endpoint = <&ipu_di0_disp1>;
126                         };
127                 };
128
129                 port@1 {
130                         reg = <1>;
131
132                         display_out: endpoint {
133                                 remote-endpoint = <&panel_in>;
134                         };
135                 };
136         };
137
138         panel {
139                 /* no compatible here, bootloader will patch in correct one */
140                 pinctrl-names = "default";
141                 pinctrl-0 = <&pinctrl_panel>;
142                 power-supply = <&reg_3p3v>;
143                 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
144                 status = "disabled";
145
146                 port {
147                         panel_in: endpoint {
148                                 remote-endpoint = <&display_out>;
149                         };
150                 };
151         };
152
153         i2c_gpio: i2c-gpio {
154                 compatible = "i2c-gpio";
155                 pinctrl-names = "default";
156                 pinctrl-0 = <&pinctrl_swi2c>;
157                 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
158                         <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
159                 i2c-gpio,delay-us = <50>;
160                 status = "okay";
161
162                 #address-cells = <1>;
163                 #size-cells = <0>;
164
165                 sgtl5000: codec@a {
166                         compatible = "fsl,sgtl5000";
167                         reg = <0x0a>;
168                         clocks = <&clk_26M_snd>;
169                         VDDA-supply = <&vdig_reg>;
170                         VDDIO-supply = <&vvideo_reg>;
171                         #sound-dai-cells = <0>;
172                 };
173         };
174
175         spi_gpio: spi-gpio {
176                 compatible = "spi-gpio";
177                 #address-cells = <1>;
178                 #size-cells = <0>;
179                 pinctrl-names = "default";
180                 pinctrl-0 = <&pinctrl_gpiospi0>;
181                 status = "okay";
182
183                 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
184                 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
185                 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
186                 num-chipselects = <1>;
187                 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
188
189                 eeprom@0 {
190                         compatible = "eeprom-93xx46";
191                         reg = <0>;
192                         spi-max-frequency = <1000000>;
193                         spi-cs-high;
194                         data-size = <8>;
195                 };
196         };
197
198         mdio_gpio: mdio-gpio {
199                 compatible = "virtual,mdio-gpio";
200                 pinctrl-names = "default";
201                 pinctrl-0 = <&pinctrl_swmdio>;
202                 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
203                         <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
204
205                 #address-cells = <1>;
206                 #size-cells = <0>;
207
208                 switch@0 {
209                         compatible = "marvell,mv88e6085";
210                         reg = <0>;
211                         dsa,member = <0 0>;
212
213                         ports {
214                                 #address-cells = <1>;
215                                 #size-cells = <0>;
216
217                                 port@0 {
218                                         reg = <0>;
219                                         label = "cpu";
220                                         ethernet = <&fec>;
221
222                                         fixed-link {
223                                                 speed = <100>;
224                                                 full-duplex;
225                                         };
226                                 };
227
228                                 port@1 {
229                                         reg = <1>;
230                                         label = "netaux";
231                                 };
232
233                                 port@3 {
234                                         reg = <3>;
235                                         label = "netright";
236                                 };
237
238                                 port@4 {
239                                         reg = <4>;
240                                         label = "netleft";
241                                 };
242                         };
243                 };
244         };
245
246         sound {
247                 compatible = "simple-audio-card";
248                 simple-audio-card,name = "Front";
249                 simple-audio-card,format = "i2s";
250                 simple-audio-card,bitclock-master = <&sound_codec>;
251                 simple-audio-card,frame-master = <&sound_codec>;
252                 simple-audio-card,widgets =
253                         "Headphone", "Headphone Jack";
254                 simple-audio-card,routing =
255                         "Headphone Jack", "HPLEFT",
256                         "Headphone Jack", "HPRIGHT";
257                 simple-audio-card,aux-devs = <&hpa1>;
258
259                 sound_cpu: simple-audio-card,cpu {
260                         sound-dai = <&ssi2>;
261                 };
262
263                 sound_codec: simple-audio-card,codec {
264                         sound-dai = <&sgtl5000>;
265                         clocks = <&clk_26M_snd>;
266                 };
267         };
268
269         usbh1phy: usbphy1 {
270                 compatible = "usb-nop-xceiv";
271                 pinctrl-names = "default";
272                 pinctrl-0 = <&pinctrl_usbh1phy>;
273                 clocks = <&clk_26M_usb>;
274                 clock-names = "main_clk";
275                 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
276                 vcc-supply = <&vusb_reg>;
277                 #phy-cells = <0>;
278         };
279
280         usbh2phy: usbphy2 {
281                 compatible = "usb-nop-xceiv";
282                 pinctrl-names = "default";
283                 pinctrl-0 = <&pinctrl_usbh2phy>;
284                 clocks = <&clk_26M_usb>;
285                 clock-names = "main_clk";
286                 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
287                 vcc-supply = <&vusb_reg>;
288                 #phy-cells = <0>;
289         };
290 };
291
292 &audmux {
293         pinctrl-names = "default";
294         pinctrl-0 = <&pinctrl_audmux>;
295         status = "okay";
296
297         ssi2 {
298                 fsl,audmux-port = <1>;
299                 fsl,port-config = <
300                         (IMX_AUDMUX_V2_PTCR_SYN |
301                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
302                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
303                          IMX_AUDMUX_V2_PTCR_TFSDIR |
304                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
305                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
306                 >;
307         };
308
309         aud3 {
310                 fsl,audmux-port = <2>;
311                 fsl,port-config = <
312                         IMX_AUDMUX_V2_PTCR_SYN
313                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
314                 >;
315         };
316 };
317
318 &cpu {
319         cpu-supply = <&sw1_reg>;
320 };
321
322 &ecspi1 {
323         pinctrl-names = "default";
324         pinctrl-0 = <&pinctrl_ecspi1>;
325         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
326                    <&gpio4 25 GPIO_ACTIVE_LOW>;
327         status = "okay";
328
329         pmic@0 {
330                 compatible = "fsl,mc13892";
331                 pinctrl-names = "default";
332                 pinctrl-0 = <&pinctrl_pmic>;
333                 spi-max-frequency = <6000000>;
334                 spi-cs-high;
335                 reg = <0>;
336                 interrupt-parent = <&gpio1>;
337                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
338                 fsl,mc13xxx-uses-adc;
339
340                 regulators {
341                         sw1_reg: sw1 {
342                                 regulator-min-microvolt = <600000>;
343                                 regulator-max-microvolt = <1375000>;
344                                 regulator-boot-on;
345                                 regulator-always-on;
346                         };
347
348                         sw2_reg: sw2 {
349                                 regulator-min-microvolt = <900000>;
350                                 regulator-max-microvolt = <1850000>;
351                                 regulator-boot-on;
352                                 regulator-always-on;
353                         };
354
355                         sw3_reg: sw3 {
356                                 regulator-min-microvolt = <1100000>;
357                                 regulator-max-microvolt = <1850000>;
358                                 regulator-boot-on;
359                                 regulator-always-on;
360                         };
361
362                         sw4_reg: sw4 {
363                                 regulator-min-microvolt = <1100000>;
364                                 regulator-max-microvolt = <1850000>;
365                                 regulator-boot-on;
366                                 regulator-always-on;
367                         };
368
369                         vpll_reg: vpll {
370                                 regulator-min-microvolt = <1050000>;
371                                 regulator-max-microvolt = <1800000>;
372                                 regulator-boot-on;
373                                 regulator-always-on;
374                         };
375
376                         vdig_reg: vdig {
377                                 regulator-min-microvolt = <1650000>;
378                                 regulator-max-microvolt = <1650000>;
379                                 regulator-boot-on;
380                         };
381
382                         vsd_reg: vsd {
383                                 regulator-min-microvolt = <1800000>;
384                                 regulator-max-microvolt = <3150000>;
385                         };
386
387                         vusb_reg: vusb {
388                                 regulator-always-on;
389                         };
390
391                         vusb2_reg: vusb2 {
392                                 regulator-min-microvolt = <2400000>;
393                                 regulator-max-microvolt = <2775000>;
394                                 regulator-boot-on;
395                                 regulator-always-on;
396                         };
397
398                         vvideo_reg: vvideo {
399                                 regulator-min-microvolt = <2775000>;
400                                 regulator-max-microvolt = <2775000>;
401                         };
402
403                         vaudio_reg: vaudio {
404                                 regulator-min-microvolt = <2300000>;
405                                 regulator-max-microvolt = <3000000>;
406                         };
407
408                         vcam_reg: vcam {
409                                 regulator-min-microvolt = <2500000>;
410                                 regulator-max-microvolt = <3000000>;
411                         };
412
413                         vgen1_reg: vgen1 {
414                                 regulator-min-microvolt = <1200000>;
415                                 regulator-max-microvolt = <1200000>;
416                         };
417
418                         vgen2_reg: vgen2 {
419                                 regulator-min-microvolt = <1200000>;
420                                 regulator-max-microvolt = <3150000>;
421                                 regulator-always-on;
422                         };
423
424                         vgen3_reg: vgen3 {
425                                 regulator-min-microvolt = <1800000>;
426                                 regulator-max-microvolt = <2900000>;
427                                 regulator-always-on;
428                         };
429                 };
430
431                 leds {
432                         #address-cells = <1>;
433                         #size-cells = <0>;
434                         led-control = <0x0 0x0 0x3f83f8 0x0>;
435
436                         sysled0@3 {
437                                 reg = <3>;
438                                 label = "system:green:status";
439                                 linux,default-trigger = "default-on";
440                         };
441
442                         sysled1@4 {
443                                 reg = <4>;
444                                 label = "system:green:act";
445                                 linux,default-trigger = "heartbeat";
446                         };
447                 };
448         };
449
450         flash@1 {
451                 #address-cells = <1>;
452                 #size-cells = <1>;
453                 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
454                 spi-max-frequency = <25000000>;
455                 reg = <1>;
456         };
457 };
458
459 &esdhc1 {
460         pinctrl-names = "default";
461         pinctrl-0 = <&pinctrl_esdhc1>;
462         bus-width = <4>;
463         no-1-8-v;
464         non-removable;
465         no-sdio;
466         no-sd;
467         status = "okay";
468 };
469
470 &fec {
471         pinctrl-names = "default";
472         pinctrl-0 = <&pinctrl_fec>;
473         phy-mode = "mii";
474         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
475         phy-supply = <&vgen3_reg>;
476         status = "okay";
477 };
478
479 &gpio1 {
480         unused-sd3-wp-gpio {
481                 /*
482                  * See pinctrl_esdhc1 below for more details on this
483                  */
484                 gpio-hog;
485                 gpios = <1 GPIO_ACTIVE_HIGH>;
486                 output-high;
487         };
488 };
489
490 &i2c2 {
491         pinctrl-names = "default";
492         pinctrl-0 = <&pinctrl_i2c2>;
493         status = "okay";
494
495         eeprom@50 {
496                 compatible = "atmel,24c04";
497                 pagesize = <16>;
498                 reg = <0x50>;
499         };
500
501         hpa1: amp@60 {
502                 compatible = "ti,tpa6130a2";
503                 reg = <0x60>;
504                 pinctrl-names = "default";
505                 pinctrl-0 = <&pinctrl_ampgpio>;
506                 power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
507                 Vdd-supply = <&reg_3p3v>;
508         };
509
510         ds1341: rtc@68 {
511                 compatible = "dallas,ds1341";
512                 reg = <0x68>;
513         };
514
515         /* touch nodes default disabled, bootloader will enable the right one */
516
517         touchscreen@4b {
518                 compatible = "atmel,maxtouch";
519                 reg = <0x4b>;
520                 pinctrl-names = "default";
521                 pinctrl-0 = <&pinctrl_ts>;
522                 interrupt-parent = <&gpio3>;
523                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
524                 status = "disabled";
525         };
526
527         touchscreen@4c {
528                 compatible = "atmel,maxtouch";
529                 reg = <0x4c>;
530                 pinctrl-names = "default";
531                 pinctrl-0 = <&pinctrl_ts>;
532                 interrupt-parent = <&gpio3>;
533                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
534                 status = "disabled";
535         };
536
537         touchscreen@20 {
538                 compatible = "syna,rmi4-i2c";
539                 reg = <0x20>;
540                 pinctrl-names = "default";
541                 pinctrl-0 = <&pinctrl_ts>;
542                 interrupt-parent = <&gpio3>;
543                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
544                 status = "disabled";
545
546                 #address-cells = <1>;
547                 #size-cells = <0>;
548
549                 rmi4-f01@1 {
550                         reg = <0x1>;
551                         syna,nosleep-mode = <2>;
552                 };
553
554                 rmi4-f11@11 {
555                         reg = <0x11>;
556                         touchscreen-inverted-x;
557                         touchscreen-swapped-x-y;
558                         syna,sensor-type = <1>;
559                 };
560         };
561
562 };
563
564 &ipu_di0_disp1 {
565         remote-endpoint = <&display_in>;
566 };
567
568 &pmu {
569         secure-reg-access;
570 };
571
572 &ssi2 {
573         status = "okay";
574 };
575
576 &uart1 {
577         pinctrl-names = "default";
578         pinctrl-0 = <&pinctrl_uart1>;
579         status = "okay";
580 };
581
582 &uart2 {
583         pinctrl-names = "default";
584         pinctrl-0 = <&pinctrl_uart2>;
585         status = "okay";
586 };
587
588 &uart3 {
589         pinctrl-names = "default";
590         pinctrl-0 = <&pinctrl_uart3>;
591         status = "okay";
592
593         rave-sp {
594                 compatible = "zii,rave-sp-rdu1";
595                 current-speed = <38400>;
596                 #address-cells = <1>;
597                 #size-cells = <1>;
598
599                 watchdog {
600                         compatible = "zii,rave-sp-watchdog";
601                 };
602
603                 backlight {
604                         compatible = "zii,rave-sp-backlight";
605                 };
606
607                 pwrbutton {
608                         compatible = "zii,rave-sp-pwrbutton";
609                 };
610
611                 eeprom@a3 {
612                         compatible = "zii,rave-sp-eeprom";
613                         reg = <0xa3 0x2000>;
614                         #address-cells = <1>;
615                         #size-cells = <1>;
616                         zii,eeprom-name = "dds-eeprom";
617                 };
618
619                 eeprom@a4 {
620                         compatible = "zii,rave-sp-eeprom";
621                         reg = <0xa4 0x4000>;
622                         #address-cells = <1>;
623                         #size-cells = <1>;
624                         zii,eeprom-name = "main-eeprom";
625                 };
626
627                 eeprom@ae {
628                         compatible = "zii,rave-sp-eeprom";
629                         reg = <0xae 0x200>;
630                         zii,eeprom-name = "switch-eeprom";
631                         /*
632                          * Not all RDU1s have this functionality, so we
633                          * rely on the bootloader to enable this
634                          */
635                         status = "disabled";
636                 };
637         };
638 };
639
640 &usbh1 {
641         pinctrl-names = "default";
642         pinctrl-0 = <&pinctrl_usbh1>;
643         dr_mode = "host";
644         phy_type = "ulpi";
645         fsl,usbphy = <&usbh1phy>;
646         disable-over-current;
647         maximum-speed = "full-speed";
648         vbus-supply = <&reg_5p0v_main>;
649         status = "okay";
650 };
651
652 &usbh2 {
653         pinctrl-names = "default";
654         pinctrl-0 = <&pinctrl_usbh2>;
655         dr_mode = "host";
656         phy_type = "ulpi";
657         fsl,usbphy = <&usbh2phy>;
658         disable-over-current;
659         vbus-supply = <&reg_5p0v_main>;
660         status = "okay";
661 };
662
663 &usbphy0 {
664         vcc-supply = <&vusb_reg>;
665 };
666
667 &usbotg {
668         dr_mode = "host";
669         disable-over-current;
670         phy_type = "utmi_wide";
671         vbus-supply = <&reg_5p0v_main>;
672         status = "okay";
673 };
674
675 &wdog1 {
676         status = "disabled";
677 };
678
679 &iomuxc {
680         pinctrl_ampgpio: ampgpiogrp {
681                 fsl,pins = <
682                         MX51_PAD_GPIO1_9__GPIO1_9               0x5e
683                 >;
684         };
685
686         pinctrl_audmux: audmuxgrp {
687                 fsl,pins = <
688                         MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0xa5
689                         MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x85
690                         MX51_PAD_AUD3_BB_CK__AUD3_TXC           0xa5
691                         MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x85
692                 >;
693         };
694
695         pinctrl_clk26mhz: clk26mhzgrp {
696                 fsl,pins = <
697                         MX51_PAD_DI1_PIN12__GPIO3_1             0x85
698                 >;
699         };
700
701         pinctrl_ecspi1: ecspi1grp {
702                 fsl,pins = <
703                         MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
704                         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
705                         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
706                         MX51_PAD_CSPI1_SS0__GPIO4_24            0x85
707                         MX51_PAD_CSPI1_SS1__GPIO4_25            0x85
708                 >;
709         };
710
711         pinctrl_esdhc1: esdhc1grp {
712                 fsl,pins = <
713                         MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
714                         MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
715                         MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
716                         MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
717                         MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
718                         MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
719                         /*
720                          * GPIO1_1 is not directly used by eSDHC1 in
721                          * any capacity, but earlier versions of RDU1
722                          * used that pin as WP GPIO for eSDHC3 and
723                          * because of that that pad has an external
724                          * pull-up resistor. This is problematic
725                          * because out of reset the pad is configured
726                          * as ALT0 which serves as SD1_WP, which, when
727                          * pulled high by and external pull-up, will
728                          * inhibit execution of any write request to
729                          * attached eMMC device.
730                          *
731                          * To avoid this problem we configure the pad
732                          * to ALT1/GPIO and avoid driving SD1_WP
733                          * signal high.
734                          */
735                         MX51_PAD_GPIO1_1__GPIO1_1               0x0000
736                 >;
737         };
738
739         pinctrl_fec: fecgrp {
740                 fsl,pins = <
741                         MX51_PAD_EIM_EB2__FEC_MDIO              0x1f5
742                         MX51_PAD_NANDF_D9__FEC_RDATA0           0x2180
743                         MX51_PAD_EIM_EB3__FEC_RDATA1            0x180
744                         MX51_PAD_EIM_CS2__FEC_RDATA2            0x180
745                         MX51_PAD_EIM_CS3__FEC_RDATA3            0x180
746                         MX51_PAD_EIM_CS4__FEC_RX_ER             0x180
747                         MX51_PAD_NANDF_D11__FEC_RX_DV           0x2084
748                         MX51_PAD_EIM_CS5__FEC_CRS               0x180
749                         MX51_PAD_NANDF_RB2__FEC_COL             0x2180
750                         MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x2180
751                         MX51_PAD_NANDF_CS2__FEC_TX_ER           0x2004
752                         MX51_PAD_NANDF_CS3__FEC_MDC             0x2004
753                         MX51_PAD_NANDF_D8__FEC_TDATA0           0x2180
754                         MX51_PAD_NANDF_CS4__FEC_TDATA1          0x2004
755                         MX51_PAD_NANDF_CS5__FEC_TDATA2          0x2004
756                         MX51_PAD_NANDF_CS6__FEC_TDATA3          0x2004
757                         MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x2004
758                         MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x2180
759                         MX51_PAD_EIM_A20__GPIO2_14              0x85
760                 >;
761         };
762
763         pinctrl_gpiospi0: gpiospi0grp {
764                 fsl,pins = <
765                         MX51_PAD_CSI2_D18__GPIO4_11             0x85
766                         MX51_PAD_CSI2_D19__GPIO4_12             0x85
767                         MX51_PAD_CSI2_HSYNC__GPIO4_14           0x85
768                         MX51_PAD_CSI2_PIXCLK__GPIO4_15          0x85
769                 >;
770         };
771
772         pinctrl_i2c2: i2c2grp {
773                 fsl,pins = <
774                         MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
775                         MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
776                 >;
777         };
778
779         pinctrl_ipu_disp1: ipudisp1grp {
780                 fsl,pins = <
781                         MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
782                         MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
783                         MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
784                         MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
785                         MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
786                         MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
787                         MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
788                         MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
789                         MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
790                         MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
791                         MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
792                         MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
793                         MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
794                         MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
795                         MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
796                         MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
797                         MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
798                         MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
799                         MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
800                         MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
801                         MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
802                         MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
803                         MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
804                         MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
805                         MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
806                         MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
807                         MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
808                 >;
809         };
810
811         pinctrl_panel: panelgrp {
812                 fsl,pins = <
813                         MX51_PAD_DI1_D0_CS__GPIO3_3             0x85
814                 >;
815         };
816
817         pinctrl_pmic: pmicgrp {
818                 fsl,pins = <
819                         MX51_PAD_GPIO1_4__GPIO1_4               0x1e0
820                         MX51_PAD_GPIO1_8__GPIO1_8               0x21e2
821                 >;
822         };
823
824         pinctrl_sndgate26mhz: sndgate26mhzgrp {
825                 fsl,pins = <
826                         MX51_PAD_CSPI1_RDY__GPIO4_26            0x85
827                 >;
828         };
829
830         pinctrl_swi2c: swi2cgrp {
831                 fsl,pins = <
832                         MX51_PAD_GPIO1_2__GPIO1_2               0xc5
833                         MX51_PAD_DI1_D1_CS__GPIO3_4             0x400001f5
834                 >;
835         };
836
837         pinctrl_swmdio: swmdiogrp {
838                 fsl,pins = <
839                         MX51_PAD_NANDF_D14__GPIO3_26            0x21e6
840                         MX51_PAD_NANDF_D15__GPIO3_25            0x21e6
841                 >;
842         };
843
844         pinctrl_ts: tsgrp {
845                 fsl,pins = <
846                         MX51_PAD_CSI1_D8__GPIO3_12              0x04
847                         MX51_PAD_CSI1_D9__GPIO3_13              0x85
848                 >;
849         };
850
851         pinctrl_uart1: uart1grp {
852                 fsl,pins = <
853                         MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
854                         MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
855                         MX51_PAD_UART1_RTS__UART1_RTS           0x1c4
856                         MX51_PAD_UART1_CTS__UART1_CTS           0x1c4
857                 >;
858         };
859
860         pinctrl_uart2: uart2grp {
861                 fsl,pins = <
862                         MX51_PAD_UART2_RXD__UART2_RXD           0xc5
863                         MX51_PAD_UART2_TXD__UART2_TXD           0xc5
864                 >;
865         };
866
867         pinctrl_uart3: uart3grp {
868                 fsl,pins = <
869                         MX51_PAD_EIM_D25__UART3_RXD             0x1c5
870                         MX51_PAD_EIM_D26__UART3_TXD             0x1c5
871                 >;
872         };
873
874         pinctrl_usbgate26mhz: usbgate26mhzgrp {
875                 fsl,pins = <
876                         MX51_PAD_DISP2_DAT6__GPIO1_19           0x85
877                 >;
878         };
879
880         pinctrl_usbh1: usbh1grp {
881                 fsl,pins = <
882                         MX51_PAD_USBH1_STP__USBH1_STP           0x0
883                         MX51_PAD_USBH1_CLK__USBH1_CLK           0x0
884                         MX51_PAD_USBH1_DIR__USBH1_DIR           0x0
885                         MX51_PAD_USBH1_NXT__USBH1_NXT           0x0
886                         MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x0
887                         MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x0
888                         MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x0
889                         MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x0
890                         MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x0
891                         MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x0
892                         MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x0
893                         MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x0
894                 >;
895         };
896
897         pinctrl_usbh1phy: usbh1phygrp {
898                 fsl,pins = <
899                         MX51_PAD_NANDF_D0__GPIO4_8              0x85
900                 >;
901         };
902
903         pinctrl_usbh2: usbh2grp {
904                 fsl,pins = <
905                         MX51_PAD_EIM_A26__USBH2_STP             0x0
906                         MX51_PAD_EIM_A24__USBH2_CLK             0x0
907                         MX51_PAD_EIM_A25__USBH2_DIR             0x0
908                         MX51_PAD_EIM_A27__USBH2_NXT             0x0
909                         MX51_PAD_EIM_D16__USBH2_DATA0           0x0
910                         MX51_PAD_EIM_D17__USBH2_DATA1           0x0
911                         MX51_PAD_EIM_D18__USBH2_DATA2           0x0
912                         MX51_PAD_EIM_D19__USBH2_DATA3           0x0
913                         MX51_PAD_EIM_D20__USBH2_DATA4           0x0
914                         MX51_PAD_EIM_D21__USBH2_DATA5           0x0
915                         MX51_PAD_EIM_D22__USBH2_DATA6           0x0
916                         MX51_PAD_EIM_D23__USBH2_DATA7           0x0
917                 >;
918         };
919
920         pinctrl_usbh2phy: usbh2phygrp {
921                 fsl,pins = <
922                         MX51_PAD_NANDF_D1__GPIO4_7              0x85
923                 >;
924         };
925 };