arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi

   1 /*
   2  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx51.dtsi"
  14
  15 / {
  16         model = "Digi ConnectCore CC(W)-MX51";
  17         compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
  18
  19         memory@90000000 {
  20                 device_type = "memory";
  21                 reg = <0x90000000 0x08000000>;
  22         };
  23 };
  24
  25 &ecspi1 {
  26         pinctrl-names = "default";
  27         pinctrl-0 = <&pinctrl_ecspi1>;
  28         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
  29         status = "okay";
  30
  31         pmic: mc13892@0 {
  32                 pinctrl-names = "default";
  33                 pinctrl-0 = <&pinctrl_mc13892>;
  34                 compatible = "fsl,mc13892";
  35                 spi-max-frequency = <16000000>;
  36                 spi-cs-high;
  37                 reg = <0>;
  38                 interrupt-parent = <&gpio1>;
  39                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
  40
  41                 regulators {
  42                         sw1_reg: sw1 {
  43                                 regulator-min-microvolt = <1000000>;
  44                                 regulator-max-microvolt = <1100000>;
  45                                 regulator-boot-on;
  46                                 regulator-always-on;
  47                         };
  48
  49                         sw2_reg: sw2 {
  50                                 regulator-min-microvolt = <1225000>;
  51                                 regulator-max-microvolt = <1225000>;
  52                                 regulator-boot-on;
  53                                 regulator-always-on;
  54                         };
  55
  56                         sw3_reg: sw3 {
  57                                 regulator-min-microvolt = <1200000>;
  58                                 regulator-max-microvolt = <1200000>;
  59                                 regulator-boot-on;
  60                                 regulator-always-on;
  61                         };
  62
  63                         swbst_reg: swbst { };
  64
  65                         viohi_reg: viohi {
  66                                 regulator-always-on;
  67                         };
  68
  69                         vpll_reg: vpll {
  70                                 regulator-min-microvolt = <1800000>;
  71                                 regulator-max-microvolt = <1800000>;
  72                                 regulator-always-on;
  73                         };
  74
  75                         vdig_reg: vdig {
  76                                 regulator-min-microvolt = <1250000>;
  77                                 regulator-max-microvolt = <1250000>;
  78                                 regulator-always-on;
  79                         };
  80
  81                         vsd_reg: vsd {
  82                                 regulator-min-microvolt = <3150000>;
  83                                 regulator-max-microvolt = <3150000>;
  84                                 regulator-always-on;
  85                         };
  86
  87                         vusb2_reg: vusb2 {
  88                                 regulator-min-microvolt = <2600000>;
  89                                 regulator-max-microvolt = <2600000>;
  90                                 regulator-always-on;
  91                         };
  92
  93                         vvideo_reg: vvideo {
  94                                 regulator-min-microvolt = <2775000>;
  95                                 regulator-max-microvolt = <2775000>;
  96                                 regulator-always-on;
  97                         };
  98
  99                         vaudio_reg: vaudio {
 100                                 regulator-min-microvolt = <3000000>;
 101                                 regulator-max-microvolt = <3000000>;
 102                                 regulator-always-on;
 103                         };
 104
 105                         vcam_reg: vcam {
 106                                 regulator-min-microvolt = <2750000>;
 107                                 regulator-max-microvolt = <2750000>;
 108                                 regulator-always-on;
 109                         };
 110
 111                         vgen1_reg: vgen1 {
 112                                 regulator-min-microvolt = <1200000>;
 113                                 regulator-max-microvolt = <1200000>;
 114                                 regulator-always-on;
 115                         };
 116
 117                         vgen2_reg: vgen2 {
 118                                 regulator-min-microvolt = <3150000>;
 119                                 regulator-max-microvolt = <3150000>;
 120                                 regulator-always-on;
 121                         };
 122
 123                         vgen3_reg: vgen3 {
 124                                 regulator-min-microvolt = <1800000>;
 125                                 regulator-max-microvolt = <1800000>;
 126                                 regulator-always-on;
 127                         };
 128
 129                         vusb_reg: vusb {
 130                                 regulator-always-on;
 131                         };
 132
 133                         gpo1_reg: gpo1 { };
 134
 135                         gpo2_reg: gpo2 { };
 136
 137                         gpo3_reg: gpo3 { };
 138
 139                         gpo4_reg: gpo4 { };
 140
 141                         pwgt2spi_reg: pwgt2spi {
 142                                 regulator-always-on;
 143                         };
 144                 };
 145         };
 146 };
 147
 148 &esdhc1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_esdhc1>;
 151         max-frequency = <50000000>;
 152         bus-width = <1>;
 153 };
 154
 155 &esdhc2 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_esdhc2>;
 158         cap-sdio-irq;
 159         wakeup-source;
 160         keep-power-in-suspend;
 161         max-frequency = <50000000>;
 162         no-1-8-v;
 163         non-removable;
 164         vmmc-supply = <&gpo4_reg>;
 165         status = "okay";
 166 };
 167
 168 &fec {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_fec>;
 171         phy-mode = "mii";
 172         phy-supply = <&gpo3_reg>;
 173         /* Pins shared with LCD2, keep status disabled */
 174 };
 175
 176 &i2c2 {
 177         pinctrl-names = "default", "gpio";
 178         pinctrl-0 = <&pinctrl_i2c2>;
 179         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 180         clock-frequency = <400000>;
 181         scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 182         sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 183         status = "okay";
 184
 185         mma7455l@1d {
 186                 pinctrl-names = "default";
 187                 pinctrl-0 = <&pinctrl_mma7455l>;
 188                 compatible = "fsl,mma7455l";
 189                 reg = <0x1d>;
 190                 interrupt-parent = <&gpio1>;
 191                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
 192         };
 193 };
 194
 195 &nfc {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_nfc>;
 198         nand-bus-width = <8>;
 199         nand-ecc-mode = "hw";
 200         nand-on-flash-bbt;
 201         status = "okay";
 202 };
 203
 204 &usbotg {
 205         phy_type = "utmi_wide";
 206         disable-over-current;
 207         /* Device role is not known, keep status disabled */
 208 };
 209
 210 &weim {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_weim>;
 213         status = "okay";
 214
 215         lan9221: lan9221@5,0 {
 216                 pinctrl-names = "default";
 217                 pinctrl-0 = <&pinctrl_lan9221>;
 218                 compatible = "smsc,lan9221", "smsc,lan9115";
 219                 reg = <5 0x00000000 0x1000>;
 220                 fsl,weim-cs-timing = <
 221                         0x00420081 0x00000000
 222                         0x32260000 0x00000000
 223                         0x72080f00 0x00000000
 224                 >;
 225                 clocks = <&clks IMX5_CLK_DUMMY>;
 226                 interrupt-parent = <&gpio1>;
 227                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
 228                 phy-mode = "mii";
 229                 reg-io-width = <2>;
 230                 smsc,irq-push-pull;
 231                 vdd33a-supply = <&gpo2_reg>;
 232                 vddvario-supply = <&gpo2_reg>;
 233         };
 234 };
 235
 236 &iomuxc {
 237         imx51-digi-connectcore-som {
 238                 pinctrl_ecspi1: ecspi1grp {
 239                         fsl,pins = <
 240                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 241                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 242                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 243                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
 244                         >;
 245                 };
 246
 247                 pinctrl_esdhc1: esdhc1grp {
 248                         fsl,pins = <
 249                                 MX51_PAD_SD1_CLK__SD1_CLK               0x400021d5
 250                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 251                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x400020d5
 252                         >;
 253                 };
 254
 255                 pinctrl_esdhc2: esdhc2grp {
 256                         fsl,pins = <
 257                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 258                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 259                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 260                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 261                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 262                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 263                         >;
 264                 };
 265
 266                 pinctrl_fec: fecgrp {
 267                         fsl,pins = <
 268                                 MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
 269                                 MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
 270                                 MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
 271                                 MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
 272                                 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
 273                                 MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
 274                                 MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
 275                                 MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
 276                                 MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
 277                                 MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
 278                                 MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
 279                                 MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
 280                                 MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
 281                                 MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
 282                                 MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
 283                                 MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
 284                                 MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
 285                                 MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
 286                         >;
 287                 };
 288
 289                 pinctrl_i2c2: i2c2grp {
 290                         fsl,pins = <
 291                                 MX51_PAD_GPIO1_2__I2C2_SCL              0x400001ed
 292                                 MX51_PAD_GPIO1_3__I2C2_SDA              0x400001ed
 293                         >;
 294                 };
 295
 296                 pinctrl_i2c2_gpio: i2c2gpiogrp {
 297                         fsl,pins = <
 298                                 MX51_PAD_GPIO1_2__GPIO1_2               0x400001ed
 299                                 MX51_PAD_GPIO1_3__GPIO1_3               0x400001ed
 300                         >;
 301                 };
 302
 303                 pinctrl_nfc: nfcgrp {
 304                         fsl,pins = <
 305                                 MX51_PAD_NANDF_D0__NANDF_D0             0x80000000
 306                                 MX51_PAD_NANDF_D1__NANDF_D1             0x80000000
 307                                 MX51_PAD_NANDF_D2__NANDF_D2             0x80000000
 308                                 MX51_PAD_NANDF_D3__NANDF_D3             0x80000000
 309                                 MX51_PAD_NANDF_D4__NANDF_D4             0x80000000
 310                                 MX51_PAD_NANDF_D5__NANDF_D5             0x80000000
 311                                 MX51_PAD_NANDF_D6__NANDF_D6             0x80000000
 312                                 MX51_PAD_NANDF_D7__NANDF_D7             0x80000000
 313                                 MX51_PAD_NANDF_ALE__NANDF_ALE           0x80000000
 314                                 MX51_PAD_NANDF_CLE__NANDF_CLE           0x80000000
 315                                 MX51_PAD_NANDF_RE_B__NANDF_RE_B         0x80000000
 316                                 MX51_PAD_NANDF_WE_B__NANDF_WE_B         0x80000000
 317                                 MX51_PAD_NANDF_WP_B__NANDF_WP_B         0x80000000
 318                                 MX51_PAD_NANDF_CS0__NANDF_CS0           0x80000000
 319                                 MX51_PAD_NANDF_RB0__NANDF_RB0           0x80000000
 320                         >;
 321                 };
 322
 323                 pinctrl_lan9221: lan9221grp {
 324                         fsl,pins = <
 325                                 MX51_PAD_GPIO1_9__GPIO1_9               0xe5 /* IRQ */
 326                         >;
 327                 };
 328
 329                 pinctrl_mc13892: mc13892grp {
 330                         fsl,pins = <
 331                                 MX51_PAD_GPIO1_5__GPIO1_5               0xe5 /* IRQ */
 332                         >;
 333                 };
 334
 335                 pinctrl_mma7455l: mma7455lgrp {
 336                         fsl,pins = <
 337                                 MX51_PAD_GPIO1_7__GPIO1_7               0xe5 /* IRQ1 */
 338                                 MX51_PAD_GPIO1_6__GPIO1_6               0xe5 /* IRQ2 */
 339                         >;
 340                 };
 341
 342                 pinctrl_weim: weimgrp {
 343                         fsl,pins = <
 344                                 MX51_PAD_EIM_DA0__EIM_DA0               0x80000000
 345                                 MX51_PAD_EIM_DA1__EIM_DA1               0x80000000
 346                                 MX51_PAD_EIM_DA2__EIM_DA2               0x80000000
 347                                 MX51_PAD_EIM_DA3__EIM_DA3               0x80000000
 348                                 MX51_PAD_EIM_DA4__EIM_DA4               0x80000000
 349                                 MX51_PAD_EIM_DA5__EIM_DA5               0x80000000
 350                                 MX51_PAD_EIM_DA6__EIM_DA6               0x80000000
 351                                 MX51_PAD_EIM_DA7__EIM_DA7               0x80000000
 352                                 MX51_PAD_EIM_DA8__EIM_DA8               0x80000000
 353                                 MX51_PAD_EIM_DA9__EIM_DA9               0x80000000
 354                                 MX51_PAD_EIM_DA10__EIM_DA10             0x80000000
 355                                 MX51_PAD_EIM_DA11__EIM_DA11             0x80000000
 356                                 MX51_PAD_EIM_DA12__EIM_DA12             0x80000000
 357                                 MX51_PAD_EIM_DA13__EIM_DA13             0x80000000
 358                                 MX51_PAD_EIM_DA14__EIM_DA14             0x80000000
 359                                 MX51_PAD_EIM_DA15__EIM_DA15             0x80000000
 360                                 MX51_PAD_EIM_A16__EIM_A16               0x80000000
 361                                 MX51_PAD_EIM_A17__EIM_A17               0x80000000
 362                                 MX51_PAD_EIM_A18__EIM_A18               0x80000000
 363                                 MX51_PAD_EIM_A19__EIM_A19               0x80000000
 364                                 MX51_PAD_EIM_A20__EIM_A20               0x80000000
 365                                 MX51_PAD_EIM_A21__EIM_A21               0x80000000
 366                                 MX51_PAD_EIM_A22__EIM_A22               0x80000000
 367                                 MX51_PAD_EIM_A23__EIM_A23               0x80000000
 368                                 MX51_PAD_EIM_A24__EIM_A24               0x80000000
 369                                 MX51_PAD_EIM_A25__EIM_A25               0x80000000
 370                                 MX51_PAD_EIM_A26__EIM_A26               0x80000000
 371                                 MX51_PAD_EIM_A27__EIM_A27               0x80000000
 372                                 MX51_PAD_EIM_D16__EIM_D16               0x80000000
 373                                 MX51_PAD_EIM_D17__EIM_D17               0x80000000
 374                                 MX51_PAD_EIM_D18__EIM_D18               0x80000000
 375                                 MX51_PAD_EIM_D19__EIM_D19               0x80000000
 376                                 MX51_PAD_EIM_D20__EIM_D20               0x80000000
 377                                 MX51_PAD_EIM_D21__EIM_D21               0x80000000
 378                                 MX51_PAD_EIM_D22__EIM_D22               0x80000000
 379                                 MX51_PAD_EIM_D23__EIM_D23               0x80000000
 380                                 MX51_PAD_EIM_D24__EIM_D24               0x80000000
 381                                 MX51_PAD_EIM_D25__EIM_D25               0x80000000
 382                                 MX51_PAD_EIM_D26__EIM_D26               0x80000000
 383                                 MX51_PAD_EIM_D27__EIM_D27               0x80000000
 384                                 MX51_PAD_EIM_D28__EIM_D28               0x80000000
 385                                 MX51_PAD_EIM_D29__EIM_D29               0x80000000
 386                                 MX51_PAD_EIM_D30__EIM_D30               0x80000000
 387                                 MX51_PAD_EIM_D31__EIM_D31               0x80000000
 388                                 MX51_PAD_EIM_OE__EIM_OE                 0x80000000
 389                                 MX51_PAD_EIM_DTACK__EIM_DTACK           0x80000000
 390                                 MX51_PAD_EIM_LBA__EIM_LBA               0x80000000
 391                                 MX51_PAD_EIM_CS5__EIM_CS5               0x80000000 /* CS5 */
 392                         >;
 393                 };
 394         };
 395 };