arch/arm/boot/dts/imx51-apf51.dts

   1 /*
   2  * Copyright 2012 Armadeus Systems - <support@armadeus.com>
   3  * Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
   4  *
   5  * Based on mx51-babbage.dts
   6  * Copyright 2011 Freescale Semiconductor, Inc.
   7  * Copyright 2011 Linaro Ltd.
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 /dts-v1/;
  18 #include "imx51.dtsi"
  19
  20 / {
  21         model = "Armadeus Systems APF51 module";
  22         compatible = "armadeus,imx51-apf51", "fsl,imx51";
  23
  24         memory {
  25                 reg = <0x90000000 0x20000000>;
  26         };
  27
  28         clocks {
  29                 osc {
  30                         clock-frequency = <33554432>;
  31                 };
  32         };
  33 };
  34
  35 &fec {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_fec>;
  38         phy-mode = "mii";
  39         phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  40         phy-reset-duration = <1>;
  41         status = "okay";
  42 };
  43
  44 &iomuxc {
  45         imx51-apf51 {
  46                 pinctrl_fec: fecgrp {
  47                         fsl,pins = <
  48                                 MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
  49                                 MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
  50                                 MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
  51                                 MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
  52                                 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
  53                                 MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
  54                                 MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
  55                                 MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
  56                                 MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
  57                                 MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
  58                                 MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
  59                                 MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
  60                                 MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
  61                                 MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
  62                                 MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
  63                                 MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
  64                                 MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
  65                                 MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
  66                         >;
  67                 };
  68
  69                 pinctrl_uart3: uart3grp {
  70                         fsl,pins = <
  71                                 MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
  72                                 MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
  73                         >;
  74                 };
  75         };
  76 };
  77
  78 &nfc {
  79         nand-bus-width = <8>;
  80         nand-ecc-mode = "hw";
  81         nand-on-flash-bbt;
  82         status = "okay";
  83 };
  84
  85 &uart3 {
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_uart3>;
  88         status = "okay";
  89 };