arch/arm/boot/dts/imx50.dtsi

   1 /*
   2  * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "imx50-pinfunc.h"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/clock/imx5-clock.h>
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         /*
  22          * The decompressor and also some bootloaders rely on a
  23          * pre-existing /chosen node to be available to insert the
  24          * command line and merge other ATAGS info.
  25          * Also for U-Boot there must be a pre-existing /memory node.
  26          */
  27         chosen {};
  28         memory { device_type = "memory"; };
  29
  30         aliases {
  31                 ethernet0 = &fec;
  32                 gpio0 = &gpio1;
  33                 gpio1 = &gpio2;
  34                 gpio2 = &gpio3;
  35                 gpio3 = &gpio4;
  36                 gpio4 = &gpio5;
  37                 gpio5 = &gpio6;
  38                 serial0 = &uart1;
  39                 serial1 = &uart2;
  40                 serial2 = &uart3;
  41                 serial3 = &uart4;
  42                 serial4 = &uart5;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a8";
  51                         reg = <0x0>;
  52                 };
  53         };
  54
  55         tzic: tz-interrupt-controller@fffc000 {
  56                 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <1>;
  59                 reg = <0x0fffc000 0x4000>;
  60         };
  61
  62         clocks {
  63                 ckil {
  64                         compatible = "fsl,imx-ckil", "fixed-clock";
  65                         #clock-cells = <0>;
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 ckih1 {
  70                         compatible = "fsl,imx-ckih1", "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <22579200>;
  73                 };
  74
  75                 ckih2 {
  76                         compatible = "fsl,imx-ckih2", "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <0>;
  79                 };
  80
  81                 osc {
  82                         compatible = "fsl,imx-osc", "fixed-clock";
  83                         #clock-cells = <0>;
  84                         clock-frequency = <24000000>;
  85                 };
  86         };
  87
  88         soc {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 compatible = "simple-bus";
  92                 interrupt-parent = <&tzic>;
  93                 ranges;
  94
  95                 aips@50000000 { /* AIPS1 */
  96                         compatible = "fsl,aips-bus", "simple-bus";
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         reg = <0x50000000 0x10000000>;
 100                         ranges;
 101
 102                         spba@50000000 {
 103                                 compatible = "fsl,spba-bus", "simple-bus";
 104                                 #address-cells = <1>;
 105                                 #size-cells = <1>;
 106                                 reg = <0x50000000 0x40000>;
 107                                 ranges;
 108
 109                                 esdhc1: esdhc@50004000 {
 110                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 111                                         reg = <0x50004000 0x4000>;
 112                                         interrupts = <1>;
 113                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 114                                                  <&clks IMX5_CLK_DUMMY>,
 115                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 116                                         clock-names = "ipg", "ahb", "per";
 117                                         bus-width = <4>;
 118                                         status = "disabled";
 119                                 };
 120
 121                                 esdhc2: esdhc@50008000 {
 122                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 123                                         reg = <0x50008000 0x4000>;
 124                                         interrupts = <2>;
 125                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 126                                                  <&clks IMX5_CLK_DUMMY>,
 127                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 128                                         clock-names = "ipg", "ahb", "per";
 129                                         bus-width = <4>;
 130                                         status = "disabled";
 131                                 };
 132
 133                                 uart3: serial@5000c000 {
 134                                         compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 135                                         reg = <0x5000c000 0x4000>;
 136                                         interrupts = <33>;
 137                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 138                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 139                                         clock-names = "ipg", "per";
 140                                         status = "disabled";
 141                                 };
 142
 143                                 ecspi1: ecspi@50010000 {
 144                                         #address-cells = <1>;
 145                                         #size-cells = <0>;
 146                                         compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 147                                         reg = <0x50010000 0x4000>;
 148                                         interrupts = <36>;
 149                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 150                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 151                                         clock-names = "ipg", "per";
 152                                         status = "disabled";
 153                                 };
 154
 155                                 ssi2: ssi@50014000 {
 156                                         #sound-dai-cells = <0>;
 157                                         compatible = "fsl,imx50-ssi",
 158                                                         "fsl,imx51-ssi",
 159                                                         "fsl,imx21-ssi";
 160                                         reg = <0x50014000 0x4000>;
 161                                         interrupts = <30>;
 162                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 163                                         dmas = <&sdma 24 1 0>,
 164                                                <&sdma 25 1 0>;
 165                                         dma-names = "rx", "tx";
 166                                         fsl,fifo-depth = <15>;
 167                                         status = "disabled";
 168                                 };
 169
 170                                 esdhc3: esdhc@50020000 {
 171                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 172                                         reg = <0x50020000 0x4000>;
 173                                         interrupts = <3>;
 174                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 175                                                  <&clks IMX5_CLK_DUMMY>,
 176                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 177                                         clock-names = "ipg", "ahb", "per";
 178                                         bus-width = <4>;
 179                                         status = "disabled";
 180                                 };
 181
 182                                 esdhc4: esdhc@50024000 {
 183                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 184                                         reg = <0x50024000 0x4000>;
 185                                         interrupts = <4>;
 186                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 187                                                  <&clks IMX5_CLK_DUMMY>,
 188                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 189                                         clock-names = "ipg", "ahb", "per";
 190                                         bus-width = <4>;
 191                                         status = "disabled";
 192                                 };
 193                         };
 194
 195                         usbotg: usb@53f80000 {
 196                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 197                                 reg = <0x53f80000 0x0200>;
 198                                 interrupts = <18>;
 199                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 200                                 status = "disabled";
 201                         };
 202
 203                         usbh1: usb@53f80200 {
 204                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 205                                 reg = <0x53f80200 0x0200>;
 206                                 interrupts = <14>;
 207                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 208                                 dr_mode = "host";
 209                                 status = "disabled";
 210                         };
 211
 212                         usbh2: usb@53f80400 {
 213                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 214                                 reg = <0x53f80400 0x0200>;
 215                                 interrupts = <16>;
 216                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 217                                 dr_mode = "host";
 218                                 status = "disabled";
 219                         };
 220
 221                         usbh3: usb@53f80600 {
 222                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 223                                 reg = <0x53f80600 0x0200>;
 224                                 interrupts = <17>;
 225                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 226                                 dr_mode = "host";
 227                                 status = "disabled";
 228                         };
 229
 230                         gpio1: gpio@53f84000 {
 231                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 232                                 reg = <0x53f84000 0x4000>;
 233                                 interrupts = <50 51>;
 234                                 gpio-controller;
 235                                 #gpio-cells = <2>;
 236                                 interrupt-controller;
 237                                 #interrupt-cells = <2>;
 238                                 gpio-ranges = <&iomuxc 0 151 28>;
 239                         };
 240
 241                         gpio2: gpio@53f88000 {
 242                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 243                                 reg = <0x53f88000 0x4000>;
 244                                 interrupts = <52 53>;
 245                                 gpio-controller;
 246                                 #gpio-cells = <2>;
 247                                 interrupt-controller;
 248                                 #interrupt-cells = <2>;
 249                                 gpio-ranges = <&iomuxc  0 75 8>, <&iomuxc 8 100 8>,
 250                                               <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
 251                                               <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
 252                                               <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
 253                         };
 254
 255                         gpio3: gpio@53f8c000 {
 256                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 257                                 reg = <0x53f8c000 0x4000>;
 258                                 interrupts = <54 55>;
 259                                 gpio-controller;
 260                                 #gpio-cells = <2>;
 261                                 interrupt-controller;
 262                                 #interrupt-cells = <2>;
 263                                 gpio-ranges = <&iomuxc 0 108 32>;
 264                         };
 265
 266                         gpio4: gpio@53f90000 {
 267                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 268                                 reg = <0x53f90000 0x4000>;
 269                                 interrupts = <56 57>;
 270                                 gpio-controller;
 271                                 #gpio-cells = <2>;
 272                                 interrupt-controller;
 273                                 #interrupt-cells = <2>;
 274                                 gpio-ranges = <&iomuxc  0   8  8>, <&iomuxc 8 45 12>,
 275                                               <&iomuxc 20 140 11>;
 276                         };
 277
 278                         wdog1: wdog@53f98000 {
 279                                 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
 280                                 reg = <0x53f98000 0x4000>;
 281                                 interrupts = <58>;
 282                                 clocks = <&clks IMX5_CLK_DUMMY>;
 283                         };
 284
 285                         gpt: timer@53fa0000 {
 286                                 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
 287                                 reg = <0x53fa0000 0x4000>;
 288                                 interrupts = <39>;
 289                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 290                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 291                                 clock-names = "ipg", "per";
 292                         };
 293
 294                         iomuxc: iomuxc@53fa8000 {
 295                                 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
 296                                 reg = <0x53fa8000 0x4000>;
 297                         };
 298
 299                         gpr: iomuxc-gpr@53fa8000 {
 300                                 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
 301                                 reg = <0x53fa8000 0xc>;
 302                         };
 303
 304                         pwm1: pwm@53fb4000 {
 305                                 #pwm-cells = <2>;
 306                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 307                                 reg = <0x53fb4000 0x4000>;
 308                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 309                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 310                                 clock-names = "ipg", "per";
 311                                 interrupts = <61>;
 312                         };
 313
 314                         pwm2: pwm@53fb8000 {
 315                                 #pwm-cells = <2>;
 316                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 317                                 reg = <0x53fb8000 0x4000>;
 318                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 319                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 320                                 clock-names = "ipg", "per";
 321                                 interrupts = <94>;
 322                         };
 323
 324                         uart1: serial@53fbc000 {
 325                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 326                                 reg = <0x53fbc000 0x4000>;
 327                                 interrupts = <31>;
 328                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 329                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 330                                 clock-names = "ipg", "per";
 331                                 status = "disabled";
 332                         };
 333
 334                         uart2: serial@53fc0000 {
 335                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 336                                 reg = <0x53fc0000 0x4000>;
 337                                 interrupts = <32>;
 338                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 339                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 340                                 clock-names = "ipg", "per";
 341                                 status = "disabled";
 342                         };
 343
 344                         src: src@53fd0000 {
 345                                 compatible = "fsl,imx50-src", "fsl,imx51-src";
 346                                 reg = <0x53fd0000 0x4000>;
 347                                 #reset-cells = <1>;
 348                         };
 349
 350                         clks: ccm@53fd4000{
 351                                 compatible = "fsl,imx50-ccm";
 352                                 reg = <0x53fd4000 0x4000>;
 353                                 interrupts = <0 71 0x04 0 72 0x04>;
 354                                 #clock-cells = <1>;
 355                         };
 356
 357                         gpio5: gpio@53fdc000 {
 358                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 359                                 reg = <0x53fdc000 0x4000>;
 360                                 interrupts = <103 104>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                                 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
 366                         };
 367
 368                         gpio6: gpio@53fe0000 {
 369                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 370                                 reg = <0x53fe0000 0x4000>;
 371                                 interrupts = <105 106>;
 372                                 gpio-controller;
 373                                 #gpio-cells = <2>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <2>;
 376                                 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
 377                         };
 378
 379                         i2c3: i2c@53fec000 {
 380                                 #address-cells = <1>;
 381                                 #size-cells = <0>;
 382                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 383                                 reg = <0x53fec000 0x4000>;
 384                                 interrupts = <64>;
 385                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 386                                 status = "disabled";
 387                         };
 388
 389                         uart4: serial@53ff0000 {
 390                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 391                                 reg = <0x53ff0000 0x4000>;
 392                                 interrupts = <13>;
 393                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 394                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 395                                 clock-names = "ipg", "per";
 396                                 status = "disabled";
 397                         };
 398                 };
 399
 400                 aips@60000000 { /* AIPS2 */
 401                         compatible = "fsl,aips-bus", "simple-bus";
 402                         #address-cells = <1>;
 403                         #size-cells = <1>;
 404                         reg = <0x60000000 0x10000000>;
 405                         ranges;
 406
 407                         uart5: serial@63f90000 {
 408                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 409                                 reg = <0x63f90000 0x4000>;
 410                                 interrupts = <86>;
 411                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 412                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 413                                 clock-names = "ipg", "per";
 414                                 status = "disabled";
 415                         };
 416
 417                         owire: owire@63fa4000 {
 418                                 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
 419                                 reg = <0x63fa4000 0x4000>;
 420                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 421                                 status = "disabled";
 422                         };
 423
 424                         ecspi2: ecspi@63fac000 {
 425                                 #address-cells = <1>;
 426                                 #size-cells = <0>;
 427                                 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 428                                 reg = <0x63fac000 0x4000>;
 429                                 interrupts = <37>;
 430                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 431                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 432                                 clock-names = "ipg", "per";
 433                                 status = "disabled";
 434                         };
 435
 436                         sdma: sdma@63fb0000 {
 437                                 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
 438                                 reg = <0x63fb0000 0x4000>;
 439                                 interrupts = <6>;
 440                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 441                                          <&clks IMX5_CLK_SDMA_GATE>;
 442                                 clock-names = "ipg", "ahb";
 443                                 #dma-cells = <3>;
 444                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
 445                         };
 446
 447                         cspi: cspi@63fc0000 {
 448                                 #address-cells = <1>;
 449                                 #size-cells = <0>;
 450                                 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
 451                                 reg = <0x63fc0000 0x4000>;
 452                                 interrupts = <38>;
 453                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 454                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 455                                 clock-names = "ipg", "per";
 456                                 status = "disabled";
 457                         };
 458
 459                         i2c2: i2c@63fc4000 {
 460                                 #address-cells = <1>;
 461                                 #size-cells = <0>;
 462                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 463                                 reg = <0x63fc4000 0x4000>;
 464                                 interrupts = <63>;
 465                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 466                                 status = "disabled";
 467                         };
 468
 469                         i2c1: i2c@63fc8000 {
 470                                 #address-cells = <1>;
 471                                 #size-cells = <0>;
 472                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 473                                 reg = <0x63fc8000 0x4000>;
 474                                 interrupts = <62>;
 475                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 476                                 status = "disabled";
 477                         };
 478
 479                         ssi1: ssi@63fcc000 {
 480                                 #sound-dai-cells = <0>;
 481                                 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
 482                                                         "fsl,imx21-ssi";
 483                                 reg = <0x63fcc000 0x4000>;
 484                                 interrupts = <29>;
 485                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 486                                 dmas = <&sdma 28 0 0>,
 487                                        <&sdma 29 0 0>;
 488                                 dma-names = "rx", "tx";
 489                                 fsl,fifo-depth = <15>;
 490                                 status = "disabled";
 491                         };
 492
 493                         audmux: audmux@63fd0000 {
 494                                 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
 495                                 reg = <0x63fd0000 0x4000>;
 496                                 status = "disabled";
 497                         };
 498
 499                         fec: ethernet@63fec000 {
 500                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 501                                 reg = <0x63fec000 0x4000>;
 502                                 interrupts = <87>;
 503                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 504                                          <&clks IMX5_CLK_FEC_GATE>,
 505                                          <&clks IMX5_CLK_FEC_GATE>;
 506                                 clock-names = "ipg", "ahb", "ptp";
 507                                 status = "disabled";
 508                         };
 509                 };
 510         };
 511 };