arch/arm/boot/dts/imx25-pdk.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include <dt-bindings/input/input.h>
  14 #include "imx25.dtsi"
  15
  16 / {
  17         model = "Freescale i.MX25 Product Development Kit";
  18         compatible = "fsl,imx25-pdk", "fsl,imx25";
  19
  20         memory {
  21                 reg = <0x80000000 0x4000000>;
  22         };
  23
  24         regulators {
  25                 compatible = "simple-bus";
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 reg_fec_3v3: regulator@0 {
  30                         compatible = "regulator-fixed";
  31                         reg = <0>;
  32                         regulator-name = "fec-3v3";
  33                         regulator-min-microvolt = <3300000>;
  34                         regulator-max-microvolt = <3300000>;
  35                         gpio = <&gpio2 3 0>;
  36                         enable-active-high;
  37                 };
  38
  39                 reg_2p5v: regulator@1 {
  40                         compatible = "regulator-fixed";
  41                         reg = <1>;
  42                         regulator-name = "2P5V";
  43                         regulator-min-microvolt = <2500000>;
  44                         regulator-max-microvolt = <2500000>;
  45                 };
  46
  47                 reg_3p3v: regulator@2 {
  48                         compatible = "regulator-fixed";
  49                         reg = <2>;
  50                         regulator-name = "3P3V";
  51                         regulator-min-microvolt = <3300000>;
  52                         regulator-max-microvolt = <3300000>;
  53                 };
  54
  55                 reg_can_3v3: regulator@3 {
  56                         compatible = "regulator-fixed";
  57                         reg = <3>;
  58                         regulator-name = "can-3v3";
  59                         regulator-min-microvolt = <3300000>;
  60                         regulator-max-microvolt = <3300000>;
  61                         gpio = <&gpio4 6 0>;
  62                 };
  63         };
  64
  65         sound {
  66                 compatible = "fsl,imx25-pdk-sgtl5000",
  67                              "fsl,imx-audio-sgtl5000";
  68                 model = "imx25-pdk-sgtl5000";
  69                 ssi-controller = <&ssi1>;
  70                 audio-codec = <&codec>;
  71                 audio-routing =
  72                         "MIC_IN", "Mic Jack",
  73                         "Mic Jack", "Mic Bias",
  74                         "Headphone Jack", "HP_OUT";
  75                 mux-int-port = <1>;
  76                 mux-ext-port = <4>;
  77         };
  78
  79         wvga: display {
  80                 model = "CLAA057VC01CW";
  81                 bits-per-pixel = <16>;
  82                 fsl,pcr = <0xfa208b80>;
  83                 bus-width = <18>;
  84                 native-mode = <&wvga_timings>;
  85                 display-timings {
  86                         wvga_timings: 640x480 {
  87                                 hactive = <640>;
  88                                 vactive = <480>;
  89                                 hback-porch = <45>;
  90                                 hfront-porch = <114>;
  91                                 hsync-len = <1>;
  92                                 vback-porch = <33>;
  93                                 vfront-porch = <11>;
  94                                 vsync-len = <1>;
  95                                 clock-frequency = <25200000>;
  96                         };
  97                 };
  98         };
  99 };
 100
 101 &audmux {
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_audmux>;
 104         status = "okay";
 105 };
 106
 107 &can1 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_can1>;
 110         xceiver-supply = <&reg_can_3v3>;
 111         status = "okay";
 112 };
 113
 114 &esdhc1 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_esdhc1>;
 117         cd-gpios = <&gpio2 1 0>;
 118         wp-gpios = <&gpio2 0 0>;
 119         status = "okay";
 120 };
 121
 122 &fec {
 123         phy-mode = "rmii";
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_fec>;
 126         phy-supply = <&reg_fec_3v3>;
 127         phy-reset-gpios = <&gpio4 8 0>;
 128         status = "okay";
 129 };
 130
 131 &i2c1 {
 132         clock-frequency = <100000>;
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_i2c1>;
 135         status = "okay";
 136
 137         codec: sgtl5000@0a {
 138                 compatible = "fsl,sgtl5000";
 139                 reg = <0x0a>;
 140                 clocks = <&clks 129>;
 141                 VDDA-supply = <&reg_2p5v>;
 142                 VDDIO-supply = <&reg_3p3v>;
 143         };
 144 };
 145
 146 &iomuxc {
 147         imx25-pdk {
 148                 pinctrl_audmux: audmuxgrp {
 149                         fsl,pins = <
 150                                 MX25_PAD_RW__AUD4_TXFS                  0xe0
 151                                 MX25_PAD_OE__AUD4_TXC                   0xe0
 152                                 MX25_PAD_EB0__AUD4_TXD                  0xe0
 153                                 MX25_PAD_EB1__AUD4_RXD                  0xe0
 154                         >;
 155                 };
 156
 157                 pinctrl_can1: can1grp {
 158                         fsl,pins = <
 159                                 MX25_PAD_GPIO_A__CAN1_TX                0x0
 160                                 MX25_PAD_GPIO_B__CAN1_RX                0x0
 161                                 MX25_PAD_D14__GPIO_4_6                  0x80000000
 162                         >;
 163                 };
 164
 165                 pinctrl_esdhc1: esdhc1grp {
 166                         fsl,pins = <
 167                                 MX25_PAD_SD1_CMD__SD1_CMD               0x80000000
 168                                 MX25_PAD_SD1_CLK__SD1_CLK               0x80000000
 169                                 MX25_PAD_SD1_DATA0__SD1_DATA0           0x80000000
 170                                 MX25_PAD_SD1_DATA1__SD1_DATA1           0x80000000
 171                                 MX25_PAD_SD1_DATA2__SD1_DATA2           0x80000000
 172                                 MX25_PAD_SD1_DATA3__SD1_DATA3           0x80000000
 173                                 MX25_PAD_A14__GPIO_2_0                  0x80000000
 174                                 MX25_PAD_A15__GPIO_2_1                  0x80000000
 175                         >;
 176                 };
 177
 178                 pinctrl_fec: fecgrp {
 179                         fsl,pins = <
 180                                 MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
 181                                 MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
 182                                 MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
 183                                 MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
 184                                 MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 185                                 MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
 186                                 MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
 187                                 MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
 188                                 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
 189                                 MX25_PAD_A17__GPIO_2_3                  0x80000000
 190                                 MX25_PAD_D12__GPIO_4_8                  0x80000000
 191                         >;
 192                 };
 193
 194                 pinctrl_i2c1: i2c1grp {
 195                         fsl,pins = <
 196                                 MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
 197                                 MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
 198                         >;
 199                 };
 200
 201                 pinctrl_kpp: kppgrp {
 202                         fsl,pins = <
 203                                 MX25_PAD_KPP_ROW0__KPP_ROW0     0x80000000
 204                                 MX25_PAD_KPP_ROW1__KPP_ROW1     0x80000000
 205                                 MX25_PAD_KPP_ROW2__KPP_ROW2     0x80000000
 206                                 MX25_PAD_KPP_ROW3__KPP_ROW3     0x80000000
 207                                 MX25_PAD_KPP_COL0__KPP_COL0     0x80000000
 208                                 MX25_PAD_KPP_COL1__KPP_COL1     0x80000000
 209                                 MX25_PAD_KPP_COL2__KPP_COL2     0x80000000
 210                                 MX25_PAD_KPP_COL3__KPP_COL3     0x80000000
 211                         >;
 212                 };
 213
 214                 pinctrl_lcd: lcdgrp {
 215                         fsl,pins = <
 216                                 MX25_PAD_LD0__LD0               0xe0
 217                                 MX25_PAD_LD1__LD1               0xe0
 218                                 MX25_PAD_LD2__LD2               0xe0
 219                                 MX25_PAD_LD3__LD3               0xe0
 220                                 MX25_PAD_LD4__LD4               0xe0
 221                                 MX25_PAD_LD5__LD5               0xe0
 222                                 MX25_PAD_LD6__LD6               0xe0
 223                                 MX25_PAD_LD7__LD7               0xe0
 224                                 MX25_PAD_LD8__LD8               0xe0
 225                                 MX25_PAD_LD9__LD9               0xe0
 226                                 MX25_PAD_LD10__LD10             0xe0
 227                                 MX25_PAD_LD11__LD11             0xe0
 228                                 MX25_PAD_LD12__LD12             0xe0
 229                                 MX25_PAD_LD13__LD13             0xe0
 230                                 MX25_PAD_LD14__LD14             0xe0
 231                                 MX25_PAD_LD15__LD15             0xe0
 232                                 MX25_PAD_GPIO_E__LD16           0xe0
 233                                 MX25_PAD_GPIO_F__LD17           0xe0
 234                                 MX25_PAD_HSYNC__HSYNC           0xe0
 235                                 MX25_PAD_VSYNC__VSYNC           0xe0
 236                                 MX25_PAD_LSCLK__LSCLK           0xe0
 237                                 MX25_PAD_OE_ACD__OE_ACD         0xe0
 238                                 MX25_PAD_CONTRAST__CONTRAST     0xe0
 239                         >;
 240                 };
 241
 242                 pinctrl_uart1: uart1grp {
 243                         fsl,pins = <
 244                                 MX25_PAD_UART1_RTS__UART1_RTS           0xe0
 245                                 MX25_PAD_UART1_CTS__UART1_CTS           0xe0
 246                                 MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
 247                                 MX25_PAD_UART1_RXD__UART1_RXD           0xc0
 248                         >;
 249                 };
 250         };
 251 };
 252
 253 &lcdc {
 254         display = <&wvga>;
 255         fsl,lpccr = <0x00a903ff>;
 256         fsl,lscr1 = <0x00120300>;
 257         fsl,dmacr = <0x00020010>;
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_lcd>;
 260         status = "okay";
 261 };
 262
 263 &nfc {
 264         nand-on-flash-bbt;
 265         status = "okay";
 266 };
 267
 268 &kpp {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&pinctrl_kpp>;
 271         linux,keymap = <
 272                         MATRIX_KEY(0x0, 0x0, KEY_UP)
 273                         MATRIX_KEY(0x0, 0x1, KEY_DOWN)
 274                         MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
 275                         MATRIX_KEY(0x0, 0x3, KEY_HOME)
 276                         MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
 277                         MATRIX_KEY(0x1, 0x1, KEY_LEFT)
 278                         MATRIX_KEY(0x1, 0x2, KEY_ENTER)
 279                         MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
 280                         MATRIX_KEY(0x2, 0x0, KEY_F6)
 281                         MATRIX_KEY(0x2, 0x1, KEY_F8)
 282                         MATRIX_KEY(0x2, 0x2, KEY_F9)
 283                         MATRIX_KEY(0x2, 0x3, KEY_F10)
 284                         MATRIX_KEY(0x3, 0x0, KEY_F1)
 285                         MATRIX_KEY(0x3, 0x1, KEY_F2)
 286                         MATRIX_KEY(0x3, 0x2, KEY_F3)
 287                         MATRIX_KEY(0x3, 0x2, KEY_POWER)
 288         >;
 289         status = "okay";
 290 };
 291
 292 &ssi1 {
 293         codec-handle = <&codec>;
 294         status = "okay";
 295 };
 296
 297 &uart1 {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_uart1>;
 300         fsl,uart-has-rtscts;
 301         status = "okay";
 302 };
 303
 304 &usbhost1 {
 305         phy_type = "serial";
 306         dr_mode = "host";
 307         status = "okay";
 308 };
 309
 310 &usbotg {
 311         phy_type = "utmi";
 312         dr_mode = "otg";
 313         external-vbus-divider;
 314         status = "okay";
 315 };