arch/arm/boot/dts/imx1-apf9328.dts

   1 /*
   2  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx1.dtsi"
  14
  15 / {
  16         model = "Armadeus APF9328";
  17         compatible = "armadeus,imx1-apf9328", "fsl,imx1";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory@8000000 {
  24                 device_type = "memory";
  25                 reg = <0x08000000 0x00800000>;
  26         };
  27 };
  28
  29 &i2c {
  30         pinctrl-names = "default";
  31         pinctrl-0 = <&pinctrl_i2c>;
  32         status = "okay";
  33 };
  34
  35 &uart1 {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_uart1>;
  38         uart-has-rtscts;
  39         status = "okay";
  40 };
  41
  42 &uart2 {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_uart2>;
  45         uart-has-rtscts;
  46         status = "okay";
  47 };
  48
  49 &weim {
  50         pinctrl-names = "default";
  51         pinctrl-0 = <&pinctrl_weim>;
  52         status = "okay";
  53
  54         nor: nor@0,0 {
  55                 compatible = "cfi-flash";
  56                 reg = <0 0x00000000 0x02000000>;
  57                 bank-width = <2>;
  58                 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61         };
  62
  63         eth: eth@4,c00000 {
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_eth>;
  66                 compatible = "davicom,dm9000";
  67                 reg = <
  68                         4 0x00c00000 0x2
  69                         4 0x00c00002 0x2
  70                 >;
  71                 interrupt-parent = <&gpio2>;
  72                 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
  73                 fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
  74         };
  75 };
  76
  77 &iomuxc {
  78         imx1-apf9328 {
  79                 pinctrl_eth: ethgrp {
  80                         fsl,pins = <
  81                                 MX1_PAD_SIM_SVEN__GPIO2_14      0x0
  82                         >;
  83                 };
  84
  85                 pinctrl_i2c: i2cgrp {
  86                         fsl,pins = <
  87                                 MX1_PAD_I2C_SCL__I2C_SCL        0x0
  88                                 MX1_PAD_I2C_SDA__I2C_SDA        0x0
  89                         >;
  90                 };
  91
  92                 pinctrl_uart1: uart1grp {
  93                         fsl,pins = <
  94                                 MX1_PAD_UART1_TXD__UART1_TXD    0x0
  95                                 MX1_PAD_UART1_RXD__UART1_RXD    0x0
  96                                 MX1_PAD_UART1_CTS__UART1_CTS    0x0
  97                                 MX1_PAD_UART1_RTS__UART1_RTS    0x0
  98                         >;
  99                 };
 100
 101                 pinctrl_uart2: uart2grp {
 102                         fsl,pins = <
 103                                 MX1_PAD_UART2_TXD__UART2_TXD    0x0
 104                                 MX1_PAD_UART2_RXD__UART2_RXD    0x0
 105                                 MX1_PAD_UART2_CTS__UART2_CTS    0x0
 106                                 MX1_PAD_UART2_RTS__UART2_RTS    0x0
 107                         >;
 108                 };
 109
 110                 pinctrl_weim: weimgrp {
 111                         fsl,pins = <
 112                                 MX1_PAD_A0__A0                  0x0
 113                                 MX1_PAD_A16__A16                0x0
 114                                 MX1_PAD_A17__A17                0x0
 115                                 MX1_PAD_A18__A18                0x0
 116                                 MX1_PAD_A19__A19                0x0
 117                                 MX1_PAD_A20__A20                0x0
 118                                 MX1_PAD_A21__A21                0x0
 119                                 MX1_PAD_A22__A22                0x0
 120                                 MX1_PAD_A23__A23                0x0
 121                                 MX1_PAD_A24__A24                0x0
 122                                 MX1_PAD_BCLK__BCLK              0x0
 123                                 MX1_PAD_CS4__CS4                0x0
 124                                 MX1_PAD_DTACK__DTACK            0x0
 125                                 MX1_PAD_ECB__ECB                0x0
 126                                 MX1_PAD_LBA__LBA                0x0
 127                         >;
 128                 };
 129         };
 130 };