arch/arm/boot/dts/imx1-ads.dts

   1 /*
   2  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx1.dtsi"
  14
  15 / {
  16         model = "Freescale MX1 ADS";
  17         compatible = "fsl,imx1ads", "fsl,imx1";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory@8000000 {
  24                 device_type = "memory";
  25                 reg = <0x08000000 0x04000000>;
  26         };
  27 };
  28
  29 &cspi1 {
  30         pinctrl-0 = <&pinctrl_cspi1>;
  31         cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
  32         status = "okay";
  33 };
  34
  35 &i2c {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_i2c>;
  38         status = "okay";
  39
  40         extgpio0: pcf8575@22 {
  41                 compatible = "nxp,pcf8575";
  42                 reg = <0x22>;
  43                 gpio-controller;
  44                 #gpio-cells = <2>;
  45         };
  46
  47         extgpio1: pcf8575@24 {
  48                 compatible = "nxp,pcf8575";
  49                 reg = <0x24>;
  50                 gpio-controller;
  51                 #gpio-cells = <2>;
  52         };
  53 };
  54
  55 &uart1 {
  56         pinctrl-names = "default";
  57         pinctrl-0 = <&pinctrl_uart1>;
  58         uart-has-rtscts;
  59         status = "okay";
  60 };
  61
  62 &uart2 {
  63         pinctrl-names = "default";
  64         pinctrl-0 = <&pinctrl_uart2>;
  65         uart-has-rtscts;
  66         status = "okay";
  67 };
  68
  69 &weim {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&pinctrl_weim>;
  72         status = "okay";
  73
  74         nor: nor@0,0 {
  75                 compatible = "cfi-flash";
  76                 reg = <0 0x00000000 0x02000000>;
  77                 bank-width = <4>;
  78                 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81         };
  82 };
  83
  84 &iomuxc {
  85         imx1-ads {
  86                 pinctrl_cspi1: cspi1grp {
  87                         fsl,pins = <
  88                                 MX1_PAD_SPI1_MISO__SPI1_MISO    0x0
  89                                 MX1_PAD_SPI1_MOSI__SPI1_MOSI    0x0
  90                                 MX1_PAD_SPI1_RDY__SPI1_RDY      0x0
  91                                 MX1_PAD_SPI1_SCLK__SPI1_SCLK    0x0
  92                                 MX1_PAD_SPI1_SS__GPIO3_15       0x0
  93                         >;
  94                 };
  95
  96                 pinctrl_i2c: i2cgrp {
  97                         fsl,pins = <
  98                                 MX1_PAD_I2C_SCL__I2C_SCL        0x0
  99                                 MX1_PAD_I2C_SDA__I2C_SDA        0x0
 100                         >;
 101                 };
 102
 103                 pinctrl_uart1: uart1grp {
 104                         fsl,pins = <
 105                                 MX1_PAD_UART1_TXD__UART1_TXD    0x0
 106                                 MX1_PAD_UART1_RXD__UART1_RXD    0x0
 107                                 MX1_PAD_UART1_CTS__UART1_CTS    0x0
 108                                 MX1_PAD_UART1_RTS__UART1_RTS    0x0
 109                         >;
 110                 };
 111
 112                 pinctrl_uart2: uart2grp {
 113                         fsl,pins = <
 114                                 MX1_PAD_UART2_TXD__UART2_TXD    0x0
 115                                 MX1_PAD_UART2_RXD__UART2_RXD    0x0
 116                                 MX1_PAD_UART2_CTS__UART2_CTS    0x0
 117                                 MX1_PAD_UART2_RTS__UART2_RTS    0x0
 118                         >;
 119                 };
 120
 121                 pinctrl_weim: weimgrp {
 122                         fsl,pins = <
 123                                 MX1_PAD_A0__A0                  0x0
 124                                 MX1_PAD_A16__A16                0x0
 125                                 MX1_PAD_A17__A17                0x0
 126                                 MX1_PAD_A18__A18                0x0
 127                                 MX1_PAD_A19__A19                0x0
 128                                 MX1_PAD_A20__A20                0x0
 129                                 MX1_PAD_A21__A21                0x0
 130                                 MX1_PAD_A22__A22                0x0
 131                                 MX1_PAD_A23__A23                0x0
 132                                 MX1_PAD_A24__A24                0x0
 133                                 MX1_PAD_BCLK__BCLK              0x0
 134                                 MX1_PAD_CS4__CS4                0x0
 135                                 MX1_PAD_DTACK__DTACK            0x0
 136                                 MX1_PAD_ECB__ECB                0x0
 137                                 MX1_PAD_LBA__LBA                0x0
 138                         >;
 139                 };
 140         };
 141 };