arch/arm/boot/dts/hi3620.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hisilicon Ltd. Hi3620 SoC
   4  *
   5  * Copyright (C) 2012-2013 Hisilicon Ltd.
   6  * Copyright (C) 2012-2013 Linaro Ltd.
   7  *
   8  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   9  */
  10
  11 #include <dt-bindings/clock/hi3620-clock.h>
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20                 serial2 = &uart2;
  21                 serial3 = &uart3;
  22                 serial4 = &uart4;
  23         };
  24
  25         pclk: clk {
  26                 compatible = "fixed-clock";
  27                 #clock-cells = <0>;
  28                 clock-frequency = <26000000>;
  29                 clock-output-names = "apb_pclk";
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 enable-method = "hisilicon,hi3620-smp";
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <0x0>;
  41                         next-level-cache = <&L2>;
  42                 };
  43
  44                 cpu@1 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         reg = <1>;
  48                         next-level-cache = <&L2>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "arm,cortex-a9";
  53                         device_type = "cpu";
  54                         reg = <2>;
  55                         next-level-cache = <&L2>;
  56                 };
  57
  58                 cpu@3 {
  59                         compatible = "arm,cortex-a9";
  60                         device_type = "cpu";
  61                         reg = <3>;
  62                         next-level-cache = <&L2>;
  63                 };
  64         };
  65
  66         amba {
  67
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72                 ranges = <0 0xfc000000 0x2000000>;
  73
  74                 L2: l2-cache {
  75                         compatible = "arm,pl310-cache";
  76                         reg = <0x100000 0x100000>;
  77                         interrupts = <0 15 4>;
  78                         cache-unified;
  79                         cache-level = <2>;
  80                 };
  81
  82                 gic: interrupt-controller@1000 {
  83                         compatible = "arm,cortex-a9-gic";
  84                         #interrupt-cells = <3>;
  85                         #address-cells = <0>;
  86                         interrupt-controller;
  87                         /* gic dist base, gic cpu base */
  88                         reg = <0x1000 0x1000>, <0x100 0x100>;
  89                 };
  90
  91                 sysctrl: system-controller@802000 {
  92                         compatible = "hisilicon,sysctrl";
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         ranges = <0 0x802000 0x1000>;
  96                         reg = <0x802000 0x1000>;
  97
  98                         smp-offset = <0x31c>;
  99                         resume-offset = <0x308>;
 100                         reboot-offset = <0x4>;
 101
 102                         clock: clock@0 {
 103                                 compatible = "hisilicon,hi3620-clock";
 104                                 reg = <0 0x10000>;
 105                                 #clock-cells = <1>;
 106                         };
 107                 };
 108
 109                 dual_timer0: dual_timer@800000 {
 110                         compatible = "arm,sp804", "arm,primecell";
 111                         reg = <0x800000 0x1000>;
 112                         /* timer00 & timer01 */
 113                         interrupts = <0 0 4>, <0 1 4>;
 114                         clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
 115                         clock-names = "apb_pclk";
 116                         status = "disabled";
 117                 };
 118
 119                 dual_timer1: dual_timer@801000 {
 120                         compatible = "arm,sp804", "arm,primecell";
 121                         reg = <0x801000 0x1000>;
 122                         /* timer10 & timer11 */
 123                         interrupts = <0 2 4>, <0 3 4>;
 124                         clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
 125                         clock-names = "apb_pclk";
 126                         status = "disabled";
 127                 };
 128
 129                 dual_timer2: dual_timer@a01000 {
 130                         compatible = "arm,sp804", "arm,primecell";
 131                         reg = <0xa01000 0x1000>;
 132                         /* timer20 & timer21 */
 133                         interrupts = <0 4 4>, <0 5 4>;
 134                         clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
 135                         clock-names = "apb_pclk";
 136                         status = "disabled";
 137                 };
 138
 139                 dual_timer3: dual_timer@a02000 {
 140                         compatible = "arm,sp804", "arm,primecell";
 141                         reg = <0xa02000 0x1000>;
 142                         /* timer30 & timer31 */
 143                         interrupts = <0 6 4>, <0 7 4>;
 144                         clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
 145                         clock-names = "apb_pclk";
 146                         status = "disabled";
 147                 };
 148
 149                 dual_timer4: dual_timer@a03000 {
 150                         compatible = "arm,sp804", "arm,primecell";
 151                         reg = <0xa03000 0x1000>;
 152                         /* timer40 & timer41 */
 153                         interrupts = <0 96 4>, <0 97 4>;
 154                         clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
 155                         clock-names = "apb_pclk";
 156                         status = "disabled";
 157                 };
 158
 159                 timer5: timer@600 {
 160                         compatible = "arm,cortex-a9-twd-timer";
 161                         reg = <0x600 0x20>;
 162                         interrupts = <1 13 0xf01>;
 163                 };
 164
 165                 uart0: uart@b00000 {
 166                         compatible = "arm,pl011", "arm,primecell";
 167                         reg = <0xb00000 0x1000>;
 168                         interrupts = <0 20 4>;
 169                         clocks = <&clock HI3620_UARTCLK0>;
 170                         clock-names = "apb_pclk";
 171                         status = "disabled";
 172                 };
 173
 174                 uart1: uart@b01000 {
 175                         compatible = "arm,pl011", "arm,primecell";
 176                         reg = <0xb01000 0x1000>;
 177                         interrupts = <0 21 4>;
 178                         clocks = <&clock HI3620_UARTCLK1>;
 179                         clock-names = "apb_pclk";
 180                         status = "disabled";
 181                 };
 182
 183                 uart2: uart@b02000 {
 184                         compatible = "arm,pl011", "arm,primecell";
 185                         reg = <0xb02000 0x1000>;
 186                         interrupts = <0 22 4>;
 187                         clocks = <&clock HI3620_UARTCLK2>;
 188                         clock-names = "apb_pclk";
 189                         status = "disabled";
 190                 };
 191
 192                 uart3: uart@b03000 {
 193                         compatible = "arm,pl011", "arm,primecell";
 194                         reg = <0xb03000 0x1000>;
 195                         interrupts = <0 23 4>;
 196                         clocks = <&clock HI3620_UARTCLK3>;
 197                         clock-names = "apb_pclk";
 198                         status = "disabled";
 199                 };
 200
 201                 uart4: uart@b04000 {
 202                         compatible = "arm,pl011", "arm,primecell";
 203                         reg = <0xb04000 0x1000>;
 204                         interrupts = <0 24 4>;
 205                         clocks = <&clock HI3620_UARTCLK4>;
 206                         clock-names = "apb_pclk";
 207                         status = "disabled";
 208                 };
 209
 210                 gpio0: gpio@806000 {
 211                         compatible = "arm,pl061", "arm,primecell";
 212                         reg = <0x806000 0x1000>;
 213                         interrupts = <0 64 0x4>;
 214                         gpio-controller;
 215                         #gpio-cells = <2>;
 216                         gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
 217                                         &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
 218                         interrupt-controller;
 219                         #interrupt-cells = <2>;
 220                         clocks = <&clock HI3620_GPIOCLK0>;
 221                         clock-names = "apb_pclk";
 222                 };
 223
 224                 gpio1: gpio@807000 {
 225                         compatible = "arm,pl061", "arm,primecell";
 226                         reg = <0x807000 0x1000>;
 227                         interrupts = <0 65 0x4>;
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                         gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
 231                                         &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
 232                                         &pmx0 6 5 1 &pmx0 7 6 1>;
 233                         interrupt-controller;
 234                         #interrupt-cells = <2>;
 235                         clocks = <&clock HI3620_GPIOCLK1>;
 236                         clock-names = "apb_pclk";
 237                 };
 238
 239                 gpio2: gpio@808000 {
 240                         compatible = "arm,pl061", "arm,primecell";
 241                         reg = <0x808000 0x1000>;
 242                         interrupts = <0 66 0x4>;
 243                         gpio-controller;
 244                         #gpio-cells = <2>;
 245                         gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
 246                                         &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
 247                                         &pmx0 6 3 1 &pmx0 7 3 1>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                         clocks = <&clock HI3620_GPIOCLK2>;
 251                         clock-names = "apb_pclk";
 252                 };
 253
 254                 gpio3: gpio@809000 {
 255                         compatible = "arm,pl061", "arm,primecell";
 256                         reg = <0x809000 0x1000>;
 257                         interrupts = <0 67 0x4>;
 258                         gpio-controller;
 259                         #gpio-cells = <2>;
 260                         gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
 261                                         &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
 262                                         &pmx0 6 11 1 &pmx0 7 11 1>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                         clocks = <&clock HI3620_GPIOCLK3>;
 266                         clock-names = "apb_pclk";
 267                 };
 268
 269                 gpio4: gpio@80a000 {
 270                         compatible = "arm,pl061", "arm,primecell";
 271                         reg = <0x80a000 0x1000>;
 272                         interrupts = <0 68 0x4>;
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
 276                                         &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
 277                                         &pmx0 6 13 1 &pmx0 7 13 1>;
 278                         interrupt-controller;
 279                         #interrupt-cells = <2>;
 280                         clocks = <&clock HI3620_GPIOCLK4>;
 281                         clock-names = "apb_pclk";
 282                 };
 283
 284                 gpio5: gpio@80b000 {
 285                         compatible = "arm,pl061", "arm,primecell";
 286                         reg = <0x80b000 0x1000>;
 287                         interrupts = <0 69 0x4>;
 288                         gpio-controller;
 289                         #gpio-cells = <2>;
 290                         gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
 291                                         &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
 292                                         &pmx0 6 16 1 &pmx0 7 16 1>;
 293                         interrupt-controller;
 294                         #interrupt-cells = <2>;
 295                         clocks = <&clock HI3620_GPIOCLK5>;
 296                         clock-names = "apb_pclk";
 297                 };
 298
 299                 gpio6: gpio@80c000 {
 300                         compatible = "arm,pl061", "arm,primecell";
 301                         reg = <0x80c000 0x1000>;
 302                         interrupts = <0 70 0x4>;
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305                         gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
 306                                         &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
 307                                         &pmx0 6 18 1 &pmx0 7 19 1>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                         clocks = <&clock HI3620_GPIOCLK6>;
 311                         clock-names = "apb_pclk";
 312                 };
 313
 314                 gpio7: gpio@80d000 {
 315                         compatible = "arm,pl061", "arm,primecell";
 316                         reg = <0x80d000 0x1000>;
 317                         interrupts = <0 71 0x4>;
 318                         gpio-controller;
 319                         #gpio-cells = <2>;
 320                         gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
 321                                         &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
 322                                         &pmx0 6 25 1 &pmx0 7 26 1>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                         clocks = <&clock HI3620_GPIOCLK7>;
 326                         clock-names = "apb_pclk";
 327                 };
 328
 329                 gpio8: gpio@80e000 {
 330                         compatible = "arm,pl061", "arm,primecell";
 331                         reg = <0x80e000 0x1000>;
 332                         interrupts = <0 72 0x4>;
 333                         gpio-controller;
 334                         #gpio-cells = <2>;
 335                         gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
 336                                         &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
 337                                         &pmx0 6 33 1 &pmx0 7 34 1>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                         clocks = <&clock HI3620_GPIOCLK8>;
 341                         clock-names = "apb_pclk";
 342                 };
 343
 344                 gpio9: gpio@80f000 {
 345                         compatible = "arm,pl061", "arm,primecell";
 346                         reg = <0x80f000 0x1000>;
 347                         interrupts = <0 73 0x4>;
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
 351                                         &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
 352                                         &pmx0 6 41 1>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                         clocks = <&clock HI3620_GPIOCLK9>;
 356                         clock-names = "apb_pclk";
 357                 };
 358
 359                 gpio10: gpio@810000 {
 360                         compatible = "arm,pl061", "arm,primecell";
 361                         reg = <0x810000 0x1000>;
 362                         interrupts = <0 74 0x4>;
 363                         gpio-controller;
 364                         #gpio-cells = <2>;
 365                         gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
 366                                         &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                         clocks = <&clock HI3620_GPIOCLK10>;
 370                         clock-names = "apb_pclk";
 371                 };
 372
 373                 gpio11: gpio@811000 {
 374                         compatible = "arm,pl061", "arm,primecell";
 375                         reg = <0x811000 0x1000>;
 376                         interrupts = <0 75 0x4>;
 377                         gpio-controller;
 378                         #gpio-cells = <2>;
 379                         gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
 380                                         &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
 381                                         &pmx0 6 49 1 &pmx0 7 49 1>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                         clocks = <&clock HI3620_GPIOCLK11>;
 385                         clock-names = "apb_pclk";
 386                 };
 387
 388                 gpio12: gpio@812000 {
 389                         compatible = "arm,pl061", "arm,primecell";
 390                         reg = <0x812000 0x1000>;
 391                         interrupts = <0 76 0x4>;
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                         gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
 395                                         &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
 396                                         &pmx0 6 51 1 &pmx0 7 52 1>;
 397                         interrupt-controller;
 398                         #interrupt-cells = <2>;
 399                         clocks = <&clock HI3620_GPIOCLK12>;
 400                         clock-names = "apb_pclk";
 401                 };
 402
 403                 gpio13: gpio@813000 {
 404                         compatible = "arm,pl061", "arm,primecell";
 405                         reg = <0x813000 0x1000>;
 406                         interrupts = <0 77 0x4>;
 407                         gpio-controller;
 408                         #gpio-cells = <2>;
 409                         gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
 410                                         &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
 411                                         &pmx0 6 55 1 &pmx0 7 56 1>;
 412                         interrupt-controller;
 413                         #interrupt-cells = <2>;
 414                         clocks = <&clock HI3620_GPIOCLK13>;
 415                         clock-names = "apb_pclk";
 416                 };
 417
 418                 gpio14: gpio@814000 {
 419                         compatible = "arm,pl061", "arm,primecell";
 420                         reg = <0x814000 0x1000>;
 421                         interrupts = <0 78 0x4>;
 422                         gpio-controller;
 423                         #gpio-cells = <2>;
 424                         gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
 425                                         &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
 426                                         &pmx0 6 60 1 &pmx0 7 61 1>;
 427                         interrupt-controller;
 428                         #interrupt-cells = <2>;
 429                         clocks = <&clock HI3620_GPIOCLK14>;
 430                         clock-names = "apb_pclk";
 431                 };
 432
 433                 gpio15: gpio@815000 {
 434                         compatible = "arm,pl061", "arm,primecell";
 435                         reg = <0x815000 0x1000>;
 436                         interrupts = <0 79 0x4>;
 437                         gpio-controller;
 438                         #gpio-cells = <2>;
 439                         gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
 440                                         &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
 441                                         &pmx0 6 64 1 &pmx0 7 65 1>;
 442                         interrupt-controller;
 443                         #interrupt-cells = <2>;
 444                         clocks = <&clock HI3620_GPIOCLK15>;
 445                         clock-names = "apb_pclk";
 446                 };
 447
 448                 gpio16: gpio@816000 {
 449                         compatible = "arm,pl061", "arm,primecell";
 450                         reg = <0x816000 0x1000>;
 451                         interrupts = <0 80 0x4>;
 452                         gpio-controller;
 453                         #gpio-cells = <2>;
 454                         gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
 455                                         &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
 456                                         &pmx0 6 72 1 &pmx0 7 73 1>;
 457                         interrupt-controller;
 458                         #interrupt-cells = <2>;
 459                         clocks = <&clock HI3620_GPIOCLK16>;
 460                         clock-names = "apb_pclk";
 461                 };
 462
 463                 gpio17: gpio@817000 {
 464                         compatible = "arm,pl061", "arm,primecell";
 465                         reg = <0x817000 0x1000>;
 466                         interrupts = <0 81 0x4>;
 467                         gpio-controller;
 468                         #gpio-cells = <2>;
 469                         gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
 470                                         &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
 471                                         &pmx0 6 80 1 &pmx0 7 81 1>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <2>;
 474                         clocks = <&clock HI3620_GPIOCLK17>;
 475                         clock-names = "apb_pclk";
 476                 };
 477
 478                 gpio18: gpio@818000 {
 479                         compatible = "arm,pl061", "arm,primecell";
 480                         reg = <0x818000 0x1000>;
 481                         interrupts = <0 82 0x4>;
 482                         gpio-controller;
 483                         #gpio-cells = <2>;
 484                         gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
 485                                         &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
 486                                         &pmx0 6 86 1 &pmx0 7 87 1>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                         clocks = <&clock HI3620_GPIOCLK18>;
 490                         clock-names = "apb_pclk";
 491                 };
 492
 493                 gpio19: gpio@819000 {
 494                         compatible = "arm,pl061", "arm,primecell";
 495                         reg = <0x819000 0x1000>;
 496                         interrupts = <0 83 0x4>;
 497                         gpio-controller;
 498                         #gpio-cells = <2>;
 499                         gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
 500                                         &pmx0 3 88 1>;
 501                         interrupt-controller;
 502                         #interrupt-cells = <2>;
 503                         clocks = <&clock HI3620_GPIOCLK19>;
 504                         clock-names = "apb_pclk";
 505                 };
 506
 507                 gpio20: gpio@81a000 {
 508                         compatible = "arm,pl061", "arm,primecell";
 509                         reg = <0x81a000 0x1000>;
 510                         interrupts = <0 84 0x4>;
 511                         gpio-controller;
 512                         #gpio-cells = <2>;
 513                         gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
 514                                         &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
 515                         interrupt-controller;
 516                         #interrupt-cells = <2>;
 517                         clocks = <&clock HI3620_GPIOCLK20>;
 518                         clock-names = "apb_pclk";
 519                 };
 520
 521                 gpio21: gpio@81b000 {
 522                         compatible = "arm,pl061", "arm,primecell";
 523                         reg = <0x81b000 0x1000>;
 524                         interrupts = <0 85 0x4>;
 525                         gpio-controller;
 526                         #gpio-cells = <2>;
 527                         gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                         clocks = <&clock HI3620_GPIOCLK21>;
 531                         clock-names = "apb_pclk";
 532                 };
 533
 534                 pmx0: pinmux@803000 {
 535                         compatible = "pinctrl-single";
 536                         reg = <0x803000 0x188>;
 537                         #address-cells = <1>;
 538                         #size-cells = <1>;
 539                         #pinctrl-cells = <1>;
 540                         #gpio-range-cells = <3>;
 541                         ranges;
 542
 543                         pinctrl-single,register-width = <32>;
 544                         pinctrl-single,function-mask = <7>;
 545                         /* pin base, nr pins & gpio function */
 546                         pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
 547                                                 &range 12 1 0 &range 13 29 1
 548                                                 &range 43 1 0 &range 44 49 1
 549                                                 &range 94 1 1 &range 96 2 1>;
 550
 551                         range: gpio-range {
 552                                 #pinctrl-single,gpio-range-cells = <3>;
 553                         };
 554                 };
 555
 556                 pmx1: pinmux@803800 {
 557                         compatible = "pinconf-single";
 558                         reg = <0x803800 0x2dc>;
 559                         #address-cells = <1>;
 560                         #size-cells = <1>;
 561                         #pinctrl-cells = <1>;
 562                         ranges;
 563
 564                         pinctrl-single,register-width = <32>;
 565                 };
 566         };
 567 };