Merge branches 'acpi-button', 'acpica' and 'acpi-sysfs'
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / gemini.dtsi
1 /*
2  * Device Tree file for Cortina systems Gemini SoC
3  */
4
5 /include/ "skeleton.dtsi"
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
9
10 / {
11         soc {
12                 #address-cells = <1>;
13                 #size-cells = <1>;
14                 ranges;
15                 compatible = "simple-bus";
16                 interrupt-parent = <&intcon>;
17
18                 flash@30000000 {
19                         compatible = "cortina,gemini-flash", "cfi-flash";
20                         syscon = <&syscon>;
21                         bank-width = <2>;
22                         #address-cells = <1>;
23                         #size-cells = <1>;
24                         status = "disabled";
25                 };
26
27                 syscon: syscon@40000000 {
28                         compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
29                         reg = <0x40000000 0x1000>;
30
31                         syscon-reboot {
32                                 compatible = "syscon-reboot";
33                                 regmap = <&syscon>;
34                                 /* GLOBAL_RESET register */
35                                 offset = <0x0c>;
36                                 /* RESET_GLOBAL | RESET_CPU1 */
37                                 mask = <0xC0000000>;
38                         };
39                 };
40
41                 watchdog@41000000 {
42                         compatible = "cortina,gemini-watchdog";
43                         reg = <0x41000000 0x1000>;
44                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
45                 };
46
47                 uart0: serial@42000000 {
48                         compatible = "ns16550a";
49                         reg = <0x42000000 0x100>;
50                         clock-frequency = <48000000>;
51                         interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
52                         reg-shift = <2>;
53                 };
54
55                 timer@43000000 {
56                         compatible = "cortina,gemini-timer";
57                         reg = <0x43000000 0x1000>;
58                         interrupt-parent = <&intcon>;
59                         interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
60                                      <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
61                                      <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
62                         syscon = <&syscon>;
63                 };
64
65                 rtc@45000000 {
66                         compatible = "cortina,gemini-rtc";
67                         reg = <0x45000000 0x100>;
68                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
69                 };
70
71                 intcon: interrupt-controller@48000000 {
72                         compatible = "faraday,ftintc010";
73                         reg = <0x48000000 0x1000>;
74                         interrupt-controller;
75                         #interrupt-cells = <2>;
76                 };
77
78                 power-controller@4b000000 {
79                         compatible = "cortina,gemini-power-controller";
80                         reg = <0x4b000000 0x100>;
81                         interrupts = <26 IRQ_TYPE_EDGE_RISING>;
82                 };
83
84                 gpio0: gpio@4d000000 {
85                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
86                         reg = <0x4d000000 0x100>;
87                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
88                         gpio-controller;
89                         #gpio-cells = <2>;
90                         interrupt-controller;
91                         #interrupt-cells = <2>;
92                 };
93
94                 gpio1: gpio@4e000000 {
95                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
96                         reg = <0x4e000000 0x100>;
97                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
98                         gpio-controller;
99                         #gpio-cells = <2>;
100                         interrupt-controller;
101                         #interrupt-cells = <2>;
102                 };
103
104                 gpio2: gpio@4f000000 {
105                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
106                         reg = <0x4f000000 0x100>;
107                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
108                         gpio-controller;
109                         #gpio-cells = <2>;
110                         interrupt-controller;
111                         #interrupt-cells = <2>;
112                 };
113
114                 pci@50000000 {
115                         compatible = "cortina,gemini-pci", "faraday,ftpci100";
116                         /*
117                          * The first 256 bytes in the IO range is actually used
118                          * to configure the host bridge.
119                          */
120                         reg = <0x50000000 0x100>;
121                         #address-cells = <3>;
122                         #size-cells = <2>;
123                         #interrupt-cells = <1>;
124                         status = "disabled";
125
126                         bus-range = <0x00 0xff>;
127                         /* PCI ranges mappings */
128                         ranges =
129                         /* 1MiB I/O space 0x50000000-0x500fffff */
130                         <0x01000000 0 0          0x50000000 0 0x00100000>,
131                         /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
132                         <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
133
134                         /* DMA ranges */
135                         dma-ranges =
136                         /* 128MiB at 0x00000000-0x07ffffff */
137                         <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
138                         /* 64MiB at 0x00000000-0x03ffffff */
139                         <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
140                         /* 64MiB at 0x00000000-0x03ffffff */
141                         <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
142
143                         /*
144                          * This PCI host bridge variant has a cascaded interrupt
145                          * controller embedded in the host bridge.
146                          */
147                         pci_intc: interrupt-controller {
148                                 interrupt-parent = <&intcon>;
149                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
150                                 interrupt-controller;
151                                 #address-cells = <0>;
152                                 #interrupt-cells = <1>;
153                         };
154                 };
155         };
156 };