arch/arm/boot/dts/gemini-sq201.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree file for ITian Square One SQ201 NAS
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "gemini.dtsi"
   9 #include <dt-bindings/input/input.h>
  10
  11 / {
  12         model = "ITian Square One SQ201";
  13         compatible = "itian,sq201", "cortina,gemini";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         memory@0 { /* 128 MB */
  18                 device_type = "memory";
  19                 reg = <0x00000000 0x8000000>;
  20         };
  21
  22         chosen {
  23                 bootargs = "console=ttyS0,115200n8";
  24                 stdout-path = &uart0;
  25         };
  26
  27         gpio_keys {
  28                 compatible = "gpio-keys";
  29
  30                 button-setup {
  31                         debounce-interval = <50>;
  32                         wakeup-source;
  33                         linux,code = <KEY_SETUP>;
  34                         label = "factory reset";
  35                         /* Conflict with NAND flash */
  36                         gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  37                 };
  38         };
  39
  40         leds {
  41                 compatible = "gpio-leds";
  42                 led-green-info {
  43                         label = "sq201:green:info";
  44                         /* Conflict with parallel flash */
  45                         gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
  46                         default-state = "on";
  47                         linux,default-trigger = "heartbeat";
  48                 };
  49                 led-green-usb {
  50                         label = "sq201:green:usb";
  51                         /* Conflict with parallel and NAND flash */
  52                         gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
  53                         default-state = "off";
  54                         linux,default-trigger = "usb-host";
  55                 };
  56         };
  57
  58         mdio0: mdio {
  59                 compatible = "virtual,mdio-gpio";
  60                 /* Uses MDC and MDIO */
  61                 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
  62                         <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 /* This is a Marvell 88E1111 ethernet transciever */
  67                 phy0: ethernet-phy@1 {
  68                         reg = <1>;
  69                 };
  70         };
  71
  72         spi {
  73                 compatible = "spi-gpio";
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76                 /* Check pin collisions */
  77                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  78                 gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  79                 gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  80                 cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
  81                 num-chipselects = <1>;
  82
  83                 switch@0 {
  84                         compatible = "vitesse,vsc7395";
  85                         reg = <0>;
  86                         /* Specified for 2.5 MHz or below */
  87                         spi-max-frequency = <2500000>;
  88                         gpio-controller;
  89                         #gpio-cells = <2>;
  90
  91                         ports {
  92                                 #address-cells = <1>;
  93                                 #size-cells = <0>;
  94
  95                                 port@0 {
  96                                         reg = <0>;
  97                                         label = "lan1";
  98                                 };
  99                                 port@1 {
 100                                         reg = <1>;
 101                                         label = "lan2";
 102                                 };
 103                                 port@2 {
 104                                         reg = <2>;
 105                                         label = "lan3";
 106                                 };
 107                                 port@3 {
 108                                         reg = <3>;
 109                                         label = "lan4";
 110                                 };
 111                                 vsc: port@6 {
 112                                         reg = <6>;
 113                                         label = "cpu";
 114                                         ethernet = <&gmac1>;
 115                                         phy-mode = "rgmii";
 116                                         fixed-link {
 117                                                 speed = <1000>;
 118                                                 full-duplex;
 119                                                 pause;
 120                                         };
 121                                 };
 122                         };
 123                 };
 124         };
 125
 126
 127         soc {
 128                 flash@30000000 {
 129                         /*
 130                          * Flash access can be enabled, with the side effect
 131                          * of disabling access to GPIO LED on GPIO0[20] which
 132                          * reuse one of the parallel flash chip select lines.
 133                          * Also the default firmware on the machine has the
 134                          * problem that since it uses the flash, the two LEDS
 135                          * on the right become numb.
 136                          */
 137                         /* status = "okay"; */
 138                         /* 16MB of flash */
 139                         reg = <0x30000000 0x01000000>;
 140
 141                         partition@0 {
 142                                 label = "RedBoot";
 143                                 reg = <0x00000000 0x00120000>;
 144                                 read-only;
 145                         };
 146                         partition@120000 {
 147                                 label = "Kernel";
 148                                 reg = <0x00120000 0x00200000>;
 149                         };
 150                         partition@320000 {
 151                                 label = "Ramdisk";
 152                                 reg = <0x00320000 0x00600000>;
 153                         };
 154                         partition@920000 {
 155                                 label = "Application";
 156                                 reg = <0x00920000 0x00600000>;
 157                         };
 158                         partition@f20000 {
 159                                 label = "VCTL";
 160                                 reg = <0x00f20000 0x00020000>;
 161                                 read-only;
 162                         };
 163                         partition@f40000 {
 164                                 label = "CurConf";
 165                                 reg = <0x00f40000 0x000a0000>;
 166                                 read-only;
 167                         };
 168                         partition@fe0000 {
 169                                 label = "FIS directory";
 170                                 reg = <0x00fe0000 0x00020000>;
 171                                 read-only;
 172                         };
 173                 };
 174
 175                 syscon: syscon@40000000 {
 176                         pinctrl {
 177                                 /*
 178                                  * gpio0fgrp cover line 18 used by reset button
 179                                  * gpio0ggrp cover line 20 used by info LED
 180                                  * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
 181                                  * gpio0kgrp cover line 31 used by USB LED
 182                                  */
 183                                 gpio0_default_pins: pinctrl-gpio0 {
 184                                         mux {
 185                                                 function = "gpio0";
 186                                                 groups = "gpio0fgrp",
 187                                                 "gpio0ggrp",
 188                                                 "gpio0hgrp",
 189                                                 "gpio0kgrp";
 190                                         };
 191                                 };
 192                                 /*
 193                                  * gpio0dgrp cover lines used by the SPI
 194                                  * to the Vitesse G5x chip.
 195                                  */
 196                                 gpio1_default_pins: pinctrl-gpio1 {
 197                                         mux {
 198                                                 function = "gpio1";
 199                                                 groups = "gpio1dgrp";
 200                                         };
 201                                 };
 202                                 pinctrl-gmii {
 203                                         mux {
 204                                                 function = "gmii";
 205                                                 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
 206                                         };
 207                                         /* Settings come from memory dump in PLATO */
 208                                         conf0 {
 209                                                 pins = "V8 GMAC0 RXDV";
 210                                                 skew-delay = <0>;
 211                                         };
 212                                         conf1 {
 213                                                 pins = "Y7 GMAC0 RXC";
 214                                                 skew-delay = <15>;
 215                                         };
 216                                         conf2 {
 217                                                 pins = "T8 GMAC0 TXEN";
 218                                                 skew-delay = <7>;
 219                                         };
 220                                         conf3 {
 221                                                 pins = "U8 GMAC0 TXC";
 222                                                 skew-delay = <10>;
 223                                         };
 224                                         conf4 {
 225                                                 pins = "T10 GMAC1 RXDV";
 226                                                 skew-delay = <7>;
 227                                         };
 228                                         conf5 {
 229                                                 pins = "Y11 GMAC1 RXC";
 230                                                 skew-delay = <8>;
 231                                         };
 232                                         conf6 {
 233                                                 pins = "W11 GMAC1 TXEN";
 234                                                 skew-delay = <7>;
 235                                         };
 236                                         conf7 {
 237                                                 pins = "V11 GMAC1 TXC";
 238                                                 skew-delay = <5>;
 239                                         };
 240                                         conf8 {
 241                                                 /* The data lines all have default skew */
 242                                                 pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
 243                                                        "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
 244                                                        "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
 245                                                        "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
 246                                                        "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
 247                                                        "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
 248                                                        "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
 249                                                        "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
 250                                                 skew-delay = <7>;
 251                                         };
 252                                         /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
 253                                         conf9 {
 254                                                 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
 255                                                 drive-strength = <16>;
 256                                         };
 257                                 };
 258                         };
 259                 };
 260
 261                 sata: sata@46000000 {
 262                         cortina,gemini-ata-muxmode = <0>;
 263                         cortina,gemini-enable-sata-bridge;
 264                         status = "okay";
 265                 };
 266
 267                 gpio0: gpio@4d000000 {
 268                         pinctrl-names = "default";
 269                         pinctrl-0 = <&gpio0_default_pins>;
 270                 };
 271
 272                 gpio1: gpio@4e000000 {
 273                         pinctrl-names = "default";
 274                         pinctrl-0 = <&gpio1_default_pins>;
 275                 };
 276
 277                 pci@50000000 {
 278                         status = "okay";
 279                         interrupt-map-mask = <0xf800 0 0 7>;
 280                         interrupt-map =
 281                                 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
 282                                 <0x4800 0 0 2 &pci_intc 1>,
 283                                 <0x4800 0 0 3 &pci_intc 2>,
 284                                 <0x4800 0 0 4 &pci_intc 3>,
 285                                 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
 286                                 <0x5000 0 0 2 &pci_intc 2>,
 287                                 <0x5000 0 0 3 &pci_intc 3>,
 288                                 <0x5000 0 0 4 &pci_intc 0>,
 289                                 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
 290                                 <0x5800 0 0 2 &pci_intc 3>,
 291                                 <0x5800 0 0 3 &pci_intc 0>,
 292                                 <0x5800 0 0 4 &pci_intc 1>,
 293                                 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
 294                                 <0x6000 0 0 2 &pci_intc 0>,
 295                                 <0x6000 0 0 3 &pci_intc 1>,
 296                                 <0x6000 0 0 4 &pci_intc 2>;
 297                 };
 298
 299                 ethernet@60000000 {
 300                         status = "okay";
 301
 302                         ethernet-port@0 {
 303                                 phy-mode = "rgmii";
 304                                 phy-handle = <&phy0>;
 305                         };
 306                         ethernet-port@1 {
 307                                 phy-mode = "rgmii";
 308                                 fixed-link {
 309                                         speed = <1000>;
 310                                         full-duplex;
 311                                         pause;
 312                                 };
 313                         };
 314                 };
 315
 316                 ata@63000000 {
 317                         status = "okay";
 318                 };
 319         };
 320 };