arch/arm/boot/dts/exynos5440.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5440 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos5440.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         compatible = "samsung,exynos5440", "samsung,exynos5";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 serial0 = &serial_0;
  22                 serial1 = &serial_1;
  23                 spi0 = &spi_0;
  24                 tmuctrl0 = &tmuctrl_0;
  25                 tmuctrl1 = &tmuctrl_1;
  26                 tmuctrl2 = &tmuctrl_2;
  27         };
  28
  29         clock: clock-controller@160000 {
  30                 compatible = "samsung,exynos5440-clock";
  31                 reg = <0x160000 0x1000>;
  32                 #clock-cells = <1>;
  33         };
  34
  35         gic: interrupt-controller@2e0000 {
  36                 compatible = "arm,cortex-a15-gic";
  37                 #interrupt-cells = <3>;
  38                 interrupt-controller;
  39                 reg =   <0x2E1000 0x1000>,
  40                         <0x2E2000 0x2000>,
  41                         <0x2E4000 0x2000>,
  42                         <0x2E6000 0x2000>;
  43                 interrupts = <GIC_PPI 9
  44                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0>;
  55                 };
  56                 cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <1>;
  60                 };
  61                 cpu@2 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <2>;
  65                 };
  66                 cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <3>;
  70                 };
  71         };
  72
  73         arm-pmu {
  74                 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
  75                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  79         };
  80
  81         timer {
  82                 compatible = "arm,cortex-a15-timer",
  83                              "arm,armv7-timer";
  84                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  88                 clock-frequency = <50000000>;
  89         };
  90
  91         cpufreq@160000 {
  92                 compatible = "samsung,exynos5440-cpufreq";
  93                 reg = <0x160000 0x1000>;
  94                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  95                 operating-points = <
  96                                 /* KHz    uV */
  97                                 1500000 1100000
  98                                 1400000 1075000
  99                                 1300000 1050000
 100                                 1200000 1025000
 101                                 1100000 1000000
 102                                 1000000 975000
 103                                 900000  950000
 104                                 800000  925000
 105                 >;
 106         };
 107
 108         serial_0: serial@b0000 {
 109                 compatible = "samsung,exynos4210-uart";
 110                 reg = <0xB0000 0x1000>;
 111                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 112                 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
 113                 clock-names = "uart", "clk_uart_baud0";
 114         };
 115
 116         serial_1: serial@c0000 {
 117                 compatible = "samsung,exynos4210-uart";
 118                 reg = <0xC0000 0x1000>;
 119                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 120                 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
 121                 clock-names = "uart", "clk_uart_baud0";
 122         };
 123
 124         spi_0: spi@d0000 {
 125                 compatible = "samsung,exynos5440-spi";
 126                 reg = <0xD0000 0x100>;
 127                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130                 samsung,spi-src-clk = <0>;
 131                 num-cs = <1>;
 132                 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
 133                 clock-names = "spi", "spi_busclk0";
 134         };
 135
 136         pin_ctrl: pinctrl@e0000 {
 137                 compatible = "samsung,exynos5440-pinctrl";
 138                 reg = <0xE0000 0x1000>;
 139                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 147                 interrupt-controller;
 148                 #interrupt-cells = <2>;
 149                 #gpio-cells = <2>;
 150
 151                 fan: fan {
 152                         samsung,exynos5440-pin-function = <1>;
 153                 };
 154
 155                 hdd_led0: hdd_led0 {
 156                         samsung,exynos5440-pin-function = <2>;
 157                 };
 158
 159                 hdd_led1: hdd_led1 {
 160                         samsung,exynos5440-pin-function = <3>;
 161                 };
 162
 163                 uart1: uart1 {
 164                         samsung,exynos5440-pin-function = <4>;
 165                 };
 166         };
 167
 168         i2c@f0000 {
 169                 compatible = "samsung,exynos5440-i2c";
 170                 reg = <0xF0000 0x1000>;
 171                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 clocks = <&clock CLK_B_125>;
 175                 clock-names = "i2c";
 176         };
 177
 178         i2c@100000 {
 179                 compatible = "samsung,exynos5440-i2c";
 180                 reg = <0x100000 0x1000>;
 181                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 clocks = <&clock CLK_B_125>;
 185                 clock-names = "i2c";
 186         };
 187
 188         watchdog@110000 {
 189                 compatible = "samsung,s3c6410-wdt";
 190                 reg = <0x110000 0x1000>;
 191                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&clock CLK_B_125>;
 193                 clock-names = "watchdog";
 194         };
 195
 196         gmac: ethernet@230000 {
 197                 compatible = "snps,dwmac-3.70a", "snps,dwmac";
 198                 reg = <0x00230000 0x8000>;
 199                 interrupt-parent = <&gic>;
 200                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 201                 interrupt-names = "macirq";
 202                 phy-mode = "sgmii";
 203                 clocks = <&clock CLK_GMAC0>;
 204                 clock-names = "stmmaceth";
 205         };
 206
 207         amba {
 208                 #address-cells = <1>;
 209                 #size-cells = <1>;
 210                 compatible = "simple-bus";
 211                 interrupt-parent = <&gic>;
 212                 ranges;
 213         };
 214
 215         rtc@130000 {
 216                 compatible = "samsung,s3c6410-rtc";
 217                 reg = <0x130000 0x1000>;
 218                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&clock CLK_B_125>;
 221                 clock-names = "rtc";
 222         };
 223
 224         tmuctrl_0: tmuctrl@160118 {
 225                 compatible = "samsung,exynos5440-tmu";
 226                 reg = <0x160118 0x230>, <0x160368 0x10>;
 227                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&clock CLK_B_125>;
 229                 clock-names = "tmu_apbif";
 230                 #include "exynos5440-tmu-sensor-conf.dtsi"
 231         };
 232
 233         tmuctrl_1: tmuctrl@16011c {
 234                 compatible = "samsung,exynos5440-tmu";
 235                 reg = <0x16011C 0x230>, <0x160368 0x10>;
 236                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&clock CLK_B_125>;
 238                 clock-names = "tmu_apbif";
 239                 #include "exynos5440-tmu-sensor-conf.dtsi"
 240         };
 241
 242         tmuctrl_2: tmuctrl@160120 {
 243                 compatible = "samsung,exynos5440-tmu";
 244                 reg = <0x160120 0x230>, <0x160368 0x10>;
 245                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&clock CLK_B_125>;
 247                 clock-names = "tmu_apbif";
 248                 #include "exynos5440-tmu-sensor-conf.dtsi"
 249         };
 250
 251         thermal-zones {
 252                 cpu0_thermal: cpu0-thermal {
 253                         thermal-sensors = <&tmuctrl_0>;
 254                         #include "exynos5440-trip-points.dtsi"
 255                 };
 256                 cpu1_thermal: cpu1-thermal {
 257                        thermal-sensors = <&tmuctrl_1>;
 258                        #include "exynos5440-trip-points.dtsi"
 259                 };
 260                 cpu2_thermal: cpu2-thermal {
 261                        thermal-sensors = <&tmuctrl_2>;
 262                        #include "exynos5440-trip-points.dtsi"
 263                 };
 264         };
 265
 266         sata@210000 {
 267                 compatible = "snps,exynos5440-ahci";
 268                 reg = <0x210000 0x10000>;
 269                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&clock CLK_SATA>;
 271                 clock-names = "sata";
 272         };
 273
 274         ohci@220000 {
 275                 compatible = "samsung,exynos5440-ohci";
 276                 reg = <0x220000 0x1000>;
 277                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&clock CLK_USB>;
 279                 clock-names = "usbhost";
 280         };
 281
 282         ehci@221000 {
 283                 compatible = "samsung,exynos5440-ehci";
 284                 reg = <0x221000 0x1000>;
 285                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&clock CLK_USB>;
 287                 clock-names = "usbhost";
 288         };
 289
 290         pcie_phy0: pcie-phy@270000 {
 291                 #phy-cells = <0>;
 292                 compatible = "samsung,exynos5440-pcie-phy";
 293                 reg = <0x270000 0x1000>, <0x271000 0x40>;
 294         };
 295
 296         pcie_phy1: pcie-phy@272000 {
 297                 #phy-cells = <0>;
 298                 compatible = "samsung,exynos5440-pcie-phy";
 299                 reg = <0x272000 0x1000>, <0x271040 0x40>;
 300         };
 301
 302         pcie_0: pcie@290000 {
 303                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 304                 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
 305                 reg-names = "elbi", "config";
 306                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
 310                 clock-names = "pcie", "pcie_bus";
 311                 #address-cells = <3>;
 312                 #size-cells = <2>;
 313                 device_type = "pci";
 314                 phys = <&pcie_phy0>;
 315                 ranges = <0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
 316                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
 317                 bus-range = <0x00 0xff>;
 318                 #interrupt-cells = <1>;
 319                 interrupt-map-mask = <0 0 0 0>;
 320                 interrupt-map = <0x0 0 &gic 53>;
 321                 num-lanes = <4>;
 322                 status = "disabled";
 323         };
 324
 325         pcie_1: pcie@2a0000 {
 326                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 327                 reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
 328                 reg-names = "elbi", "config";
 329                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
 333                 clock-names = "pcie", "pcie_bus";
 334                 #address-cells = <3>;
 335                 #size-cells = <2>;
 336                 device_type = "pci";
 337                 phys = <&pcie_phy1>;
 338                 ranges = <0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
 339                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
 340                 bus-range = <0x00 0xff>;
 341                 #interrupt-cells = <1>;
 342                 interrupt-map-mask = <0 0 0 0>;
 343                 interrupt-map = <0x0 0 &gic 56>;
 344                 num-lanes = <4>;
 345                 status = "disabled";
 346         };
 347 };