arch/arm/boot/dts/exynos5440.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5440 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <dt-bindings/clock/exynos5440.h>
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "samsung,exynos5440", "samsung,exynos5";
  17
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 spi0 = &spi_0;
  22                 tmuctrl0 = &tmuctrl_0;
  23                 tmuctrl1 = &tmuctrl_1;
  24                 tmuctrl2 = &tmuctrl_2;
  25         };
  26
  27         clock: clock-controller@160000 {
  28                 compatible = "samsung,exynos5440-clock";
  29                 reg = <0x160000 0x1000>;
  30                 #clock-cells = <1>;
  31         };
  32
  33         gic: interrupt-controller@2E0000 {
  34                 compatible = "arm,cortex-a15-gic";
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg =   <0x2E1000 0x1000>,
  38                         <0x2E2000 0x1000>,
  39                         <0x2E4000 0x2000>,
  40                         <0x2E6000 0x2000>;
  41                 interrupts = <1 9 0xf04>;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0>;
  52                 };
  53                 cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a15";
  56                         reg = <1>;
  57                 };
  58                 cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <2>;
  62                 };
  63                 cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <3>;
  67                 };
  68         };
  69
  70         arm-pmu {
  71                 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
  72                 interrupts = <0 52 4>,
  73                              <0 53 4>,
  74                              <0 54 4>,
  75                              <0 55 4>;
  76         };
  77
  78         timer {
  79                 compatible = "arm,cortex-a15-timer",
  80                              "arm,armv7-timer";
  81                 interrupts = <1 13 0xf08>,
  82                              <1 14 0xf08>,
  83                              <1 11 0xf08>,
  84                              <1 10 0xf08>;
  85                 clock-frequency = <50000000>;
  86         };
  87
  88         cpufreq@160000 {
  89                 compatible = "samsung,exynos5440-cpufreq";
  90                 reg = <0x160000 0x1000>;
  91                 interrupts = <0 57 0>;
  92                 operating-points = <
  93                                 /* KHz    uV */
  94                                 1500000 1100000
  95                                 1400000 1075000
  96                                 1300000 1050000
  97                                 1200000 1025000
  98                                 1100000 1000000
  99                                 1000000 975000
 100                                 900000  950000
 101                                 800000  925000
 102                 >;
 103         };
 104
 105         serial@B0000 {
 106                 compatible = "samsung,exynos4210-uart";
 107                 reg = <0xB0000 0x1000>;
 108                 interrupts = <0 2 0>;
 109                 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
 110                 clock-names = "uart", "clk_uart_baud0";
 111         };
 112
 113         serial@C0000 {
 114                 compatible = "samsung,exynos4210-uart";
 115                 reg = <0xC0000 0x1000>;
 116                 interrupts = <0 3 0>;
 117                 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
 118                 clock-names = "uart", "clk_uart_baud0";
 119         };
 120
 121         spi_0: spi@D0000 {
 122                 compatible = "samsung,exynos5440-spi";
 123                 reg = <0xD0000 0x100>;
 124                 interrupts = <0 4 0>;
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 samsung,spi-src-clk = <0>;
 128                 num-cs = <1>;
 129                 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
 130                 clock-names = "spi", "spi_busclk0";
 131         };
 132
 133         pin_ctrl: pinctrl {
 134                 compatible = "samsung,exynos5440-pinctrl";
 135                 reg = <0xE0000 0x1000>;
 136                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
 137                              <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
 138                 interrupt-controller;
 139                 #interrupt-cells = <2>;
 140                 #gpio-cells = <2>;
 141
 142                 fan: fan {
 143                         samsung,exynos5440-pin-function = <1>;
 144                 };
 145
 146                 hdd_led0: hdd_led0 {
 147                         samsung,exynos5440-pin-function = <2>;
 148                 };
 149
 150                 hdd_led1: hdd_led1 {
 151                         samsung,exynos5440-pin-function = <3>;
 152                 };
 153
 154                 uart1: uart1 {
 155                         samsung,exynos5440-pin-function = <4>;
 156                 };
 157         };
 158
 159         i2c@F0000 {
 160                 compatible = "samsung,exynos5440-i2c";
 161                 reg = <0xF0000 0x1000>;
 162                 interrupts = <0 5 0>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 clocks = <&clock CLK_B_125>;
 166                 clock-names = "i2c";
 167         };
 168
 169         i2c@100000 {
 170                 compatible = "samsung,exynos5440-i2c";
 171                 reg = <0x100000 0x1000>;
 172                 interrupts = <0 6 0>;
 173                 #address-cells = <1>;
 174                 #size-cells = <0>;
 175                 clocks = <&clock CLK_B_125>;
 176                 clock-names = "i2c";
 177         };
 178
 179         watchdog@110000 {
 180                 compatible = "samsung,s3c2410-wdt";
 181                 reg = <0x110000 0x1000>;
 182                 interrupts = <0 1 0>;
 183                 clocks = <&clock CLK_B_125>;
 184                 clock-names = "watchdog";
 185         };
 186
 187         gmac: ethernet@00230000 {
 188                 compatible = "snps,dwmac-3.70a";
 189                 reg = <0x00230000 0x8000>;
 190                 interrupt-parent = <&gic>;
 191                 interrupts = <0 31 4>;
 192                 interrupt-names = "macirq";
 193                 phy-mode = "sgmii";
 194                 clocks = <&clock CLK_GMAC0>;
 195                 clock-names = "stmmaceth";
 196         };
 197
 198         amba {
 199                 #address-cells = <1>;
 200                 #size-cells = <1>;
 201                 compatible = "arm,amba-bus";
 202                 interrupt-parent = <&gic>;
 203                 ranges;
 204         };
 205
 206         rtc {
 207                 compatible = "samsung,s3c6410-rtc";
 208                 reg = <0x130000 0x1000>;
 209                 interrupts = <0 17 0>, <0 16 0>;
 210                 clocks = <&clock CLK_B_125>;
 211                 clock-names = "rtc";
 212         };
 213
 214         tmuctrl_0: tmuctrl@160118 {
 215                 compatible = "samsung,exynos5440-tmu";
 216                 reg = <0x160118 0x230>, <0x160368 0x10>;
 217                 interrupts = <0 58 0>;
 218                 clocks = <&clock CLK_B_125>;
 219                 clock-names = "tmu_apbif";
 220         };
 221
 222         tmuctrl_1: tmuctrl@16011C {
 223                 compatible = "samsung,exynos5440-tmu";
 224                 reg = <0x16011C 0x230>, <0x160368 0x10>;
 225                 interrupts = <0 58 0>;
 226                 clocks = <&clock CLK_B_125>;
 227                 clock-names = "tmu_apbif";
 228         };
 229
 230         tmuctrl_2: tmuctrl@160120 {
 231                 compatible = "samsung,exynos5440-tmu";
 232                 reg = <0x160120 0x230>, <0x160368 0x10>;
 233                 interrupts = <0 58 0>;
 234                 clocks = <&clock CLK_B_125>;
 235                 clock-names = "tmu_apbif";
 236         };
 237
 238         sata@210000 {
 239                 compatible = "snps,exynos5440-ahci";
 240                 reg = <0x210000 0x10000>;
 241                 interrupts = <0 30 0>;
 242                 clocks = <&clock CLK_SATA>;
 243                 clock-names = "sata";
 244         };
 245
 246         ohci@220000 {
 247                 compatible = "samsung,exynos5440-ohci";
 248                 reg = <0x220000 0x1000>;
 249                 interrupts = <0 29 0>;
 250                 clocks = <&clock CLK_USB>;
 251                 clock-names = "usbhost";
 252         };
 253
 254         ehci@221000 {
 255                 compatible = "samsung,exynos5440-ehci";
 256                 reg = <0x221000 0x1000>;
 257                 interrupts = <0 29 0>;
 258                 clocks = <&clock CLK_USB>;
 259                 clock-names = "usbhost";
 260         };
 261
 262         pcie@290000 {
 263                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 264                 reg = <0x290000 0x1000
 265                         0x270000 0x1000
 266                         0x271000 0x40>;
 267                 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
 268                 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
 269                 clock-names = "pcie", "pcie_bus";
 270                 #address-cells = <3>;
 271                 #size-cells = <2>;
 272                 device_type = "pci";
 273                 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
 274                           0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
 275                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
 276                 #interrupt-cells = <1>;
 277                 interrupt-map-mask = <0 0 0 0>;
 278                 interrupt-map = <0x0 0 &gic 53>;
 279                 num-lanes = <4>;
 280                 status = "disabled";
 281         };
 282
 283         pcie@2a0000 {
 284                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 285                 reg = <0x2a0000 0x1000
 286                         0x272000 0x1000
 287                         0x271040 0x40>;
 288                 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
 289                 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
 290                 clock-names = "pcie", "pcie_bus";
 291                 #address-cells = <3>;
 292                 #size-cells = <2>;
 293                 device_type = "pci";
 294                 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
 295                           0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
 296                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
 297                 #interrupt-cells = <1>;
 298                 interrupt-map-mask = <0 0 0 0>;
 299                 interrupt-map = <0x0 0 &gic 56>;
 300                 num-lanes = <4>;
 301                 status = "disabled";
 302         };
 303 };