arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi

   1 /*
   2  * Hardkernel Odroid XU3 Audio Codec device tree source
   3  *
   4  * Copyright (c) 2015 Krzysztof Kozlowski
   5  * Copyright (c) 2014 Collabora Ltd.
   6  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   7  *              http://www.samsung.com
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <dt-bindings/sound/samsung-i2s.h>
  15
  16 / {
  17         sound: sound {
  18                 compatible = "simple-audio-card";
  19
  20                 simple-audio-card,name = "Odroid-XU3";
  21                 simple-audio-card,widgets =
  22                         "Headphone", "Headphone Jack",
  23                         "Speakers", "Speakers";
  24                 simple-audio-card,routing =
  25                         "Headphone Jack", "HPL",
  26                         "Headphone Jack", "HPR",
  27                         "Headphone Jack", "MICBIAS",
  28                         "IN1", "Headphone Jack",
  29                         "Speakers", "SPKL",
  30                         "Speakers", "SPKR";
  31
  32                 simple-audio-card,format = "i2s";
  33                 simple-audio-card,bitclock-master = <&link0_codec>;
  34                 simple-audio-card,frame-master = <&link0_codec>;
  35
  36                 simple-audio-card,cpu {
  37                         sound-dai = <&i2s0 0>;
  38                         system-clock-frequency = <19200000>;
  39                 };
  40
  41                 link0_codec: simple-audio-card,codec {
  42                         sound-dai = <&max98090>;
  43                         clocks = <&i2s0 CLK_I2S_CDCLK>;
  44                 };
  45         };
  46 };
  47
  48 &clock_audss {
  49         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
  50                         <&clock_audss EXYNOS_MOUT_I2S>,
  51                         <&clock_audss EXYNOS_DOUT_AUD_BUS>;
  52         assigned-clock-parents = <&clock CLK_FIN_PLL>,
  53                         <&clock_audss EXYNOS_MOUT_AUDSS>;
  54         assigned-clock-rates = <0>,
  55                         <0>,
  56                         <19200000>;
  57 };
  58
  59 &hsi2c_5 {
  60         status = "okay";
  61         max98090: max98090@10 {
  62                 compatible = "maxim,max98090";
  63                 reg = <0x10>;
  64                 interrupt-parent = <&gpx3>;
  65                 interrupts = <2 IRQ_TYPE_NONE>;
  66                 clocks = <&i2s0 CLK_I2S_CDCLK>;
  67                 clock-names = "mclk";
  68                 #sound-dai-cells = <0>;
  69         };
  70 };
  71
  72 &i2s0 {
  73         status = "okay";
  74 };