arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hardkernel Odroid XU3 audio subsystem device tree source
   4  *
   5  * Copyright (c) 2015 Krzysztof Kozlowski
   6  * Copyright (c) 2014 Collabora Ltd.
   7  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   8  *              http://www.samsung.com
   9  */
  10
  11 #include <dt-bindings/sound/samsung-i2s.h>
  12
  13 / {
  14         sound: sound {
  15                 compatible = "samsung,odroid-xu3-audio";
  16                 model = "Odroid-XU3";
  17
  18                 samsung,audio-widgets =
  19                         "Headphone", "Headphone Jack",
  20                         "Speakers", "Speakers";
  21                 samsung,audio-routing =
  22                         "Headphone Jack", "HPL",
  23                         "Headphone Jack", "HPR",
  24                         "Headphone Jack", "MICBIAS",
  25                         "IN1", "Headphone Jack",
  26                         "Speakers", "SPKL",
  27                         "Speakers", "SPKR";
  28
  29                 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
  30                                 <&clock CLK_MOUT_EPLL>,
  31                                 <&clock CLK_MOUT_MAU_EPLL>,
  32                                 <&clock CLK_MOUT_USER_MAU_EPLL>,
  33                                 <&clock_audss EXYNOS_MOUT_AUDSS>,
  34                                 <&clock_audss EXYNOS_MOUT_I2S>,
  35                                 <&clock_audss EXYNOS_DOUT_SRP>,
  36                                 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
  37                                 <&clock_audss EXYNOS_DOUT_I2S>;
  38
  39                 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
  40                                 <&clock CLK_FOUT_EPLL>,
  41                                 <&clock CLK_MOUT_EPLL>,
  42                                 <&clock CLK_MOUT_MAU_EPLL>,
  43                                 <&clock CLK_MAU_EPLL>,
  44                                 <&clock_audss EXYNOS_MOUT_AUDSS>;
  45
  46                 assigned-clock-rates = <0>,
  47                                 <0>,
  48                                 <0>,
  49                                 <0>,
  50                                 <0>,
  51                                 <0>,
  52                                 <196608001>,
  53                                 <(196608002 / 2)>,
  54                                 <196608000>;
  55
  56                 cpu {
  57                         sound-dai = <&i2s0 0>;
  58                 };
  59                 codec {
  60                         sound-dai = <&hdmi>, <&max98090>;
  61                 };
  62         };
  63 };
  64
  65 &clock_audss {
  66         assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
  67                           <&clock CLK_FOUT_EPLL>;
  68         assigned-clock-rates = <(196608000 / 256)>,
  69                                <196608000>;
  70 };
  71
  72 &hsi2c_5 {
  73         status = "okay";
  74         max98090: max98090@10 {
  75                 compatible = "maxim,max98090";
  76                 reg = <0x10>;
  77                 interrupt-parent = <&gpx3>;
  78                 interrupts = <2 IRQ_TYPE_NONE>;
  79                 clocks = <&i2s0 CLK_I2S_CDCLK>;
  80                 clock-names = "mclk";
  81                 #sound-dai-cells = <0>;
  82         };
  83 };
  84
  85 &i2s0 {
  86         status = "okay";
  87 };