arch/arm/boot/dts/exynos5422-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5422 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
   8  *
   9  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  10  * but particular boards choose different booting order.
  11  *
  12  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  13  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  14  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  15  * from the LITTLE: Cortex-A7.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@100 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x100>;
  31                         clocks = <&clock CLK_KFC_CLK>;
  32                         clock-frequency = <1000000000>;
  33                         cci-control-port = <&cci_control0>;
  34                         operating-points-v2 = <&cluster_a7_opp_table>;
  35                         cooling-min-level = <0>;
  36                         cooling-max-level = <11>;
  37                         #cooling-cells = <2>; /* min followed by max */
  38                         capacity-dmips-mhz = <539>;
  39                 };
  40
  41                 cpu1: cpu@101 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0x101>;
  45                         clock-frequency = <1000000000>;
  46                         cci-control-port = <&cci_control0>;
  47                         operating-points-v2 = <&cluster_a7_opp_table>;
  48                         cooling-min-level = <0>;
  49                         cooling-max-level = <11>;
  50                         #cooling-cells = <2>; /* min followed by max */
  51                         capacity-dmips-mhz = <539>;
  52                 };
  53
  54                 cpu2: cpu@102 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0x102>;
  58                         clock-frequency = <1000000000>;
  59                         cci-control-port = <&cci_control0>;
  60                         operating-points-v2 = <&cluster_a7_opp_table>;
  61                         cooling-min-level = <0>;
  62                         cooling-max-level = <11>;
  63                         #cooling-cells = <2>; /* min followed by max */
  64                         capacity-dmips-mhz = <539>;
  65                 };
  66
  67                 cpu3: cpu@103 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a7";
  70                         reg = <0x103>;
  71                         clock-frequency = <1000000000>;
  72                         cci-control-port = <&cci_control0>;
  73                         operating-points-v2 = <&cluster_a7_opp_table>;
  74                         cooling-min-level = <0>;
  75                         cooling-max-level = <11>;
  76                         #cooling-cells = <2>; /* min followed by max */
  77                         capacity-dmips-mhz = <539>;
  78                 };
  79
  80                 cpu4: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a15";
  83                         clocks = <&clock CLK_ARM_CLK>;
  84                         reg = <0x0>;
  85                         clock-frequency = <1800000000>;
  86                         cci-control-port = <&cci_control1>;
  87                         operating-points-v2 = <&cluster_a15_opp_table>;
  88                         cooling-min-level = <0>;
  89                         cooling-max-level = <15>;
  90                         #cooling-cells = <2>; /* min followed by max */
  91                         capacity-dmips-mhz = <1024>;
  92                 };
  93
  94                 cpu5: cpu@1 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a15";
  97                         reg = <0x1>;
  98                         clock-frequency = <1800000000>;
  99                         cci-control-port = <&cci_control1>;
 100                         operating-points-v2 = <&cluster_a15_opp_table>;
 101                         cooling-min-level = <0>;
 102                         cooling-max-level = <15>;
 103                         #cooling-cells = <2>; /* min followed by max */
 104                         capacity-dmips-mhz = <1024>;
 105                 };
 106
 107                 cpu6: cpu@2 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a15";
 110                         reg = <0x2>;
 111                         clock-frequency = <1800000000>;
 112                         cci-control-port = <&cci_control1>;
 113                         operating-points-v2 = <&cluster_a15_opp_table>;
 114                         cooling-min-level = <0>;
 115                         cooling-max-level = <15>;
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         capacity-dmips-mhz = <1024>;
 118                 };
 119
 120                 cpu7: cpu@3 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a15";
 123                         reg = <0x3>;
 124                         clock-frequency = <1800000000>;
 125                         cci-control-port = <&cci_control1>;
 126                         operating-points-v2 = <&cluster_a15_opp_table>;
 127                         cooling-min-level = <0>;
 128                         cooling-max-level = <15>;
 129                         #cooling-cells = <2>; /* min followed by max */
 130                         capacity-dmips-mhz = <1024>;
 131                 };
 132         };
 133 };