arch/arm/boot/dts/exynos5422-cpus.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5422 SoC cpu device tree source
   4  *
   5  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
   9  *
  10  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  11  * but particular boards choose different booting order.
  12  *
  13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  14  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  16  * from the LITTLE: Cortex-A7.
  17  */
  18
  19 / {
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@100 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a7";
  27                         reg = <0x100>;
  28                         clocks = <&clock CLK_KFC_CLK>;
  29                         clock-frequency = <1000000000>;
  30                         cci-control-port = <&cci_control0>;
  31                         operating-points-v2 = <&cluster_a7_opp_table>;
  32                         cooling-min-level = <0>;
  33                         cooling-max-level = <11>;
  34                         #cooling-cells = <2>; /* min followed by max */
  35                         capacity-dmips-mhz = <539>;
  36                 };
  37
  38                 cpu1: cpu@101 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0x101>;
  42                         clock-frequency = <1000000000>;
  43                         cci-control-port = <&cci_control0>;
  44                         operating-points-v2 = <&cluster_a7_opp_table>;
  45                         cooling-min-level = <0>;
  46                         cooling-max-level = <11>;
  47                         #cooling-cells = <2>; /* min followed by max */
  48                         capacity-dmips-mhz = <539>;
  49                 };
  50
  51                 cpu2: cpu@102 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54                         reg = <0x102>;
  55                         clock-frequency = <1000000000>;
  56                         cci-control-port = <&cci_control0>;
  57                         operating-points-v2 = <&cluster_a7_opp_table>;
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <11>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                         capacity-dmips-mhz = <539>;
  62                 };
  63
  64                 cpu3: cpu@103 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0x103>;
  68                         clock-frequency = <1000000000>;
  69                         cci-control-port = <&cci_control0>;
  70                         operating-points-v2 = <&cluster_a7_opp_table>;
  71                         cooling-min-level = <0>;
  72                         cooling-max-level = <11>;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         capacity-dmips-mhz = <539>;
  75                 };
  76
  77                 cpu4: cpu@0 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a15";
  80                         clocks = <&clock CLK_ARM_CLK>;
  81                         reg = <0x0>;
  82                         clock-frequency = <1800000000>;
  83                         cci-control-port = <&cci_control1>;
  84                         operating-points-v2 = <&cluster_a15_opp_table>;
  85                         cooling-min-level = <0>;
  86                         cooling-max-level = <15>;
  87                         #cooling-cells = <2>; /* min followed by max */
  88                         capacity-dmips-mhz = <1024>;
  89                 };
  90
  91                 cpu5: cpu@1 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a15";
  94                         reg = <0x1>;
  95                         clock-frequency = <1800000000>;
  96                         cci-control-port = <&cci_control1>;
  97                         operating-points-v2 = <&cluster_a15_opp_table>;
  98                         cooling-min-level = <0>;
  99                         cooling-max-level = <15>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         capacity-dmips-mhz = <1024>;
 102                 };
 103
 104                 cpu6: cpu@2 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a15";
 107                         reg = <0x2>;
 108                         clock-frequency = <1800000000>;
 109                         cci-control-port = <&cci_control1>;
 110                         operating-points-v2 = <&cluster_a15_opp_table>;
 111                         cooling-min-level = <0>;
 112                         cooling-max-level = <15>;
 113                         #cooling-cells = <2>; /* min followed by max */
 114                         capacity-dmips-mhz = <1024>;
 115                 };
 116
 117                 cpu7: cpu@3 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a15";
 120                         reg = <0x3>;
 121                         clock-frequency = <1800000000>;
 122                         cci-control-port = <&cci_control1>;
 123                         operating-points-v2 = <&cluster_a15_opp_table>;
 124                         cooling-min-level = <0>;
 125                         cooling-max-level = <15>;
 126                         #cooling-cells = <2>; /* min followed by max */
 127                         capacity-dmips-mhz = <1024>;
 128                 };
 129         };
 130 };
 131
 132 &arm_a7_pmu {
 133         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 134         status = "okay";
 135 };
 136
 137 &arm_a15_pmu {
 138         interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 139         status = "okay";
 140 };