arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49                 usbdrdphy0 = &usbdrd_phy0;
  50                 usbdrdphy1 = &usbdrd_phy1;
  51         };
  52
  53         cluster_a15_opp_table: opp_table0 {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56                 opp@1800000000 {
  57                         opp-hz = /bits/ 64 <1800000000>;
  58                         opp-microvolt = <1250000>;
  59                         clock-latency-ns = <140000>;
  60                 };
  61                 opp@1700000000 {
  62                         opp-hz = /bits/ 64 <1700000000>;
  63                         opp-microvolt = <1212500>;
  64                         clock-latency-ns = <140000>;
  65                 };
  66                 opp@1600000000 {
  67                         opp-hz = /bits/ 64 <1600000000>;
  68                         opp-microvolt = <1175000>;
  69                         clock-latency-ns = <140000>;
  70                 };
  71                 opp@1500000000 {
  72                         opp-hz = /bits/ 64 <1500000000>;
  73                         opp-microvolt = <1137500>;
  74                         clock-latency-ns = <140000>;
  75                 };
  76                 opp@1400000000 {
  77                         opp-hz = /bits/ 64 <1400000000>;
  78                         opp-microvolt = <1112500>;
  79                         clock-latency-ns = <140000>;
  80                 };
  81                 opp@1300000000 {
  82                         opp-hz = /bits/ 64 <1300000000>;
  83                         opp-microvolt = <1062500>;
  84                         clock-latency-ns = <140000>;
  85                 };
  86                 opp@1200000000 {
  87                         opp-hz = /bits/ 64 <1200000000>;
  88                         opp-microvolt = <1037500>;
  89                         clock-latency-ns = <140000>;
  90                 };
  91                 opp@1100000000 {
  92                         opp-hz = /bits/ 64 <1100000000>;
  93                         opp-microvolt = <1012500>;
  94                         clock-latency-ns = <140000>;
  95                 };
  96                 opp@1000000000 {
  97                         opp-hz = /bits/ 64 <1000000000>;
  98                         opp-microvolt = < 987500>;
  99                         clock-latency-ns = <140000>;
 100                 };
 101                 opp@900000000 {
 102                         opp-hz = /bits/ 64 <900000000>;
 103                         opp-microvolt = < 962500>;
 104                         clock-latency-ns = <140000>;
 105                 };
 106                 opp@800000000 {
 107                         opp-hz = /bits/ 64 <800000000>;
 108                         opp-microvolt = < 937500>;
 109                         clock-latency-ns = <140000>;
 110                 };
 111                 opp@700000000 {
 112                         opp-hz = /bits/ 64 <700000000>;
 113                         opp-microvolt = < 912500>;
 114                         clock-latency-ns = <140000>;
 115                 };
 116         };
 117
 118         cluster_a7_opp_table: opp_table1 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121                 opp@1300000000 {
 122                         opp-hz = /bits/ 64 <1300000000>;
 123                         opp-microvolt = <1275000>;
 124                         clock-latency-ns = <140000>;
 125                 };
 126                 opp@1200000000 {
 127                         opp-hz = /bits/ 64 <1200000000>;
 128                         opp-microvolt = <1212500>;
 129                         clock-latency-ns = <140000>;
 130                 };
 131                 opp@1100000000 {
 132                         opp-hz = /bits/ 64 <1100000000>;
 133                         opp-microvolt = <1162500>;
 134                         clock-latency-ns = <140000>;
 135                 };
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         opp-microvolt = <1112500>;
 139                         clock-latency-ns = <140000>;
 140                 };
 141                 opp@900000000 {
 142                         opp-hz = /bits/ 64 <900000000>;
 143                         opp-microvolt = <1062500>;
 144                         clock-latency-ns = <140000>;
 145                 };
 146                 opp@800000000 {
 147                         opp-hz = /bits/ 64 <800000000>;
 148                         opp-microvolt = <1025000>;
 149                         clock-latency-ns = <140000>;
 150                 };
 151                 opp@700000000 {
 152                         opp-hz = /bits/ 64 <700000000>;
 153                         opp-microvolt = <975000>;
 154                         clock-latency-ns = <140000>;
 155                 };
 156                 opp@600000000 {
 157                         opp-hz = /bits/ 64 <600000000>;
 158                         opp-microvolt = <937500>;
 159                         clock-latency-ns = <140000>;
 160                 };
 161         };
 162
 163         /*
 164          * The 'cpus' node is not present here but instead it is provided
 165          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 166          */
 167
 168         cci: cci@10d20000 {
 169                 compatible = "arm,cci-400";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 reg = <0x10d20000 0x1000>;
 173                 ranges = <0x0 0x10d20000 0x6000>;
 174
 175                 cci_control0: slave-if@4000 {
 176                         compatible = "arm,cci-400-ctrl-if";
 177                         interface-type = "ace";
 178                         reg = <0x4000 0x1000>;
 179                 };
 180                 cci_control1: slave-if@5000 {
 181                         compatible = "arm,cci-400-ctrl-if";
 182                         interface-type = "ace";
 183                         reg = <0x5000 0x1000>;
 184                 };
 185         };
 186
 187         sysram@02020000 {
 188                 compatible = "mmio-sram";
 189                 reg = <0x02020000 0x54000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges = <0 0x02020000 0x54000>;
 193
 194                 smp-sysram@0 {
 195                         compatible = "samsung,exynos4210-sysram";
 196                         reg = <0x0 0x1000>;
 197                 };
 198
 199                 smp-sysram@53000 {
 200                         compatible = "samsung,exynos4210-sysram-ns";
 201                         reg = <0x53000 0x1000>;
 202                 };
 203         };
 204
 205         clock: clock-controller@10010000 {
 206                 compatible = "samsung,exynos5420-clock";
 207                 reg = <0x10010000 0x30000>;
 208                 #clock-cells = <1>;
 209         };
 210
 211         clock_audss: audss-clock-controller@3810000 {
 212                 compatible = "samsung,exynos5420-audss-clock";
 213                 reg = <0x03810000 0x0C>;
 214                 #clock-cells = <1>;
 215                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 216                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 217                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 218         };
 219
 220         mfc: codec@11000000 {
 221                 compatible = "samsung,mfc-v7";
 222                 reg = <0x11000000 0x10000>;
 223                 interrupts = <0 96 0>;
 224                 clocks = <&clock CLK_MFC>;
 225                 clock-names = "mfc";
 226                 power-domains = <&mfc_pd>;
 227                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 228                 iommu-names = "left", "right";
 229         };
 230
 231         mmc_0: mmc@12200000 {
 232                 compatible = "samsung,exynos5420-dw-mshc-smu";
 233                 interrupts = <0 75 0>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x12200000 0x2000>;
 237                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 238                 clock-names = "biu", "ciu";
 239                 fifo-depth = <0x40>;
 240                 status = "disabled";
 241         };
 242
 243         mmc_1: mmc@12210000 {
 244                 compatible = "samsung,exynos5420-dw-mshc-smu";
 245                 interrupts = <0 76 0>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 reg = <0x12210000 0x2000>;
 249                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 250                 clock-names = "biu", "ciu";
 251                 fifo-depth = <0x40>;
 252                 status = "disabled";
 253         };
 254
 255         mmc_2: mmc@12220000 {
 256                 compatible = "samsung,exynos5420-dw-mshc";
 257                 interrupts = <0 77 0>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 reg = <0x12220000 0x1000>;
 261                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 262                 clock-names = "biu", "ciu";
 263                 fifo-depth = <0x40>;
 264                 status = "disabled";
 265         };
 266
 267         mct: mct@101C0000 {
 268                 compatible = "samsung,exynos4210-mct";
 269                 reg = <0x101C0000 0x800>;
 270                 interrupt-controller;
 271                 #interrupt-cells = <1>;
 272                 interrupt-parent = <&mct_map>;
 273                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 274                                 <8>, <9>, <10>, <11>;
 275                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 276                 clock-names = "fin_pll", "mct";
 277
 278                 mct_map: mct-map {
 279                         #interrupt-cells = <1>;
 280                         #address-cells = <0>;
 281                         #size-cells = <0>;
 282                         interrupt-map = <0 &combiner 23 3>,
 283                                         <1 &combiner 23 4>,
 284                                         <2 &combiner 25 2>,
 285                                         <3 &combiner 25 3>,
 286                                         <4 &gic 0 120 0>,
 287                                         <5 &gic 0 121 0>,
 288                                         <6 &gic 0 122 0>,
 289                                         <7 &gic 0 123 0>,
 290                                         <8 &gic 0 128 0>,
 291                                         <9 &gic 0 129 0>,
 292                                         <10 &gic 0 130 0>,
 293                                         <11 &gic 0 131 0>;
 294                 };
 295         };
 296
 297         nocp_mem0_0: nocp@10CA1000 {
 298                 compatible = "samsung,exynos5420-nocp";
 299                 reg = <0x10CA1000 0x200>;
 300                 status = "disabled";
 301         };
 302
 303         nocp_mem0_1: nocp@10CA1400 {
 304                 compatible = "samsung,exynos5420-nocp";
 305                 reg = <0x10CA1400 0x200>;
 306                 status = "disabled";
 307         };
 308
 309         nocp_mem1_0: nocp@10CA1800 {
 310                 compatible = "samsung,exynos5420-nocp";
 311                 reg = <0x10CA1800 0x200>;
 312                 status = "disabled";
 313         };
 314
 315         nocp_mem1_1: nocp@10CA1C00 {
 316                 compatible = "samsung,exynos5420-nocp";
 317                 reg = <0x10CA1C00 0x200>;
 318                 status = "disabled";
 319         };
 320
 321         nocp_g3d_0: nocp@11A51000 {
 322                 compatible = "samsung,exynos5420-nocp";
 323                 reg = <0x11A51000 0x200>;
 324                 status = "disabled";
 325         };
 326
 327         nocp_g3d_1: nocp@11A51400 {
 328                 compatible = "samsung,exynos5420-nocp";
 329                 reg = <0x11A51400 0x200>;
 330                 status = "disabled";
 331         };
 332
 333         gsc_pd: power-domain@10044000 {
 334                 compatible = "samsung,exynos4210-pd";
 335                 reg = <0x10044000 0x20>;
 336                 #power-domain-cells = <0>;
 337                 clocks = <&clock CLK_FIN_PLL>,
 338                          <&clock CLK_MOUT_USER_ACLK300_GSCL>,
 339                          <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 340                 clock-names = "oscclk", "clk0", "asb0", "asb1";
 341         };
 342
 343         isp_pd: power-domain@10044020 {
 344                 compatible = "samsung,exynos4210-pd";
 345                 reg = <0x10044020 0x20>;
 346                 #power-domain-cells = <0>;
 347         };
 348
 349         mfc_pd: power-domain@10044060 {
 350                 compatible = "samsung,exynos4210-pd";
 351                 reg = <0x10044060 0x20>;
 352                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 353                 clock-names = "oscclk", "clk0";
 354                 #power-domain-cells = <0>;
 355         };
 356
 357         msc_pd: power-domain@10044120 {
 358                 compatible = "samsung,exynos4210-pd";
 359                 reg = <0x10044120 0x20>;
 360                 #power-domain-cells = <0>;
 361         };
 362
 363         disp_pd: power-domain@100440C0 {
 364                 compatible = "samsung,exynos4210-pd";
 365                 reg = <0x100440C0 0x20>;
 366                 #power-domain-cells = <0>;
 367                 clocks = <&clock CLK_FIN_PLL>,
 368                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 369                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 370                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 371                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 372                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 373         };
 374
 375         pinctrl_0: pinctrl@13400000 {
 376                 compatible = "samsung,exynos5420-pinctrl";
 377                 reg = <0x13400000 0x1000>;
 378                 interrupts = <0 45 0>;
 379
 380                 wakeup-interrupt-controller {
 381                         compatible = "samsung,exynos4210-wakeup-eint";
 382                         interrupt-parent = <&gic>;
 383                         interrupts = <0 32 0>;
 384                 };
 385         };
 386
 387         pinctrl_1: pinctrl@13410000 {
 388                 compatible = "samsung,exynos5420-pinctrl";
 389                 reg = <0x13410000 0x1000>;
 390                 interrupts = <0 78 0>;
 391         };
 392
 393         pinctrl_2: pinctrl@14000000 {
 394                 compatible = "samsung,exynos5420-pinctrl";
 395                 reg = <0x14000000 0x1000>;
 396                 interrupts = <0 46 0>;
 397         };
 398
 399         pinctrl_3: pinctrl@14010000 {
 400                 compatible = "samsung,exynos5420-pinctrl";
 401                 reg = <0x14010000 0x1000>;
 402                 interrupts = <0 50 0>;
 403         };
 404
 405         pinctrl_4: pinctrl@03860000 {
 406                 compatible = "samsung,exynos5420-pinctrl";
 407                 reg = <0x03860000 0x1000>;
 408                 interrupts = <0 47 0>;
 409         };
 410
 411         amba {
 412                 #address-cells = <1>;
 413                 #size-cells = <1>;
 414                 compatible = "simple-bus";
 415                 interrupt-parent = <&gic>;
 416                 ranges;
 417
 418                 adma: adma@03880000 {
 419                         compatible = "arm,pl330", "arm,primecell";
 420                         reg = <0x03880000 0x1000>;
 421                         interrupts = <0 110 0>;
 422                         clocks = <&clock_audss EXYNOS_ADMA>;
 423                         clock-names = "apb_pclk";
 424                         #dma-cells = <1>;
 425                         #dma-channels = <6>;
 426                         #dma-requests = <16>;
 427                 };
 428
 429                 pdma0: pdma@121A0000 {
 430                         compatible = "arm,pl330", "arm,primecell";
 431                         reg = <0x121A0000 0x1000>;
 432                         interrupts = <0 34 0>;
 433                         clocks = <&clock CLK_PDMA0>;
 434                         clock-names = "apb_pclk";
 435                         #dma-cells = <1>;
 436                         #dma-channels = <8>;
 437                         #dma-requests = <32>;
 438                 };
 439
 440                 pdma1: pdma@121B0000 {
 441                         compatible = "arm,pl330", "arm,primecell";
 442                         reg = <0x121B0000 0x1000>;
 443                         interrupts = <0 35 0>;
 444                         clocks = <&clock CLK_PDMA1>;
 445                         clock-names = "apb_pclk";
 446                         #dma-cells = <1>;
 447                         #dma-channels = <8>;
 448                         #dma-requests = <32>;
 449                 };
 450
 451                 mdma0: mdma@10800000 {
 452                         compatible = "arm,pl330", "arm,primecell";
 453                         reg = <0x10800000 0x1000>;
 454                         interrupts = <0 33 0>;
 455                         clocks = <&clock CLK_MDMA0>;
 456                         clock-names = "apb_pclk";
 457                         #dma-cells = <1>;
 458                         #dma-channels = <8>;
 459                         #dma-requests = <1>;
 460                 };
 461
 462                 mdma1: mdma@11C10000 {
 463                         compatible = "arm,pl330", "arm,primecell";
 464                         reg = <0x11C10000 0x1000>;
 465                         interrupts = <0 124 0>;
 466                         clocks = <&clock CLK_MDMA1>;
 467                         clock-names = "apb_pclk";
 468                         #dma-cells = <1>;
 469                         #dma-channels = <8>;
 470                         #dma-requests = <1>;
 471                         /*
 472                          * MDMA1 can support both secure and non-secure
 473                          * AXI transactions. When this is enabled in the kernel
 474                          * for boards that run in secure mode, we are getting
 475                          * imprecise external aborts causing the kernel to oops.
 476                          */
 477                         status = "disabled";
 478                 };
 479         };
 480
 481         i2s0: i2s@03830000 {
 482                 compatible = "samsung,exynos5420-i2s";
 483                 reg = <0x03830000 0x100>;
 484                 dmas = <&adma 0
 485                         &adma 2
 486                         &adma 1>;
 487                 dma-names = "tx", "rx", "tx-sec";
 488                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 489                         <&clock_audss EXYNOS_I2S_BUS>,
 490                         <&clock_audss EXYNOS_SCLK_I2S>;
 491                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 492                 #clock-cells = <1>;
 493                 clock-output-names = "i2s_cdclk0";
 494                 #sound-dai-cells = <1>;
 495                 samsung,idma-addr = <0x03000000>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&i2s0_bus>;
 498                 status = "disabled";
 499         };
 500
 501         i2s1: i2s@12D60000 {
 502                 compatible = "samsung,exynos5420-i2s";
 503                 reg = <0x12D60000 0x100>;
 504                 dmas = <&pdma1 12
 505                         &pdma1 11>;
 506                 dma-names = "tx", "rx";
 507                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 508                 clock-names = "iis", "i2s_opclk0";
 509                 #clock-cells = <1>;
 510                 clock-output-names = "i2s_cdclk1";
 511                 #sound-dai-cells = <1>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2s1_bus>;
 514                 status = "disabled";
 515         };
 516
 517         i2s2: i2s@12D70000 {
 518                 compatible = "samsung,exynos5420-i2s";
 519                 reg = <0x12D70000 0x100>;
 520                 dmas = <&pdma0 12
 521                         &pdma0 11>;
 522                 dma-names = "tx", "rx";
 523                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 524                 clock-names = "iis", "i2s_opclk0";
 525                 #clock-cells = <1>;
 526                 clock-output-names = "i2s_cdclk2";
 527                 #sound-dai-cells = <1>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&i2s2_bus>;
 530                 status = "disabled";
 531         };
 532
 533         spi_0: spi@12d20000 {
 534                 compatible = "samsung,exynos4210-spi";
 535                 reg = <0x12d20000 0x100>;
 536                 interrupts = <0 68 0>;
 537                 dmas = <&pdma0 5
 538                         &pdma0 4>;
 539                 dma-names = "tx", "rx";
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&spi0_bus>;
 544                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 545                 clock-names = "spi", "spi_busclk0";
 546                 status = "disabled";
 547         };
 548
 549         spi_1: spi@12d30000 {
 550                 compatible = "samsung,exynos4210-spi";
 551                 reg = <0x12d30000 0x100>;
 552                 interrupts = <0 69 0>;
 553                 dmas = <&pdma1 5
 554                         &pdma1 4>;
 555                 dma-names = "tx", "rx";
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&spi1_bus>;
 560                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 561                 clock-names = "spi", "spi_busclk0";
 562                 status = "disabled";
 563         };
 564
 565         spi_2: spi@12d40000 {
 566                 compatible = "samsung,exynos4210-spi";
 567                 reg = <0x12d40000 0x100>;
 568                 interrupts = <0 70 0>;
 569                 dmas = <&pdma0 7
 570                         &pdma0 6>;
 571                 dma-names = "tx", "rx";
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&spi2_bus>;
 576                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 577                 clock-names = "spi", "spi_busclk0";
 578                 status = "disabled";
 579         };
 580
 581         pwm: pwm@12dd0000 {
 582                 compatible = "samsung,exynos4210-pwm";
 583                 reg = <0x12dd0000 0x100>;
 584                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 585                 #pwm-cells = <3>;
 586                 clocks = <&clock CLK_PWM>;
 587                 clock-names = "timers";
 588         };
 589
 590         dp_phy: dp-video-phy {
 591                 compatible = "samsung,exynos5420-dp-video-phy";
 592                 samsung,pmu-syscon = <&pmu_system_controller>;
 593                 #phy-cells = <0>;
 594         };
 595
 596         mipi_phy: mipi-video-phy {
 597                 compatible = "samsung,s5pv210-mipi-video-phy";
 598                 syscon = <&pmu_system_controller>;
 599                 #phy-cells = <1>;
 600         };
 601
 602         dsi@14500000 {
 603                 compatible = "samsung,exynos5410-mipi-dsi";
 604                 reg = <0x14500000 0x10000>;
 605                 interrupts = <0 82 0>;
 606                 phys = <&mipi_phy 1>;
 607                 phy-names = "dsim";
 608                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 609                 clock-names = "bus_clk", "pll_clk";
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 status = "disabled";
 613         };
 614
 615         adc: adc@12D10000 {
 616                 compatible = "samsung,exynos-adc-v2";
 617                 reg = <0x12D10000 0x100>;
 618                 interrupts = <0 106 0>;
 619                 clocks = <&clock CLK_TSADC>;
 620                 clock-names = "adc";
 621                 #io-channel-cells = <1>;
 622                 io-channel-ranges;
 623                 samsung,syscon-phandle = <&pmu_system_controller>;
 624                 status = "disabled";
 625         };
 626
 627         i2c_0: i2c@12C60000 {
 628                 compatible = "samsung,s3c2440-i2c";
 629                 reg = <0x12C60000 0x100>;
 630                 interrupts = <0 56 0>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 clocks = <&clock CLK_I2C0>;
 634                 clock-names = "i2c";
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&i2c0_bus>;
 637                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 638                 status = "disabled";
 639         };
 640
 641         i2c_1: i2c@12C70000 {
 642                 compatible = "samsung,s3c2440-i2c";
 643                 reg = <0x12C70000 0x100>;
 644                 interrupts = <0 57 0>;
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 clocks = <&clock CLK_I2C1>;
 648                 clock-names = "i2c";
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&i2c1_bus>;
 651                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 652                 status = "disabled";
 653         };
 654
 655         i2c_2: i2c@12C80000 {
 656                 compatible = "samsung,s3c2440-i2c";
 657                 reg = <0x12C80000 0x100>;
 658                 interrupts = <0 58 0>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 clocks = <&clock CLK_I2C2>;
 662                 clock-names = "i2c";
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&i2c2_bus>;
 665                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 666                 status = "disabled";
 667         };
 668
 669         i2c_3: i2c@12C90000 {
 670                 compatible = "samsung,s3c2440-i2c";
 671                 reg = <0x12C90000 0x100>;
 672                 interrupts = <0 59 0>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 clocks = <&clock CLK_I2C3>;
 676                 clock-names = "i2c";
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&i2c3_bus>;
 679                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 680                 status = "disabled";
 681         };
 682
 683         hsi2c_4: i2c@12CA0000 {
 684                 compatible = "samsung,exynos5-hsi2c";
 685                 reg = <0x12CA0000 0x1000>;
 686                 interrupts = <0 60 0>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&i2c4_hs_bus>;
 691                 clocks = <&clock CLK_USI0>;
 692                 clock-names = "hsi2c";
 693                 status = "disabled";
 694         };
 695
 696         hsi2c_5: i2c@12CB0000 {
 697                 compatible = "samsung,exynos5-hsi2c";
 698                 reg = <0x12CB0000 0x1000>;
 699                 interrupts = <0 61 0>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&i2c5_hs_bus>;
 704                 clocks = <&clock CLK_USI1>;
 705                 clock-names = "hsi2c";
 706                 status = "disabled";
 707         };
 708
 709         hsi2c_6: i2c@12CC0000 {
 710                 compatible = "samsung,exynos5-hsi2c";
 711                 reg = <0x12CC0000 0x1000>;
 712                 interrupts = <0 62 0>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&i2c6_hs_bus>;
 717                 clocks = <&clock CLK_USI2>;
 718                 clock-names = "hsi2c";
 719                 status = "disabled";
 720         };
 721
 722         hsi2c_7: i2c@12CD0000 {
 723                 compatible = "samsung,exynos5-hsi2c";
 724                 reg = <0x12CD0000 0x1000>;
 725                 interrupts = <0 63 0>;
 726                 #address-cells = <1>;
 727                 #size-cells = <0>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&i2c7_hs_bus>;
 730                 clocks = <&clock CLK_USI3>;
 731                 clock-names = "hsi2c";
 732                 status = "disabled";
 733         };
 734
 735         hsi2c_8: i2c@12E00000 {
 736                 compatible = "samsung,exynos5-hsi2c";
 737                 reg = <0x12E00000 0x1000>;
 738                 interrupts = <0 87 0>;
 739                 #address-cells = <1>;
 740                 #size-cells = <0>;
 741                 pinctrl-names = "default";
 742                 pinctrl-0 = <&i2c8_hs_bus>;
 743                 clocks = <&clock CLK_USI4>;
 744                 clock-names = "hsi2c";
 745                 status = "disabled";
 746         };
 747
 748         hsi2c_9: i2c@12E10000 {
 749                 compatible = "samsung,exynos5-hsi2c";
 750                 reg = <0x12E10000 0x1000>;
 751                 interrupts = <0 88 0>;
 752                 #address-cells = <1>;
 753                 #size-cells = <0>;
 754                 pinctrl-names = "default";
 755                 pinctrl-0 = <&i2c9_hs_bus>;
 756                 clocks = <&clock CLK_USI5>;
 757                 clock-names = "hsi2c";
 758                 status = "disabled";
 759         };
 760
 761         hsi2c_10: i2c@12E20000 {
 762                 compatible = "samsung,exynos5-hsi2c";
 763                 reg = <0x12E20000 0x1000>;
 764                 interrupts = <0 203 0>;
 765                 #address-cells = <1>;
 766                 #size-cells = <0>;
 767                 pinctrl-names = "default";
 768                 pinctrl-0 = <&i2c10_hs_bus>;
 769                 clocks = <&clock CLK_USI6>;
 770                 clock-names = "hsi2c";
 771                 status = "disabled";
 772         };
 773
 774         hdmi: hdmi@14530000 {
 775                 compatible = "samsung,exynos5420-hdmi";
 776                 reg = <0x14530000 0x70000>;
 777                 interrupts = <0 95 0>;
 778                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 779                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 780                          <&clock CLK_MOUT_HDMI>;
 781                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 782                         "sclk_hdmiphy", "mout_hdmi";
 783                 phy = <&hdmiphy>;
 784                 samsung,syscon-phandle = <&pmu_system_controller>;
 785                 status = "disabled";
 786                 power-domains = <&disp_pd>;
 787         };
 788
 789         hdmiphy: hdmiphy@145D0000 {
 790                 reg = <0x145D0000 0x20>;
 791         };
 792
 793         mixer: mixer@14450000 {
 794                 compatible = "samsung,exynos5420-mixer";
 795                 reg = <0x14450000 0x10000>;
 796                 interrupts = <0 94 0>;
 797                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 798                          <&clock CLK_SCLK_HDMI>;
 799                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 800                 power-domains = <&disp_pd>;
 801                 iommus = <&sysmmu_tv>;
 802         };
 803
 804         rotator: rotator@11C00000 {
 805                 compatible = "samsung,exynos5250-rotator";
 806                 reg = <0x11C00000 0x64>;
 807                 interrupts = <0 84 0>;
 808                 clocks = <&clock CLK_ROTATOR>;
 809                 clock-names = "rotator";
 810                 iommus = <&sysmmu_rotator>;
 811         };
 812
 813         gsc_0: video-scaler@13e00000 {
 814                 compatible = "samsung,exynos5-gsc";
 815                 reg = <0x13e00000 0x1000>;
 816                 interrupts = <0 85 0>;
 817                 clocks = <&clock CLK_GSCL0>;
 818                 clock-names = "gscl";
 819                 power-domains = <&gsc_pd>;
 820                 iommus = <&sysmmu_gscl0>;
 821         };
 822
 823         gsc_1: video-scaler@13e10000 {
 824                 compatible = "samsung,exynos5-gsc";
 825                 reg = <0x13e10000 0x1000>;
 826                 interrupts = <0 86 0>;
 827                 clocks = <&clock CLK_GSCL1>;
 828                 clock-names = "gscl";
 829                 power-domains = <&gsc_pd>;
 830                 iommus = <&sysmmu_gscl1>;
 831         };
 832
 833         jpeg_0: jpeg@11F50000 {
 834                 compatible = "samsung,exynos5420-jpeg";
 835                 reg = <0x11F50000 0x1000>;
 836                 interrupts = <0 89 0>;
 837                 clock-names = "jpeg";
 838                 clocks = <&clock CLK_JPEG>;
 839                 iommus = <&sysmmu_jpeg0>;
 840         };
 841
 842         jpeg_1: jpeg@11F60000 {
 843                 compatible = "samsung,exynos5420-jpeg";
 844                 reg = <0x11F60000 0x1000>;
 845                 interrupts = <0 168 0>;
 846                 clock-names = "jpeg";
 847                 clocks = <&clock CLK_JPEG2>;
 848                 iommus = <&sysmmu_jpeg1>;
 849         };
 850
 851         pmu_system_controller: system-controller@10040000 {
 852                 compatible = "samsung,exynos5420-pmu", "syscon";
 853                 reg = <0x10040000 0x5000>;
 854                 clock-names = "clkout16";
 855                 clocks = <&clock CLK_FIN_PLL>;
 856                 #clock-cells = <1>;
 857                 interrupt-controller;
 858                 #interrupt-cells = <3>;
 859                 interrupt-parent = <&gic>;
 860         };
 861
 862         sysreg_system_controller: syscon@10050000 {
 863                 compatible = "samsung,exynos5-sysreg", "syscon";
 864                 reg = <0x10050000 0x5000>;
 865         };
 866
 867         tmu_cpu0: tmu@10060000 {
 868                 compatible = "samsung,exynos5420-tmu";
 869                 reg = <0x10060000 0x100>;
 870                 interrupts = <0 65 0>;
 871                 clocks = <&clock CLK_TMU>;
 872                 clock-names = "tmu_apbif";
 873                 #include "exynos4412-tmu-sensor-conf.dtsi"
 874         };
 875
 876         tmu_cpu1: tmu@10064000 {
 877                 compatible = "samsung,exynos5420-tmu";
 878                 reg = <0x10064000 0x100>;
 879                 interrupts = <0 183 0>;
 880                 clocks = <&clock CLK_TMU>;
 881                 clock-names = "tmu_apbif";
 882                 #include "exynos4412-tmu-sensor-conf.dtsi"
 883         };
 884
 885         tmu_cpu2: tmu@10068000 {
 886                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 887                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 888                 interrupts = <0 184 0>;
 889                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 890                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 891                 #include "exynos4412-tmu-sensor-conf.dtsi"
 892         };
 893
 894         tmu_cpu3: tmu@1006c000 {
 895                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 896                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 897                 interrupts = <0 185 0>;
 898                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 899                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 900                 #include "exynos4412-tmu-sensor-conf.dtsi"
 901         };
 902
 903         tmu_gpu: tmu@100a0000 {
 904                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 905                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 906                 interrupts = <0 215 0>;
 907                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 908                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 909                 #include "exynos4412-tmu-sensor-conf.dtsi"
 910         };
 911
 912         thermal-zones {
 913                 cpu0_thermal: cpu0-thermal {
 914                         thermal-sensors = <&tmu_cpu0>;
 915                         #include "exynos5420-trip-points.dtsi"
 916                 };
 917                 cpu1_thermal: cpu1-thermal {
 918                        thermal-sensors = <&tmu_cpu1>;
 919                        #include "exynos5420-trip-points.dtsi"
 920                 };
 921                 cpu2_thermal: cpu2-thermal {
 922                        thermal-sensors = <&tmu_cpu2>;
 923                        #include "exynos5420-trip-points.dtsi"
 924                 };
 925                 cpu3_thermal: cpu3-thermal {
 926                        thermal-sensors = <&tmu_cpu3>;
 927                        #include "exynos5420-trip-points.dtsi"
 928                 };
 929                 gpu_thermal: gpu-thermal {
 930                        thermal-sensors = <&tmu_gpu>;
 931                        #include "exynos5420-trip-points.dtsi"
 932                 };
 933         };
 934
 935         watchdog: watchdog@101D0000 {
 936                 compatible = "samsung,exynos5420-wdt";
 937                 reg = <0x101D0000 0x100>;
 938                 interrupts = <0 42 0>;
 939                 clocks = <&clock CLK_WDT>;
 940                 clock-names = "watchdog";
 941                 samsung,syscon-phandle = <&pmu_system_controller>;
 942         };
 943
 944         sss: sss@10830000 {
 945                 compatible = "samsung,exynos4210-secss";
 946                 reg = <0x10830000 0x300>;
 947                 interrupts = <0 112 0>;
 948                 clocks = <&clock CLK_SSS>;
 949                 clock-names = "secss";
 950         };
 951
 952         usbdrd3_0: usb3-0 {
 953                 compatible = "samsung,exynos5250-dwusb3";
 954                 clocks = <&clock CLK_USBD300>;
 955                 clock-names = "usbdrd30";
 956                 #address-cells = <1>;
 957                 #size-cells = <1>;
 958                 ranges;
 959
 960                 usbdrd_dwc3_0: dwc3@12000000 {
 961                         compatible = "snps,dwc3";
 962                         reg = <0x12000000 0x10000>;
 963                         interrupts = <0 72 0>;
 964                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 965                         phy-names = "usb2-phy", "usb3-phy";
 966                 };
 967         };
 968
 969         usbdrd_phy0: phy@12100000 {
 970                 compatible = "samsung,exynos5420-usbdrd-phy";
 971                 reg = <0x12100000 0x100>;
 972                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 973                 clock-names = "phy", "ref";
 974                 samsung,pmu-syscon = <&pmu_system_controller>;
 975                 #phy-cells = <1>;
 976         };
 977
 978         usbdrd3_1: usb3-1 {
 979                 compatible = "samsung,exynos5250-dwusb3";
 980                 clocks = <&clock CLK_USBD301>;
 981                 clock-names = "usbdrd30";
 982                 #address-cells = <1>;
 983                 #size-cells = <1>;
 984                 ranges;
 985
 986                 usbdrd_dwc3_1: dwc3@12400000 {
 987                         compatible = "snps,dwc3";
 988                         reg = <0x12400000 0x10000>;
 989                         interrupts = <0 73 0>;
 990                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 991                         phy-names = "usb2-phy", "usb3-phy";
 992                 };
 993         };
 994
 995         usbdrd_phy1: phy@12500000 {
 996                 compatible = "samsung,exynos5420-usbdrd-phy";
 997                 reg = <0x12500000 0x100>;
 998                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 999                 clock-names = "phy", "ref";
1000                 samsung,pmu-syscon = <&pmu_system_controller>;
1001                 #phy-cells = <1>;
1002         };
1003
1004         usbhost2: usb@12110000 {
1005                 compatible = "samsung,exynos4210-ehci";
1006                 reg = <0x12110000 0x100>;
1007                 interrupts = <0 71 0>;
1008
1009                 clocks = <&clock CLK_USBH20>;
1010                 clock-names = "usbhost";
1011                 #address-cells = <1>;
1012                 #size-cells = <0>;
1013                 port@0 {
1014                         reg = <0>;
1015                         phys = <&usb2_phy 1>;
1016                 };
1017         };
1018
1019         usbhost1: usb@12120000 {
1020                 compatible = "samsung,exynos4210-ohci";
1021                 reg = <0x12120000 0x100>;
1022                 interrupts = <0 71 0>;
1023
1024                 clocks = <&clock CLK_USBH20>;
1025                 clock-names = "usbhost";
1026                 #address-cells = <1>;
1027                 #size-cells = <0>;
1028                 port@0 {
1029                         reg = <0>;
1030                         phys = <&usb2_phy 1>;
1031                 };
1032         };
1033
1034         usb2_phy: phy@12130000 {
1035                 compatible = "samsung,exynos5250-usb2-phy";
1036                 reg = <0x12130000 0x100>;
1037                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1038                 clock-names = "phy", "ref";
1039                 #phy-cells = <1>;
1040                 samsung,sysreg-phandle = <&sysreg_system_controller>;
1041                 samsung,pmureg-phandle = <&pmu_system_controller>;
1042         };
1043
1044         sysmmu_g2dr: sysmmu@0x10A60000 {
1045                 compatible = "samsung,exynos-sysmmu";
1046                 reg = <0x10A60000 0x1000>;
1047                 interrupt-parent = <&combiner>;
1048                 interrupts = <24 5>;
1049                 clock-names = "sysmmu", "master";
1050                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1051                 #iommu-cells = <0>;
1052         };
1053
1054         sysmmu_g2dw: sysmmu@0x10A70000 {
1055                 compatible = "samsung,exynos-sysmmu";
1056                 reg = <0x10A70000 0x1000>;
1057                 interrupt-parent = <&combiner>;
1058                 interrupts = <22 2>;
1059                 clock-names = "sysmmu", "master";
1060                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1061                 #iommu-cells = <0>;
1062         };
1063
1064         sysmmu_tv: sysmmu@0x14650000 {
1065                 compatible = "samsung,exynos-sysmmu";
1066                 reg = <0x14650000 0x1000>;
1067                 interrupt-parent = <&combiner>;
1068                 interrupts = <7 4>;
1069                 clock-names = "sysmmu", "master";
1070                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1071                 power-domains = <&disp_pd>;
1072                 #iommu-cells = <0>;
1073         };
1074
1075         sysmmu_gscl0: sysmmu@0x13E80000 {
1076                 compatible = "samsung,exynos-sysmmu";
1077                 reg = <0x13E80000 0x1000>;
1078                 interrupt-parent = <&combiner>;
1079                 interrupts = <2 0>;
1080                 clock-names = "sysmmu", "master";
1081                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1082                 power-domains = <&gsc_pd>;
1083                 #iommu-cells = <0>;
1084         };
1085
1086         sysmmu_gscl1: sysmmu@0x13E90000 {
1087                 compatible = "samsung,exynos-sysmmu";
1088                 reg = <0x13E90000 0x1000>;
1089                 interrupt-parent = <&combiner>;
1090                 interrupts = <2 2>;
1091                 clock-names = "sysmmu", "master";
1092                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1093                 power-domains = <&gsc_pd>;
1094                 #iommu-cells = <0>;
1095         };
1096
1097         sysmmu_scaler0r: sysmmu@0x12880000 {
1098                 compatible = "samsung,exynos-sysmmu";
1099                 reg = <0x12880000 0x1000>;
1100                 interrupt-parent = <&combiner>;
1101                 interrupts = <22 4>;
1102                 clock-names = "sysmmu", "master";
1103                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1104                 #iommu-cells = <0>;
1105         };
1106
1107         sysmmu_scaler1r: sysmmu@0x12890000 {
1108                 compatible = "samsung,exynos-sysmmu";
1109                 reg = <0x12890000 0x1000>;
1110                 interrupts = <0 186 0>;
1111                 clock-names = "sysmmu", "master";
1112                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1113                 #iommu-cells = <0>;
1114         };
1115
1116         sysmmu_scaler2r: sysmmu@0x128A0000 {
1117                 compatible = "samsung,exynos-sysmmu";
1118                 reg = <0x128A0000 0x1000>;
1119                 interrupts = <0 188 0>;
1120                 clock-names = "sysmmu", "master";
1121                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1122                 #iommu-cells = <0>;
1123         };
1124
1125         sysmmu_scaler0w: sysmmu@0x128C0000 {
1126                 compatible = "samsung,exynos-sysmmu";
1127                 reg = <0x128C0000 0x1000>;
1128                 interrupt-parent = <&combiner>;
1129                 interrupts = <27 2>;
1130                 clock-names = "sysmmu", "master";
1131                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1132                 #iommu-cells = <0>;
1133         };
1134
1135         sysmmu_scaler1w: sysmmu@0x128D0000 {
1136                 compatible = "samsung,exynos-sysmmu";
1137                 reg = <0x128D0000 0x1000>;
1138                 interrupt-parent = <&combiner>;
1139                 interrupts = <22 6>;
1140                 clock-names = "sysmmu", "master";
1141                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1142                 #iommu-cells = <0>;
1143         };
1144
1145         sysmmu_scaler2w: sysmmu@0x128E0000 {
1146                 compatible = "samsung,exynos-sysmmu";
1147                 reg = <0x128E0000 0x1000>;
1148                 interrupt-parent = <&combiner>;
1149                 interrupts = <19 6>;
1150                 clock-names = "sysmmu", "master";
1151                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1152                 #iommu-cells = <0>;
1153         };
1154
1155         sysmmu_rotator: sysmmu@0x11D40000 {
1156                 compatible = "samsung,exynos-sysmmu";
1157                 reg = <0x11D40000 0x1000>;
1158                 interrupt-parent = <&combiner>;
1159                 interrupts = <4 0>;
1160                 clock-names = "sysmmu", "master";
1161                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1162                 #iommu-cells = <0>;
1163         };
1164
1165         sysmmu_jpeg0: sysmmu@0x11F10000 {
1166                 compatible = "samsung,exynos-sysmmu";
1167                 reg = <0x11F10000 0x1000>;
1168                 interrupt-parent = <&combiner>;
1169                 interrupts = <4 2>;
1170                 clock-names = "sysmmu", "master";
1171                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1172                 #iommu-cells = <0>;
1173         };
1174
1175         sysmmu_jpeg1: sysmmu@0x11F20000 {
1176                 compatible = "samsung,exynos-sysmmu";
1177                 reg = <0x11F20000 0x1000>;
1178                 interrupts = <0 169 0>;
1179                 clock-names = "sysmmu", "master";
1180                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1181                 #iommu-cells = <0>;
1182         };
1183
1184         sysmmu_mfc_l: sysmmu@0x11200000 {
1185                 compatible = "samsung,exynos-sysmmu";
1186                 reg = <0x11200000 0x1000>;
1187                 interrupt-parent = <&combiner>;
1188                 interrupts = <6 2>;
1189                 clock-names = "sysmmu", "master";
1190                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1191                 power-domains = <&mfc_pd>;
1192                 #iommu-cells = <0>;
1193         };
1194
1195         sysmmu_mfc_r: sysmmu@0x11210000 {
1196                 compatible = "samsung,exynos-sysmmu";
1197                 reg = <0x11210000 0x1000>;
1198                 interrupt-parent = <&combiner>;
1199                 interrupts = <8 5>;
1200                 clock-names = "sysmmu", "master";
1201                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1202                 power-domains = <&mfc_pd>;
1203                 #iommu-cells = <0>;
1204         };
1205
1206         sysmmu_fimd1_0: sysmmu@0x14640000 {
1207                 compatible = "samsung,exynos-sysmmu";
1208                 reg = <0x14640000 0x1000>;
1209                 interrupt-parent = <&combiner>;
1210                 interrupts = <3 2>;
1211                 clock-names = "sysmmu", "master";
1212                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1213                 power-domains = <&disp_pd>;
1214                 #iommu-cells = <0>;
1215         };
1216
1217         sysmmu_fimd1_1: sysmmu@0x14680000 {
1218                 compatible = "samsung,exynos-sysmmu";
1219                 reg = <0x14680000 0x1000>;
1220                 interrupt-parent = <&combiner>;
1221                 interrupts = <3 0>;
1222                 clock-names = "sysmmu", "master";
1223                 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1224                 power-domains = <&disp_pd>;
1225                 #iommu-cells = <0>;
1226         };
1227
1228         bus_wcore: bus_wcore {
1229                 compatible = "samsung,exynos-bus";
1230                 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1231                 clock-names = "bus";
1232                 operating-points-v2 = <&bus_wcore_opp_table>;
1233                 status = "disabled";
1234         };
1235
1236         bus_noc: bus_noc {
1237                 compatible = "samsung,exynos-bus";
1238                 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1239                 clock-names = "bus";
1240                 operating-points-v2 = <&bus_noc_opp_table>;
1241                 status = "disabled";
1242         };
1243
1244         bus_fsys_apb: bus_fsys_apb {
1245                 compatible = "samsung,exynos-bus";
1246                 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1247                 clock-names = "bus";
1248                 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1249                 status = "disabled";
1250         };
1251
1252         bus_fsys: bus_fsys {
1253                 compatible = "samsung,exynos-bus";
1254                 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1255                 clock-names = "bus";
1256                 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1257                 status = "disabled";
1258         };
1259
1260         bus_fsys2: bus_fsys2 {
1261                 compatible = "samsung,exynos-bus";
1262                 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1263                 clock-names = "bus";
1264                 operating-points-v2 = <&bus_fsys2_opp_table>;
1265                 status = "disabled";
1266         };
1267
1268         bus_mfc: bus_mfc {
1269                 compatible = "samsung,exynos-bus";
1270                 clocks = <&clock CLK_DOUT_ACLK333>;
1271                 clock-names = "bus";
1272                 operating-points-v2 = <&bus_mfc_opp_table>;
1273                 status = "disabled";
1274         };
1275
1276         bus_gen: bus_gen {
1277                 compatible = "samsung,exynos-bus";
1278                 clocks = <&clock CLK_DOUT_ACLK266>;
1279                 clock-names = "bus";
1280                 operating-points-v2 = <&bus_gen_opp_table>;
1281                 status = "disabled";
1282         };
1283
1284         bus_peri: bus_peri {
1285                 compatible = "samsung,exynos-bus";
1286                 clocks = <&clock CLK_DOUT_ACLK66>;
1287                 clock-names = "bus";
1288                 operating-points-v2 = <&bus_peri_opp_table>;
1289                 status = "disabled";
1290         };
1291
1292         bus_g2d: bus_g2d {
1293                 compatible = "samsung,exynos-bus";
1294                 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1295                 clock-names = "bus";
1296                 operating-points-v2 = <&bus_g2d_opp_table>;
1297                 status = "disabled";
1298         };
1299
1300         bus_g2d_acp: bus_g2d_acp {
1301                 compatible = "samsung,exynos-bus";
1302                 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1303                 clock-names = "bus";
1304                 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1305                 status = "disabled";
1306         };
1307
1308         bus_jpeg: bus_jpeg {
1309                 compatible = "samsung,exynos-bus";
1310                 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1311                 clock-names = "bus";
1312                 operating-points-v2 = <&bus_jpeg_opp_table>;
1313                 status = "disabled";
1314         };
1315
1316         bus_jpeg_apb: bus_jpeg_apb {
1317                 compatible = "samsung,exynos-bus";
1318                 clocks = <&clock CLK_DOUT_ACLK166>;
1319                 clock-names = "bus";
1320                 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1321                 status = "disabled";
1322         };
1323
1324         bus_disp1_fimd: bus_disp1_fimd {
1325                 compatible = "samsung,exynos-bus";
1326                 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1327                 clock-names = "bus";
1328                 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1329                 status = "disabled";
1330         };
1331
1332         bus_disp1: bus_disp1 {
1333                 compatible = "samsung,exynos-bus";
1334                 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1335                 clock-names = "bus";
1336                 operating-points-v2 = <&bus_disp1_opp_table>;
1337                 status = "disabled";
1338         };
1339
1340         bus_gscl_scaler: bus_gscl_scaler {
1341                 compatible = "samsung,exynos-bus";
1342                 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1343                 clock-names = "bus";
1344                 operating-points-v2 = <&bus_gscl_opp_table>;
1345                 status = "disabled";
1346         };
1347
1348         bus_mscl: bus_mscl {
1349                 compatible = "samsung,exynos-bus";
1350                 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1351                 clock-names = "bus";
1352                 operating-points-v2 = <&bus_mscl_opp_table>;
1353                 status = "disabled";
1354         };
1355
1356         bus_wcore_opp_table: opp_table2 {
1357                 compatible = "operating-points-v2";
1358
1359                 opp00 {
1360                         opp-hz = /bits/ 64 <84000000>;
1361                         opp-microvolt = <925000>;
1362                 };
1363                 opp01 {
1364                         opp-hz = /bits/ 64 <111000000>;
1365                         opp-microvolt = <950000>;
1366                 };
1367                 opp02 {
1368                         opp-hz = /bits/ 64 <222000000>;
1369                         opp-microvolt = <950000>;
1370                 };
1371                 opp03 {
1372                         opp-hz = /bits/ 64 <333000000>;
1373                         opp-microvolt = <950000>;
1374                 };
1375                 opp04 {
1376                         opp-hz = /bits/ 64 <400000000>;
1377                         opp-microvolt = <987500>;
1378                 };
1379         };
1380
1381         bus_noc_opp_table: opp_table3 {
1382                 compatible = "operating-points-v2";
1383
1384                 opp00 {
1385                         opp-hz = /bits/ 64 <67000000>;
1386                 };
1387                 opp01 {
1388                         opp-hz = /bits/ 64 <75000000>;
1389                 };
1390                 opp02 {
1391                         opp-hz = /bits/ 64 <86000000>;
1392                 };
1393                 opp03 {
1394                         opp-hz = /bits/ 64 <100000000>;
1395                 };
1396         };
1397
1398         bus_fsys_apb_opp_table: opp_table4 {
1399                 compatible = "operating-points-v2";
1400                 opp-shared;
1401
1402                 opp00 {
1403                         opp-hz = /bits/ 64 <100000000>;
1404                 };
1405                 opp01 {
1406                         opp-hz = /bits/ 64 <200000000>;
1407                 };
1408         };
1409
1410         bus_fsys2_opp_table: opp_table5 {
1411                 compatible = "operating-points-v2";
1412
1413                 opp00 {
1414                         opp-hz = /bits/ 64 <75000000>;
1415                 };
1416                 opp01 {
1417                         opp-hz = /bits/ 64 <100000000>;
1418                 };
1419                 opp02 {
1420                         opp-hz = /bits/ 64 <150000000>;
1421                 };
1422         };
1423
1424         bus_mfc_opp_table: opp_table6 {
1425                 compatible = "operating-points-v2";
1426
1427                 opp00 {
1428                         opp-hz = /bits/ 64 <96000000>;
1429                 };
1430                 opp01 {
1431                         opp-hz = /bits/ 64 <111000000>;
1432                 };
1433                 opp02 {
1434                         opp-hz = /bits/ 64 <167000000>;
1435                 };
1436                 opp03 {
1437                         opp-hz = /bits/ 64 <222000000>;
1438                 };
1439                 opp04 {
1440                         opp-hz = /bits/ 64 <333000000>;
1441                 };
1442         };
1443
1444         bus_gen_opp_table: opp_table7 {
1445                 compatible = "operating-points-v2";
1446
1447                 opp00 {
1448                         opp-hz = /bits/ 64 <89000000>;
1449                 };
1450                 opp01 {
1451                         opp-hz = /bits/ 64 <133000000>;
1452                 };
1453                 opp02 {
1454                         opp-hz = /bits/ 64 <178000000>;
1455                 };
1456                 opp03 {
1457                         opp-hz = /bits/ 64 <267000000>;
1458                 };
1459         };
1460
1461         bus_peri_opp_table: opp_table8 {
1462                 compatible = "operating-points-v2";
1463
1464                 opp00 {
1465                         opp-hz = /bits/ 64 <67000000>;
1466                 };
1467         };
1468
1469         bus_g2d_opp_table: opp_table9 {
1470                 compatible = "operating-points-v2";
1471
1472                 opp00 {
1473                         opp-hz = /bits/ 64 <84000000>;
1474                 };
1475                 opp01 {
1476                         opp-hz = /bits/ 64 <167000000>;
1477                 };
1478                 opp02 {
1479                         opp-hz = /bits/ 64 <222000000>;
1480                 };
1481                 opp03 {
1482                         opp-hz = /bits/ 64 <300000000>;
1483                 };
1484                 opp04 {
1485                         opp-hz = /bits/ 64 <333000000>;
1486                 };
1487         };
1488
1489         bus_g2d_acp_opp_table: opp_table10 {
1490                 compatible = "operating-points-v2";
1491
1492                 opp00 {
1493                         opp-hz = /bits/ 64 <67000000>;
1494                 };
1495                 opp01 {
1496                         opp-hz = /bits/ 64 <133000000>;
1497                 };
1498                 opp02 {
1499                         opp-hz = /bits/ 64 <178000000>;
1500                 };
1501                 opp03 {
1502                         opp-hz = /bits/ 64 <267000000>;
1503                 };
1504         };
1505
1506         bus_jpeg_opp_table: opp_table11 {
1507                 compatible = "operating-points-v2";
1508
1509                 opp00 {
1510                         opp-hz = /bits/ 64 <75000000>;
1511                 };
1512                 opp01 {
1513                         opp-hz = /bits/ 64 <150000000>;
1514                 };
1515                 opp02 {
1516                         opp-hz = /bits/ 64 <200000000>;
1517                 };
1518                 opp03 {
1519                         opp-hz = /bits/ 64 <300000000>;
1520                 };
1521         };
1522
1523         bus_jpeg_apb_opp_table: opp_table12 {
1524                 compatible = "operating-points-v2";
1525
1526                 opp00 {
1527                         opp-hz = /bits/ 64 <84000000>;
1528                 };
1529                 opp01 {
1530                         opp-hz = /bits/ 64 <111000000>;
1531                 };
1532                 opp02 {
1533                         opp-hz = /bits/ 64 <134000000>;
1534                 };
1535                 opp03 {
1536                         opp-hz = /bits/ 64 <167000000>;
1537                 };
1538         };
1539
1540         bus_disp1_fimd_opp_table: opp_table13 {
1541                 compatible = "operating-points-v2";
1542
1543                 opp00 {
1544                         opp-hz = /bits/ 64 <120000000>;
1545                 };
1546                 opp01 {
1547                         opp-hz = /bits/ 64 <200000000>;
1548                 };
1549         };
1550
1551         bus_disp1_opp_table: opp_table14 {
1552                 compatible = "operating-points-v2";
1553
1554                 opp00 {
1555                         opp-hz = /bits/ 64 <120000000>;
1556                 };
1557                 opp01 {
1558                         opp-hz = /bits/ 64 <200000000>;
1559                 };
1560                 opp02 {
1561                         opp-hz = /bits/ 64 <300000000>;
1562                 };
1563         };
1564
1565         bus_gscl_opp_table: opp_table15 {
1566                 compatible = "operating-points-v2";
1567
1568                 opp00 {
1569                         opp-hz = /bits/ 64 <150000000>;
1570                 };
1571                 opp01 {
1572                         opp-hz = /bits/ 64 <200000000>;
1573                 };
1574                 opp02 {
1575                         opp-hz = /bits/ 64 <300000000>;
1576                 };
1577         };
1578
1579         bus_mscl_opp_table: opp_table16 {
1580                 compatible = "operating-points-v2";
1581
1582                 opp00 {
1583                         opp-hz = /bits/ 64 <84000000>;
1584                 };
1585                 opp01 {
1586                         opp-hz = /bits/ 64 <167000000>;
1587                 };
1588                 opp02 {
1589                         opp-hz = /bits/ 64 <222000000>;
1590                 };
1591                 opp03 {
1592                         opp-hz = /bits/ 64 <333000000>;
1593                 };
1594                 opp04 {
1595                         opp-hz = /bits/ 64 <400000000>;
1596                 };
1597         };
1598 };
1599
1600 &dp {
1601         clocks = <&clock CLK_DP1>;
1602         clock-names = "dp";
1603         phys = <&dp_phy>;
1604         phy-names = "dp";
1605         power-domains = <&disp_pd>;
1606 };
1607
1608 &fimd {
1609         compatible = "samsung,exynos5420-fimd";
1610         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1611         clock-names = "sclk_fimd", "fimd";
1612         power-domains = <&disp_pd>;
1613         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1614         iommu-names = "m0", "m1";
1615 };
1616
1617 &rtc {
1618         clocks = <&clock CLK_RTC>;
1619         clock-names = "rtc";
1620         interrupt-parent = <&pmu_system_controller>;
1621         status = "disabled";
1622 };
1623
1624 &serial_0 {
1625         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1626         clock-names = "uart", "clk_uart_baud0";
1627 };
1628
1629 &serial_1 {
1630         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1631         clock-names = "uart", "clk_uart_baud0";
1632 };
1633
1634 &serial_2 {
1635         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1636         clock-names = "uart", "clk_uart_baud0";
1637 };
1638
1639 &serial_3 {
1640         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1641         clock-names = "uart", "clk_uart_baud0";
1642 };
1643
1644 #include "exynos5420-pinctrl.dtsi"