arch/arm/boot/dts/exynos5420-cpus.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5420 SoC cpu device tree source
   4  *
   5  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * This file provides desired ordering for Exynos5420 and Exynos5800
   9  * boards: CPU[0123] being the A15.
  10  *
  11  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  12  * but particular boards choose different booting order.
  13  *
  14  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  15  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  16  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  17  * from the LITTLE: Cortex-A7.
  18  */
  19
  20 / {
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a15";
  28                         reg = <0x0>;
  29                         clocks = <&clock CLK_ARM_CLK>;
  30                         clock-frequency = <1800000000>;
  31                         cci-control-port = <&cci_control1>;
  32                         operating-points-v2 = <&cluster_a15_opp_table>;
  33                         cooling-min-level = <0>;
  34                         cooling-max-level = <11>;
  35                         #cooling-cells = <2>; /* min followed by max */
  36                         capacity-dmips-mhz = <1024>;
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0x1>;
  43                         clock-frequency = <1800000000>;
  44                         cci-control-port = <&cci_control1>;
  45                         operating-points-v2 = <&cluster_a15_opp_table>;
  46                         cooling-min-level = <0>;
  47                         cooling-max-level = <11>;
  48                         #cooling-cells = <2>; /* min followed by max */
  49                         capacity-dmips-mhz = <1024>;
  50                 };
  51
  52                 cpu2: cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <0x2>;
  56                         clock-frequency = <1800000000>;
  57                         cci-control-port = <&cci_control1>;
  58                         operating-points-v2 = <&cluster_a15_opp_table>;
  59                         cooling-min-level = <0>;
  60                         cooling-max-level = <11>;
  61                         #cooling-cells = <2>; /* min followed by max */
  62                         capacity-dmips-mhz = <1024>;
  63                 };
  64
  65                 cpu3: cpu@3 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <0x3>;
  69                         clock-frequency = <1800000000>;
  70                         cci-control-port = <&cci_control1>;
  71                         operating-points-v2 = <&cluster_a15_opp_table>;
  72                         cooling-min-level = <0>;
  73                         cooling-max-level = <11>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         capacity-dmips-mhz = <1024>;
  76                 };
  77
  78                 cpu4: cpu@100 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0x100>;
  82                         clocks = <&clock CLK_KFC_CLK>;
  83                         clock-frequency = <1000000000>;
  84                         cci-control-port = <&cci_control0>;
  85                         operating-points-v2 = <&cluster_a7_opp_table>;
  86                         cooling-min-level = <0>;
  87                         cooling-max-level = <7>;
  88                         #cooling-cells = <2>; /* min followed by max */
  89                         capacity-dmips-mhz = <539>;
  90                 };
  91
  92                 cpu5: cpu@101 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0x101>;
  96                         clock-frequency = <1000000000>;
  97                         cci-control-port = <&cci_control0>;
  98                         operating-points-v2 = <&cluster_a7_opp_table>;
  99                         cooling-min-level = <0>;
 100                         cooling-max-level = <7>;
 101                         #cooling-cells = <2>; /* min followed by max */
 102                         capacity-dmips-mhz = <539>;
 103                 };
 104
 105                 cpu6: cpu@102 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x102>;
 109                         clock-frequency = <1000000000>;
 110                         cci-control-port = <&cci_control0>;
 111                         operating-points-v2 = <&cluster_a7_opp_table>;
 112                         cooling-min-level = <0>;
 113                         cooling-max-level = <7>;
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         capacity-dmips-mhz = <539>;
 116                 };
 117
 118                 cpu7: cpu@103 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a7";
 121                         reg = <0x103>;
 122                         clock-frequency = <1000000000>;
 123                         cci-control-port = <&cci_control0>;
 124                         operating-points-v2 = <&cluster_a7_opp_table>;
 125                         cooling-min-level = <0>;
 126                         cooling-max-level = <7>;
 127                         #cooling-cells = <2>; /* min followed by max */
 128                         capacity-dmips-mhz = <539>;
 129                 };
 130         };
 131 };
 132
 133 &arm_a7_pmu {
 134         interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 135         status = "okay";
 136 };
 137
 138 &arm_a15_pmu {
 139         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 140         status = "okay";
 141 };