arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "skeleton.dtsi"
  17 #include "exynos-syscon-restart.dtsi"
  18 #include <dt-bindings/clock/exynos5410.h>
  19
  20 / {
  21         compatible = "samsung,exynos5410", "samsung,exynos5";
  22         interrupt-parent = <&gic>;
  23
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &uart2;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 CPU0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0x0>;
  42                         clock-frequency = <1600000000>;
  43                 };
  44
  45                 CPU1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x1>;
  49                         clock-frequency = <1600000000>;
  50                 };
  51
  52                 CPU2: cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <0x2>;
  56                         clock-frequency = <1600000000>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x3>;
  63                         clock-frequency = <1600000000>;
  64                 };
  65         };
  66
  67         soc: soc {
  68                 compatible = "simple-bus";
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 ranges;
  72
  73                 combiner: interrupt-controller@10440000 {
  74                         compatible = "samsung,exynos4210-combiner";
  75                         #interrupt-cells = <2>;
  76                         interrupt-controller;
  77                         samsung,combiner-nr = <32>;
  78                         reg = <0x10440000 0x1000>;
  79                         interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  80                                         <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  81                                         <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  82                                         <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  83                                         <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  84                                         <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  85                                         <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  86                                         <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  87                 };
  88
  89                 gic: interrupt-controller@10481000 {
  90                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  91                         #interrupt-cells = <3>;
  92                         interrupt-controller;
  93                         reg =   <0x10481000 0x1000>,
  94                                 <0x10482000 0x1000>,
  95                                 <0x10484000 0x2000>,
  96                                 <0x10486000 0x2000>;
  97                         interrupts = <1 9 0xf04>;
  98                 };
  99
 100                 chipid@10000000 {
 101                         compatible = "samsung,exynos4210-chipid";
 102                         reg = <0x10000000 0x100>;
 103                 };
 104
 105                 sromc: memory-controller@12250000 {
 106                         compatible = "samsung,exynos4210-srom";
 107                         reg = <0x12250000 0x14>;
 108                         #address-cells = <2>;
 109                         #size-cells = <1>;
 110                         ranges = <0 0 0x04000000 0x20000
 111                                   1 0 0x05000000 0x20000
 112                                   2 0 0x06000000 0x20000
 113                                   3 0 0x07000000 0x20000>;
 114                 };
 115
 116                 pmu_system_controller: system-controller@10040000 {
 117                         compatible = "samsung,exynos5410-pmu", "syscon";
 118                         reg = <0x10040000 0x5000>;
 119                 };
 120
 121                 mct: mct@101C0000 {
 122                         compatible = "samsung,exynos4210-mct";
 123                         reg = <0x101C0000 0xB00>;
 124                         interrupt-parent = <&interrupt_map>;
 125                         interrupts = <0>, <1>, <2>, <3>,
 126                                 <4>, <5>, <6>, <7>,
 127                                 <8>, <9>, <10>, <11>;
 128                         clocks = <&fin_pll>, <&clock CLK_MCT>;
 129                         clock-names = "fin_pll", "mct";
 130
 131                         interrupt_map: interrupt-map {
 132                                 #interrupt-cells = <1>;
 133                                 #address-cells = <0>;
 134                                 #size-cells = <0>;
 135                                 interrupt-map = <0 &combiner 23 3>,
 136                                                 <1 &combiner 23 4>,
 137                                                 <2 &combiner 25 2>,
 138                                                 <3 &combiner 25 3>,
 139                                                 <4 &gic 0 120 0>,
 140                                                 <5 &gic 0 121 0>,
 141                                                 <6 &gic 0 122 0>,
 142                                                 <7 &gic 0 123 0>,
 143                                                 <8 &gic 0 128 0>,
 144                                                 <9 &gic 0 129 0>,
 145                                                 <10 &gic 0 130 0>,
 146                                                 <11 &gic 0 131 0>;
 147                         };
 148                 };
 149
 150                 sysram@02020000 {
 151                         compatible = "mmio-sram";
 152                         reg = <0x02020000 0x54000>;
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges = <0 0x02020000 0x54000>;
 156
 157                         smp-sysram@0 {
 158                                 compatible = "samsung,exynos4210-sysram";
 159                                 reg = <0x0 0x1000>;
 160                         };
 161
 162                         smp-sysram@53000 {
 163                                 compatible = "samsung,exynos4210-sysram-ns";
 164                                 reg = <0x53000 0x1000>;
 165                         };
 166                 };
 167
 168                 clock: clock-controller@10010000 {
 169                         compatible = "samsung,exynos5410-clock";
 170                         reg = <0x10010000 0x30000>;
 171                         #clock-cells = <1>;
 172                 };
 173
 174                 mmc_0: mmc@12200000 {
 175                         compatible = "samsung,exynos5250-dw-mshc";
 176                         reg = <0x12200000 0x1000>;
 177                         interrupts = <0 75 0>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 181                         clock-names = "biu", "ciu";
 182                         fifo-depth = <0x80>;
 183                         status = "disabled";
 184                 };
 185
 186                 mmc_1: mmc@12210000 {
 187                         compatible = "samsung,exynos5250-dw-mshc";
 188                         reg = <0x12210000 0x1000>;
 189                         interrupts = <0 76 0>;
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 193                         clock-names = "biu", "ciu";
 194                         fifo-depth = <0x80>;
 195                         status = "disabled";
 196                 };
 197
 198                 mmc_2: mmc@12220000 {
 199                         compatible = "samsung,exynos5250-dw-mshc";
 200                         reg = <0x12220000 0x1000>;
 201                         interrupts = <0 77 0>;
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 205                         clock-names = "biu", "ciu";
 206                         fifo-depth = <0x80>;
 207                         status = "disabled";
 208                 };
 209
 210                 pinctrl_0: pinctrl@13400000 {
 211                         compatible = "samsung,exynos5410-pinctrl";
 212                         reg = <0x13400000 0x1000>;
 213                         interrupts = <0 45 0>;
 214
 215                         wakeup-interrupt-controller {
 216                                 compatible = "samsung,exynos4210-wakeup-eint";
 217                                 interrupt-parent = <&gic>;
 218                                 interrupts = <0 32 0>;
 219                         };
 220                 };
 221
 222                 pinctrl_1: pinctrl@14000000 {
 223                         compatible = "samsung,exynos5410-pinctrl";
 224                         reg = <0x14000000 0x1000>;
 225                         interrupts = <0 46 0>;
 226                 };
 227
 228                 pinctrl_2: pinctrl@10d10000 {
 229                         compatible = "samsung,exynos5410-pinctrl";
 230                         reg = <0x10d10000 0x1000>;
 231                         interrupts = <0 50 0>;
 232                 };
 233
 234                 pinctrl_3: pinctrl@03860000 {
 235                         compatible = "samsung,exynos5410-pinctrl";
 236                         reg = <0x03860000 0x1000>;
 237                         interrupts = <0 47 0>;
 238                 };
 239
 240                 uart0: serial@12C00000 {
 241                         compatible = "samsung,exynos4210-uart";
 242                         reg = <0x12C00000 0x100>;
 243                         interrupts = <0 51 0>;
 244                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 245                         clock-names = "uart", "clk_uart_baud0";
 246                         status = "disabled";
 247                 };
 248
 249                 uart1: serial@12C10000 {
 250                         compatible = "samsung,exynos4210-uart";
 251                         reg = <0x12C10000 0x100>;
 252                         interrupts = <0 52 0>;
 253                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 254                         clock-names = "uart", "clk_uart_baud0";
 255                         status = "disabled";
 256                 };
 257
 258                 uart2: serial@12C20000 {
 259                         compatible = "samsung,exynos4210-uart";
 260                         reg = <0x12C20000 0x100>;
 261                         interrupts = <0 53 0>;
 262                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 263                         clock-names = "uart", "clk_uart_baud0";
 264                         status = "disabled";
 265                 };
 266         };
 267 };
 268
 269 #include "exynos5410-pinctrl.dtsi"