Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / exynos5250.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SAMSUNG EXYNOS5250 SoC device tree source
4  *
5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6  *              http://www.samsung.com
7  *
8  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9  * EXYNOS5250 based board files can include this file and provide
10  * values for board specfic bindings.
11  *
12  * Note: This file does not include device nodes for all the controllers in
13  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14  * additional nodes can be added to this file.
15  */
16
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21
22 / {
23         compatible = "samsung,exynos5250", "samsung,exynos5";
24
25         aliases {
26                 spi0 = &spi_0;
27                 spi1 = &spi_1;
28                 spi2 = &spi_2;
29                 gsc0 = &gsc_0;
30                 gsc1 = &gsc_1;
31                 gsc2 = &gsc_2;
32                 gsc3 = &gsc_3;
33                 mshc0 = &mmc_0;
34                 mshc1 = &mmc_1;
35                 mshc2 = &mmc_2;
36                 mshc3 = &mmc_3;
37                 i2c4 = &i2c_4;
38                 i2c5 = &i2c_5;
39                 i2c6 = &i2c_6;
40                 i2c7 = &i2c_7;
41                 i2c8 = &i2c_8;
42                 i2c9 = &i2c_9;
43                 pinctrl0 = &pinctrl_0;
44                 pinctrl1 = &pinctrl_1;
45                 pinctrl2 = &pinctrl_2;
46                 pinctrl3 = &pinctrl_3;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52
53                 cpu0: cpu@0 {
54                         device_type = "cpu";
55                         compatible = "arm,cortex-a15";
56                         reg = <0>;
57                         clocks = <&clock CLK_ARM_CLK>;
58                         clock-names = "cpu";
59                         operating-points-v2 = <&cpu0_opp_table>;
60                         #cooling-cells = <2>; /* min followed by max */
61                 };
62                 cpu1: cpu@1 {
63                         device_type = "cpu";
64                         compatible = "arm,cortex-a15";
65                         reg = <1>;
66                         clocks = <&clock CLK_ARM_CLK>;
67                         clock-names = "cpu";
68                         operating-points-v2 = <&cpu0_opp_table>;
69                         #cooling-cells = <2>; /* min followed by max */
70                 };
71         };
72
73         cpu0_opp_table: opp_table0 {
74                 compatible = "operating-points-v2";
75                 opp-shared;
76
77                 opp-200000000 {
78                         opp-hz = /bits/ 64 <200000000>;
79                         opp-microvolt = <925000>;
80                         clock-latency-ns = <140000>;
81                 };
82                 opp-300000000 {
83                         opp-hz = /bits/ 64 <300000000>;
84                         opp-microvolt = <937500>;
85                         clock-latency-ns = <140000>;
86                 };
87                 opp-400000000 {
88                         opp-hz = /bits/ 64 <400000000>;
89                         opp-microvolt = <950000>;
90                         clock-latency-ns = <140000>;
91                 };
92                 opp-500000000 {
93                         opp-hz = /bits/ 64 <500000000>;
94                         opp-microvolt = <975000>;
95                         clock-latency-ns = <140000>;
96                 };
97                 opp-600000000 {
98                         opp-hz = /bits/ 64 <600000000>;
99                         opp-microvolt = <1000000>;
100                         clock-latency-ns = <140000>;
101                 };
102                 opp-700000000 {
103                         opp-hz = /bits/ 64 <700000000>;
104                         opp-microvolt = <1012500>;
105                         clock-latency-ns = <140000>;
106                 };
107                 opp-800000000 {
108                         opp-hz = /bits/ 64 <800000000>;
109                         opp-microvolt = <1025000>;
110                         clock-latency-ns = <140000>;
111                 };
112                 opp-900000000 {
113                         opp-hz = /bits/ 64 <900000000>;
114                         opp-microvolt = <1050000>;
115                         clock-latency-ns = <140000>;
116                 };
117                 opp-1000000000 {
118                         opp-hz = /bits/ 64 <1000000000>;
119                         opp-microvolt = <1075000>;
120                         clock-latency-ns = <140000>;
121                         opp-suspend;
122                 };
123                 opp-1100000000 {
124                         opp-hz = /bits/ 64 <1100000000>;
125                         opp-microvolt = <1100000>;
126                         clock-latency-ns = <140000>;
127                 };
128                 opp-1200000000 {
129                         opp-hz = /bits/ 64 <1200000000>;
130                         opp-microvolt = <1125000>;
131                         clock-latency-ns = <140000>;
132                 };
133                 opp-1300000000 {
134                         opp-hz = /bits/ 64 <1300000000>;
135                         opp-microvolt = <1150000>;
136                         clock-latency-ns = <140000>;
137                 };
138                 opp-1400000000 {
139                         opp-hz = /bits/ 64 <1400000000>;
140                         opp-microvolt = <1200000>;
141                         clock-latency-ns = <140000>;
142                 };
143                 opp-1500000000 {
144                         opp-hz = /bits/ 64 <1500000000>;
145                         opp-microvolt = <1225000>;
146                         clock-latency-ns = <140000>;
147                 };
148                 opp-1600000000 {
149                         opp-hz = /bits/ 64 <1600000000>;
150                         opp-microvolt = <1250000>;
151                         clock-latency-ns = <140000>;
152                 };
153                 opp-1700000000 {
154                         opp-hz = /bits/ 64 <1700000000>;
155                         opp-microvolt = <1300000>;
156                         clock-latency-ns = <140000>;
157                 };
158         };
159
160         pmu {
161                 compatible = "arm,cortex-a15-pmu";
162                 interrupt-parent = <&combiner>;
163                 interrupts = <1 2>, <22 4>;
164         };
165
166         soc: soc {
167                 sysram@2020000 {
168                         compatible = "mmio-sram";
169                         reg = <0x02020000 0x30000>;
170                         #address-cells = <1>;
171                         #size-cells = <1>;
172                         ranges = <0 0x02020000 0x30000>;
173
174                         smp-sysram@0 {
175                                 compatible = "samsung,exynos4210-sysram";
176                                 reg = <0x0 0x1000>;
177                         };
178
179                         smp-sysram@2f000 {
180                                 compatible = "samsung,exynos4210-sysram-ns";
181                                 reg = <0x2f000 0x1000>;
182                         };
183                 };
184
185                 pd_gsc: power-domain@10044000 {
186                         compatible = "samsung,exynos4210-pd";
187                         reg = <0x10044000 0x20>;
188                         #power-domain-cells = <0>;
189                         label = "GSC";
190                 };
191
192                 pd_mfc: power-domain@10044040 {
193                         compatible = "samsung,exynos4210-pd";
194                         reg = <0x10044040 0x20>;
195                         #power-domain-cells = <0>;
196                         label = "MFC";
197                 };
198
199                 pd_g3d: power-domain@10044060 {
200                         compatible = "samsung,exynos4210-pd";
201                         reg = <0x10044060 0x20>;
202                         #power-domain-cells = <0>;
203                         label = "G3D";
204                 };
205
206                 pd_disp1: power-domain@100440a0 {
207                         compatible = "samsung,exynos4210-pd";
208                         reg = <0x100440A0 0x20>;
209                         #power-domain-cells = <0>;
210                         label = "DISP1";
211                 };
212
213                 pd_mau: power-domain@100440c0 {
214                         compatible = "samsung,exynos4210-pd";
215                         reg = <0x100440C0 0x20>;
216                         #power-domain-cells = <0>;
217                         label = "MAU";
218                 };
219
220                 clock: clock-controller@10010000 {
221                         compatible = "samsung,exynos5250-clock";
222                         reg = <0x10010000 0x30000>;
223                         #clock-cells = <1>;
224                 };
225
226                 clock_audss: audss-clock-controller@3810000 {
227                         compatible = "samsung,exynos5250-audss-clock";
228                         reg = <0x03810000 0x0C>;
229                         #clock-cells = <1>;
230                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233                         power-domains = <&pd_mau>;
234                 };
235
236                 mct@101c0000 {
237                         compatible = "samsung,exynos4210-mct";
238                         reg = <0x101C0000 0x800>;
239                         interrupt-controller;
240                         #interrupt-cells = <2>;
241                         interrupt-parent = <&mct_map>;
242                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
243                                      <4 0>, <5 0>;
244                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
245                         clock-names = "fin_pll", "mct";
246
247                         mct_map: mct-map {
248                                 #interrupt-cells = <2>;
249                                 #address-cells = <0>;
250                                 #size-cells = <0>;
251                                 interrupt-map = <0x0 0 &combiner 23 3>,
252                                                 <0x1 0 &combiner 23 4>,
253                                                 <0x2 0 &combiner 25 2>,
254                                                 <0x3 0 &combiner 25 3>,
255                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
256                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
257                         };
258                 };
259
260                 pinctrl_0: pinctrl@11400000 {
261                         compatible = "samsung,exynos5250-pinctrl";
262                         reg = <0x11400000 0x1000>;
263                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
264
265                         wakup_eint: wakeup-interrupt-controller {
266                                 compatible = "samsung,exynos4210-wakeup-eint";
267                                 interrupt-parent = <&gic>;
268                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
269                         };
270                 };
271
272                 pinctrl_1: pinctrl@13400000 {
273                         compatible = "samsung,exynos5250-pinctrl";
274                         reg = <0x13400000 0x1000>;
275                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
276                 };
277
278                 pinctrl_2: pinctrl@10d10000 {
279                         compatible = "samsung,exynos5250-pinctrl";
280                         reg = <0x10d10000 0x1000>;
281                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
282                 };
283
284                 pinctrl_3: pinctrl@3860000 {
285                         compatible = "samsung,exynos5250-pinctrl";
286                         reg = <0x03860000 0x1000>;
287                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
288                         power-domains = <&pd_mau>;
289                 };
290
291                 pmu_system_controller: system-controller@10040000 {
292                         compatible = "samsung,exynos5250-pmu", "syscon";
293                         reg = <0x10040000 0x5000>;
294                         clock-names = "clkout16";
295                         clocks = <&clock CLK_FIN_PLL>;
296                         #clock-cells = <1>;
297                         interrupt-controller;
298                         #interrupt-cells = <3>;
299                         interrupt-parent = <&gic>;
300                 };
301
302                 watchdog@101d0000 {
303                         compatible = "samsung,exynos5250-wdt";
304                         reg = <0x101D0000 0x100>;
305                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
306                         clocks = <&clock CLK_WDT>;
307                         clock-names = "watchdog";
308                         samsung,syscon-phandle = <&pmu_system_controller>;
309                 };
310
311                 mfc: codec@11000000 {
312                         compatible = "samsung,mfc-v6";
313                         reg = <0x11000000 0x10000>;
314                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
315                         power-domains = <&pd_mfc>;
316                         clocks = <&clock CLK_MFC>;
317                         clock-names = "mfc";
318                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
319                         iommu-names = "left", "right";
320                 };
321
322                 rotator: rotator@11c00000 {
323                         compatible = "samsung,exynos5250-rotator";
324                         reg = <0x11C00000 0x64>;
325                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
326                         clocks = <&clock CLK_ROTATOR>;
327                         clock-names = "rotator";
328                         iommus = <&sysmmu_rotator>;
329                 };
330
331                 tmu: tmu@10060000 {
332                         compatible = "samsung,exynos5250-tmu";
333                         reg = <0x10060000 0x100>;
334                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
335                         clocks = <&clock CLK_TMU>;
336                         clock-names = "tmu_apbif";
337                         #thermal-sensor-cells = <0>;
338                 };
339
340                 sata: sata@122f0000 {
341                         compatible = "snps,dwc-ahci";
342                         samsung,sata-freq = <66>;
343                         reg = <0x122F0000 0x1ff>;
344                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
345                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
346                         clock-names = "sata", "sclk_sata";
347                         phys = <&sata_phy>;
348                         phy-names = "sata-phy";
349                         status = "disabled";
350                 };
351
352                 sata_phy: sata-phy@12170000 {
353                         compatible = "samsung,exynos5250-sata-phy";
354                         reg = <0x12170000 0x1ff>;
355                         clocks = <&clock CLK_SATA_PHYCTRL>;
356                         clock-names = "sata_phyctrl";
357                         #phy-cells = <0>;
358                         samsung,syscon-phandle = <&pmu_system_controller>;
359                         status = "disabled";
360                 };
361
362                 /* i2c_0-3 are defined in exynos5.dtsi */
363                 i2c_4: i2c@12ca0000 {
364                         compatible = "samsung,s3c2440-i2c";
365                         reg = <0x12CA0000 0x100>;
366                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
367                         #address-cells = <1>;
368                         #size-cells = <0>;
369                         clocks = <&clock CLK_I2C4>;
370                         clock-names = "i2c";
371                         pinctrl-names = "default";
372                         pinctrl-0 = <&i2c4_bus>;
373                         status = "disabled";
374                 };
375
376                 i2c_5: i2c@12cb0000 {
377                         compatible = "samsung,s3c2440-i2c";
378                         reg = <0x12CB0000 0x100>;
379                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
380                         #address-cells = <1>;
381                         #size-cells = <0>;
382                         clocks = <&clock CLK_I2C5>;
383                         clock-names = "i2c";
384                         pinctrl-names = "default";
385                         pinctrl-0 = <&i2c5_bus>;
386                         status = "disabled";
387                 };
388
389                 i2c_6: i2c@12cc0000 {
390                         compatible = "samsung,s3c2440-i2c";
391                         reg = <0x12CC0000 0x100>;
392                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
393                         #address-cells = <1>;
394                         #size-cells = <0>;
395                         clocks = <&clock CLK_I2C6>;
396                         clock-names = "i2c";
397                         pinctrl-names = "default";
398                         pinctrl-0 = <&i2c6_bus>;
399                         status = "disabled";
400                 };
401
402                 i2c_7: i2c@12cd0000 {
403                         compatible = "samsung,s3c2440-i2c";
404                         reg = <0x12CD0000 0x100>;
405                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
406                         #address-cells = <1>;
407                         #size-cells = <0>;
408                         clocks = <&clock CLK_I2C7>;
409                         clock-names = "i2c";
410                         pinctrl-names = "default";
411                         pinctrl-0 = <&i2c7_bus>;
412                         status = "disabled";
413                 };
414
415                 i2c_8: i2c@12ce0000 {
416                         compatible = "samsung,s3c2440-hdmiphy-i2c";
417                         reg = <0x12CE0000 0x1000>;
418                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
419                         #address-cells = <1>;
420                         #size-cells = <0>;
421                         clocks = <&clock CLK_I2C_HDMI>;
422                         clock-names = "i2c";
423                         status = "disabled";
424
425                         hdmiphy: hdmiphy@38 {
426                                 compatible = "samsung,exynos4212-hdmiphy";
427                                 reg = <0x38>;
428                         };
429                 };
430
431                 i2c_9: i2c@121d0000 {
432                         compatible = "samsung,exynos5-sata-phy-i2c";
433                         reg = <0x121D0000 0x100>;
434                         #address-cells = <1>;
435                         #size-cells = <0>;
436                         clocks = <&clock CLK_SATA_PHYI2C>;
437                         clock-names = "i2c";
438                         status = "disabled";
439                 };
440
441                 spi_0: spi@12d20000 {
442                         compatible = "samsung,exynos4210-spi";
443                         status = "disabled";
444                         reg = <0x12d20000 0x100>;
445                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
446                         dmas = <&pdma0 5
447                                 &pdma0 4>;
448                         dma-names = "tx", "rx";
449                         #address-cells = <1>;
450                         #size-cells = <0>;
451                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
452                         clock-names = "spi", "spi_busclk0";
453                         pinctrl-names = "default";
454                         pinctrl-0 = <&spi0_bus>;
455                 };
456
457                 spi_1: spi@12d30000 {
458                         compatible = "samsung,exynos4210-spi";
459                         status = "disabled";
460                         reg = <0x12d30000 0x100>;
461                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
462                         dmas = <&pdma1 5
463                                 &pdma1 4>;
464                         dma-names = "tx", "rx";
465                         #address-cells = <1>;
466                         #size-cells = <0>;
467                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
468                         clock-names = "spi", "spi_busclk0";
469                         pinctrl-names = "default";
470                         pinctrl-0 = <&spi1_bus>;
471                 };
472
473                 spi_2: spi@12d40000 {
474                         compatible = "samsung,exynos4210-spi";
475                         status = "disabled";
476                         reg = <0x12d40000 0x100>;
477                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
478                         dmas = <&pdma0 7
479                                 &pdma0 6>;
480                         dma-names = "tx", "rx";
481                         #address-cells = <1>;
482                         #size-cells = <0>;
483                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
484                         clock-names = "spi", "spi_busclk0";
485                         pinctrl-names = "default";
486                         pinctrl-0 = <&spi2_bus>;
487                 };
488
489                 mmc_0: mmc@12200000 {
490                         compatible = "samsung,exynos5250-dw-mshc";
491                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
492                         #address-cells = <1>;
493                         #size-cells = <0>;
494                         reg = <0x12200000 0x1000>;
495                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
496                         clock-names = "biu", "ciu";
497                         fifo-depth = <0x80>;
498                         status = "disabled";
499                 };
500
501                 mmc_1: mmc@12210000 {
502                         compatible = "samsung,exynos5250-dw-mshc";
503                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
504                         #address-cells = <1>;
505                         #size-cells = <0>;
506                         reg = <0x12210000 0x1000>;
507                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
508                         clock-names = "biu", "ciu";
509                         fifo-depth = <0x80>;
510                         status = "disabled";
511                 };
512
513                 mmc_2: mmc@12220000 {
514                         compatible = "samsung,exynos5250-dw-mshc";
515                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
516                         #address-cells = <1>;
517                         #size-cells = <0>;
518                         reg = <0x12220000 0x1000>;
519                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
520                         clock-names = "biu", "ciu";
521                         fifo-depth = <0x80>;
522                         status = "disabled";
523                 };
524
525                 mmc_3: mmc@12230000 {
526                         compatible = "samsung,exynos5250-dw-mshc";
527                         reg = <0x12230000 0x1000>;
528                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
529                         #address-cells = <1>;
530                         #size-cells = <0>;
531                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
532                         clock-names = "biu", "ciu";
533                         fifo-depth = <0x80>;
534                         status = "disabled";
535                 };
536
537                 i2s0: i2s@3830000 {
538                         compatible = "samsung,s5pv210-i2s";
539                         status = "disabled";
540                         reg = <0x03830000 0x100>;
541                         dmas = <&pdma0 10
542                                 &pdma0 9
543                                 &pdma0 8>;
544                         dma-names = "tx", "rx", "tx-sec";
545                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
546                                 <&clock_audss EXYNOS_I2S_BUS>,
547                                 <&clock_audss EXYNOS_SCLK_I2S>;
548                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
549                         samsung,idma-addr = <0x03000000>;
550                         pinctrl-names = "default";
551                         pinctrl-0 = <&i2s0_bus>;
552                         power-domains = <&pd_mau>;
553                         #clock-cells = <1>;
554                         #sound-dai-cells = <1>;
555                 };
556
557                 i2s1: i2s@12d60000 {
558                         compatible = "samsung,s3c6410-i2s";
559                         status = "disabled";
560                         reg = <0x12D60000 0x100>;
561                         dmas = <&pdma1 12
562                                 &pdma1 11>;
563                         dma-names = "tx", "rx";
564                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
565                         clock-names = "iis", "i2s_opclk0";
566                         pinctrl-names = "default";
567                         pinctrl-0 = <&i2s1_bus>;
568                         power-domains = <&pd_mau>;
569                         #sound-dai-cells = <1>;
570                 };
571
572                 i2s2: i2s@12d70000 {
573                         compatible = "samsung,s3c6410-i2s";
574                         status = "disabled";
575                         reg = <0x12D70000 0x100>;
576                         dmas = <&pdma0 12
577                                 &pdma0 11>;
578                         dma-names = "tx", "rx";
579                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
580                         clock-names = "iis", "i2s_opclk0";
581                         pinctrl-names = "default";
582                         pinctrl-0 = <&i2s2_bus>;
583                         power-domains = <&pd_mau>;
584                         #sound-dai-cells = <1>;
585                 };
586
587                 usb_dwc3 {
588                         compatible = "samsung,exynos5250-dwusb3";
589                         clocks = <&clock CLK_USB3>;
590                         clock-names = "usbdrd30";
591                         #address-cells = <1>;
592                         #size-cells = <1>;
593                         ranges;
594
595                         usbdrd_dwc3: dwc3@12000000 {
596                                 compatible = "synopsys,dwc3";
597                                 reg = <0x12000000 0x10000>;
598                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
599                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
600                                 phy-names = "usb2-phy", "usb3-phy";
601                         };
602                 };
603
604                 usbdrd_phy: phy@12100000 {
605                         compatible = "samsung,exynos5250-usbdrd-phy";
606                         reg = <0x12100000 0x100>;
607                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
608                         clock-names = "phy", "ref";
609                         samsung,pmu-syscon = <&pmu_system_controller>;
610                         #phy-cells = <1>;
611                 };
612
613                 ehci: usb@12110000 {
614                         compatible = "samsung,exynos4210-ehci";
615                         reg = <0x12110000 0x100>;
616                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617
618                         clocks = <&clock CLK_USB2>;
619                         clock-names = "usbhost";
620                         #address-cells = <1>;
621                         #size-cells = <0>;
622                         port@0 {
623                                 reg = <0>;
624                                 phys = <&usb2_phy_gen 1>;
625                         };
626                 };
627
628                 ohci: usb@12120000 {
629                         compatible = "samsung,exynos4210-ohci";
630                         reg = <0x12120000 0x100>;
631                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
632
633                         clocks = <&clock CLK_USB2>;
634                         clock-names = "usbhost";
635                         #address-cells = <1>;
636                         #size-cells = <0>;
637                         port@0 {
638                                 reg = <0>;
639                                 phys = <&usb2_phy_gen 1>;
640                         };
641                 };
642
643                 usb2_phy_gen: phy@12130000 {
644                         compatible = "samsung,exynos5250-usb2-phy";
645                         reg = <0x12130000 0x100>;
646                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
647                         clock-names = "phy", "ref";
648                         #phy-cells = <1>;
649                         samsung,sysreg-phandle = <&sysreg_system_controller>;
650                         samsung,pmureg-phandle = <&pmu_system_controller>;
651                 };
652
653                 amba {
654                         #address-cells = <1>;
655                         #size-cells = <1>;
656                         compatible = "simple-bus";
657                         interrupt-parent = <&gic>;
658                         ranges;
659
660                         pdma0: pdma@121a0000 {
661                                 compatible = "arm,pl330", "arm,primecell";
662                                 reg = <0x121A0000 0x1000>;
663                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
664                                 clocks = <&clock CLK_PDMA0>;
665                                 clock-names = "apb_pclk";
666                                 #dma-cells = <1>;
667                                 #dma-channels = <8>;
668                                 #dma-requests = <32>;
669                         };
670
671                         pdma1: pdma@121b0000 {
672                                 compatible = "arm,pl330", "arm,primecell";
673                                 reg = <0x121B0000 0x1000>;
674                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
675                                 clocks = <&clock CLK_PDMA1>;
676                                 clock-names = "apb_pclk";
677                                 #dma-cells = <1>;
678                                 #dma-channels = <8>;
679                                 #dma-requests = <32>;
680                         };
681
682                         mdma0: mdma@10800000 {
683                                 compatible = "arm,pl330", "arm,primecell";
684                                 reg = <0x10800000 0x1000>;
685                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
686                                 clocks = <&clock CLK_MDMA0>;
687                                 clock-names = "apb_pclk";
688                                 #dma-cells = <1>;
689                                 #dma-channels = <8>;
690                                 #dma-requests = <1>;
691                         };
692
693                         mdma1: mdma@11c10000 {
694                                 compatible = "arm,pl330", "arm,primecell";
695                                 reg = <0x11C10000 0x1000>;
696                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
697                                 clocks = <&clock CLK_MDMA1>;
698                                 clock-names = "apb_pclk";
699                                 #dma-cells = <1>;
700                                 #dma-channels = <8>;
701                                 #dma-requests = <1>;
702                         };
703                 };
704
705                 gsc_0:  gsc@13e00000 {
706                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
707                         reg = <0x13e00000 0x1000>;
708                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
709                         power-domains = <&pd_gsc>;
710                         clocks = <&clock CLK_GSCL0>;
711                         clock-names = "gscl";
712                         iommus = <&sysmmu_gsc0>;
713                 };
714
715                 gsc_1:  gsc@13e10000 {
716                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
717                         reg = <0x13e10000 0x1000>;
718                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
719                         power-domains = <&pd_gsc>;
720                         clocks = <&clock CLK_GSCL1>;
721                         clock-names = "gscl";
722                         iommus = <&sysmmu_gsc1>;
723                 };
724
725                 gsc_2:  gsc@13e20000 {
726                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
727                         reg = <0x13e20000 0x1000>;
728                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
729                         power-domains = <&pd_gsc>;
730                         clocks = <&clock CLK_GSCL2>;
731                         clock-names = "gscl";
732                         iommus = <&sysmmu_gsc2>;
733                 };
734
735                 gsc_3:  gsc@13e30000 {
736                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
737                         reg = <0x13e30000 0x1000>;
738                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
739                         power-domains = <&pd_gsc>;
740                         clocks = <&clock CLK_GSCL3>;
741                         clock-names = "gscl";
742                         iommus = <&sysmmu_gsc3>;
743                 };
744
745                 hdmi: hdmi@14530000 {
746                         compatible = "samsung,exynos4212-hdmi";
747                         reg = <0x14530000 0x70000>;
748                         power-domains = <&pd_disp1>;
749                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
750                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
751                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
752                                  <&clock CLK_MOUT_HDMI>;
753                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
754                                         "sclk_hdmiphy", "mout_hdmi";
755                         samsung,syscon-phandle = <&pmu_system_controller>;
756                         phy = <&hdmiphy>;
757                         #sound-dai-cells = <0>;
758                         status = "disabled";
759                 };
760
761                 hdmicec: cec@101b0000 {
762                         compatible = "samsung,s5p-cec";
763                         reg = <0x101B0000 0x200>;
764                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
765                         clocks = <&clock CLK_HDMI_CEC>;
766                         clock-names = "hdmicec";
767                         samsung,syscon-phandle = <&pmu_system_controller>;
768                         hdmi-phandle = <&hdmi>;
769                         pinctrl-names = "default";
770                         pinctrl-0 = <&hdmi_cec>;
771                         status = "disabled";
772                 };
773
774                 mixer: mixer@14450000 {
775                         compatible = "samsung,exynos5250-mixer";
776                         reg = <0x14450000 0x10000>;
777                         power-domains = <&pd_disp1>;
778                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
779                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
780                                  <&clock CLK_SCLK_HDMI>;
781                         clock-names = "mixer", "hdmi", "sclk_hdmi";
782                         iommus = <&sysmmu_tv>;
783                         status = "disabled";
784                 };
785
786                 dp_phy: video-phy {
787                         compatible = "samsung,exynos5250-dp-video-phy";
788                         samsung,pmu-syscon = <&pmu_system_controller>;
789                         #phy-cells = <0>;
790                 };
791
792                 mipi_phy: video-phy@10040710 {
793                         compatible = "samsung,s5pv210-mipi-video-phy";
794                         reg = <0x10040710 0x100>;
795                         #phy-cells = <1>;
796                         syscon = <&pmu_system_controller>;
797                 };
798
799                 dsi_0: dsi@14500000 {
800                         compatible = "samsung,exynos4210-mipi-dsi";
801                         reg = <0x14500000 0x10000>;
802                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
803                         samsung,power-domain = <&pd_disp1>;
804                         phys = <&mipi_phy 3>;
805                         phy-names = "dsim";
806                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
807                         clock-names = "bus_clk", "sclk_mipi";
808                         status = "disabled";
809                         #address-cells = <1>;
810                         #size-cells = <0>;
811                 };
812
813                 adc: adc@12d10000 {
814                         compatible = "samsung,exynos-adc-v1";
815                         reg = <0x12D10000 0x100>;
816                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
817                         clocks = <&clock CLK_ADC>;
818                         clock-names = "adc";
819                         #io-channel-cells = <1>;
820                         io-channel-ranges;
821                         samsung,syscon-phandle = <&pmu_system_controller>;
822                         status = "disabled";
823                 };
824
825                 sysmmu_g2d: sysmmu@10a60000 {
826                         compatible = "samsung,exynos-sysmmu";
827                         reg = <0x10A60000 0x1000>;
828                         interrupt-parent = <&combiner>;
829                         interrupts = <24 5>;
830                         clock-names = "sysmmu", "master";
831                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
832                         #iommu-cells = <0>;
833                 };
834
835                 sysmmu_mfc_r: sysmmu@11200000 {
836                         compatible = "samsung,exynos-sysmmu";
837                         reg = <0x11200000 0x1000>;
838                         interrupt-parent = <&combiner>;
839                         interrupts = <6 2>;
840                         power-domains = <&pd_mfc>;
841                         clock-names = "sysmmu", "master";
842                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
843                         #iommu-cells = <0>;
844                 };
845
846                 sysmmu_mfc_l: sysmmu@11210000 {
847                         compatible = "samsung,exynos-sysmmu";
848                         reg = <0x11210000 0x1000>;
849                         interrupt-parent = <&combiner>;
850                         interrupts = <8 5>;
851                         power-domains = <&pd_mfc>;
852                         clock-names = "sysmmu", "master";
853                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
854                         #iommu-cells = <0>;
855                 };
856
857                 sysmmu_rotator: sysmmu@11d40000 {
858                         compatible = "samsung,exynos-sysmmu";
859                         reg = <0x11D40000 0x1000>;
860                         interrupt-parent = <&combiner>;
861                         interrupts = <4 0>;
862                         clock-names = "sysmmu", "master";
863                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
864                         #iommu-cells = <0>;
865                 };
866
867                 sysmmu_jpeg: sysmmu@11f20000 {
868                         compatible = "samsung,exynos-sysmmu";
869                         reg = <0x11F20000 0x1000>;
870                         interrupt-parent = <&combiner>;
871                         interrupts = <4 2>;
872                         power-domains = <&pd_gsc>;
873                         clock-names = "sysmmu", "master";
874                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
875                         #iommu-cells = <0>;
876                 };
877
878                 sysmmu_fimc_isp: sysmmu@13260000 {
879                         compatible = "samsung,exynos-sysmmu";
880                         reg = <0x13260000 0x1000>;
881                         interrupt-parent = <&combiner>;
882                         interrupts = <10 6>;
883                         clock-names = "sysmmu";
884                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
885                         #iommu-cells = <0>;
886                 };
887
888                 sysmmu_fimc_drc: sysmmu@13270000 {
889                         compatible = "samsung,exynos-sysmmu";
890                         reg = <0x13270000 0x1000>;
891                         interrupt-parent = <&combiner>;
892                         interrupts = <11 6>;
893                         clock-names = "sysmmu";
894                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
895                         #iommu-cells = <0>;
896                 };
897
898                 sysmmu_fimc_fd: sysmmu@132a0000 {
899                         compatible = "samsung,exynos-sysmmu";
900                         reg = <0x132A0000 0x1000>;
901                         interrupt-parent = <&combiner>;
902                         interrupts = <5 0>;
903                         clock-names = "sysmmu";
904                         clocks = <&clock CLK_SMMU_FIMC_FD>;
905                         #iommu-cells = <0>;
906                 };
907
908                 sysmmu_fimc_scc: sysmmu@13280000 {
909                         compatible = "samsung,exynos-sysmmu";
910                         reg = <0x13280000 0x1000>;
911                         interrupt-parent = <&combiner>;
912                         interrupts = <5 2>;
913                         clock-names = "sysmmu";
914                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
915                         #iommu-cells = <0>;
916                 };
917
918                 sysmmu_fimc_scp: sysmmu@13290000 {
919                         compatible = "samsung,exynos-sysmmu";
920                         reg = <0x13290000 0x1000>;
921                         interrupt-parent = <&combiner>;
922                         interrupts = <3 6>;
923                         clock-names = "sysmmu";
924                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
925                         #iommu-cells = <0>;
926                 };
927
928                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
929                         compatible = "samsung,exynos-sysmmu";
930                         reg = <0x132B0000 0x1000>;
931                         interrupt-parent = <&combiner>;
932                         interrupts = <5 4>;
933                         clock-names = "sysmmu";
934                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
935                         #iommu-cells = <0>;
936                 };
937
938                 sysmmu_fimc_odc: sysmmu@132c0000 {
939                         compatible = "samsung,exynos-sysmmu";
940                         reg = <0x132C0000 0x1000>;
941                         interrupt-parent = <&combiner>;
942                         interrupts = <11 0>;
943                         clock-names = "sysmmu";
944                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
945                         #iommu-cells = <0>;
946                 };
947
948                 sysmmu_fimc_dis0: sysmmu@132d0000 {
949                         compatible = "samsung,exynos-sysmmu";
950                         reg = <0x132D0000 0x1000>;
951                         interrupt-parent = <&combiner>;
952                         interrupts = <10 4>;
953                         clock-names = "sysmmu";
954                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
955                         #iommu-cells = <0>;
956                 };
957
958                 sysmmu_fimc_dis1: sysmmu@132e0000 {
959                         compatible = "samsung,exynos-sysmmu";
960                         reg = <0x132E0000 0x1000>;
961                         interrupt-parent = <&combiner>;
962                         interrupts = <9 4>;
963                         clock-names = "sysmmu";
964                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
965                         #iommu-cells = <0>;
966                 };
967
968                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
969                         compatible = "samsung,exynos-sysmmu";
970                         reg = <0x132F0000 0x1000>;
971                         interrupt-parent = <&combiner>;
972                         interrupts = <5 6>;
973                         clock-names = "sysmmu";
974                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
975                         #iommu-cells = <0>;
976                 };
977
978                 sysmmu_fimc_lite0: sysmmu@13c40000 {
979                         compatible = "samsung,exynos-sysmmu";
980                         reg = <0x13C40000 0x1000>;
981                         interrupt-parent = <&combiner>;
982                         interrupts = <3 4>;
983                         power-domains = <&pd_gsc>;
984                         clock-names = "sysmmu", "master";
985                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
986                         #iommu-cells = <0>;
987                 };
988
989                 sysmmu_fimc_lite1: sysmmu@13c50000 {
990                         compatible = "samsung,exynos-sysmmu";
991                         reg = <0x13C50000 0x1000>;
992                         interrupt-parent = <&combiner>;
993                         interrupts = <24 1>;
994                         power-domains = <&pd_gsc>;
995                         clock-names = "sysmmu", "master";
996                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
997                         #iommu-cells = <0>;
998                 };
999
1000                 sysmmu_gsc0: sysmmu@13e80000 {
1001                         compatible = "samsung,exynos-sysmmu";
1002                         reg = <0x13E80000 0x1000>;
1003                         interrupt-parent = <&combiner>;
1004                         interrupts = <2 0>;
1005                         power-domains = <&pd_gsc>;
1006                         clock-names = "sysmmu", "master";
1007                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1008                         #iommu-cells = <0>;
1009                 };
1010
1011                 sysmmu_gsc1: sysmmu@13e90000 {
1012                         compatible = "samsung,exynos-sysmmu";
1013                         reg = <0x13E90000 0x1000>;
1014                         interrupt-parent = <&combiner>;
1015                         interrupts = <2 2>;
1016                         power-domains = <&pd_gsc>;
1017                         clock-names = "sysmmu", "master";
1018                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1019                         #iommu-cells = <0>;
1020                 };
1021
1022                 sysmmu_gsc2: sysmmu@13ea0000 {
1023                         compatible = "samsung,exynos-sysmmu";
1024                         reg = <0x13EA0000 0x1000>;
1025                         interrupt-parent = <&combiner>;
1026                         interrupts = <2 4>;
1027                         power-domains = <&pd_gsc>;
1028                         clock-names = "sysmmu", "master";
1029                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1030                         #iommu-cells = <0>;
1031                 };
1032
1033                 sysmmu_gsc3: sysmmu@13eb0000 {
1034                         compatible = "samsung,exynos-sysmmu";
1035                         reg = <0x13EB0000 0x1000>;
1036                         interrupt-parent = <&combiner>;
1037                         interrupts = <2 6>;
1038                         power-domains = <&pd_gsc>;
1039                         clock-names = "sysmmu", "master";
1040                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1041                         #iommu-cells = <0>;
1042                 };
1043
1044                 sysmmu_fimd1: sysmmu@14640000 {
1045                         compatible = "samsung,exynos-sysmmu";
1046                         reg = <0x14640000 0x1000>;
1047                         interrupt-parent = <&combiner>;
1048                         interrupts = <3 2>;
1049                         power-domains = <&pd_disp1>;
1050                         clock-names = "sysmmu", "master";
1051                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1052                         #iommu-cells = <0>;
1053                 };
1054
1055                 sysmmu_tv: sysmmu@14650000 {
1056                         compatible = "samsung,exynos-sysmmu";
1057                         reg = <0x14650000 0x1000>;
1058                         interrupt-parent = <&combiner>;
1059                         interrupts = <7 4>;
1060                         power-domains = <&pd_disp1>;
1061                         clock-names = "sysmmu", "master";
1062                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1063                         #iommu-cells = <0>;
1064                 };
1065         };
1066
1067         thermal-zones {
1068                 cpu_thermal: cpu-thermal {
1069                         polling-delay-passive = <0>;
1070                         polling-delay = <0>;
1071                         thermal-sensors = <&tmu 0>;
1072
1073                         cooling-maps {
1074                                 map0 {
1075                                      /* Corresponds to 800MHz at freq_table */
1076                                      cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1077                                 };
1078                                 map1 {
1079                                      /* Corresponds to 200MHz at freq_table */
1080                                      cooling-device = <&cpu0 15 15>,
1081                                                       <&cpu1 15 15>;
1082                                };
1083                        };
1084                 };
1085         };
1086
1087         timer {
1088                 compatible = "arm,armv7-timer";
1089                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1090                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1091                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1092                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1093                 /*
1094                  * Unfortunately we need this since some versions
1095                  * of U-Boot on Exynos don't set the CNTFRQ register,
1096                  * so we need the value from DT.
1097                  */
1098                 clock-frequency = <24000000>;
1099         };
1100 };
1101
1102 &dp {
1103         power-domains = <&pd_disp1>;
1104         clocks = <&clock CLK_DP>;
1105         clock-names = "dp";
1106         phys = <&dp_phy>;
1107         phy-names = "dp";
1108 };
1109
1110 &fimd {
1111         power-domains = <&pd_disp1>;
1112         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1113         clock-names = "sclk_fimd", "fimd";
1114         iommus = <&sysmmu_fimd1>;
1115 };
1116
1117 &g2d {
1118         iommus = <&sysmmu_g2d>;
1119         clocks = <&clock CLK_G2D>;
1120         clock-names = "fimg2d";
1121         status = "okay";
1122 };
1123
1124 &i2c_0 {
1125         clocks = <&clock CLK_I2C0>;
1126         clock-names = "i2c";
1127         pinctrl-names = "default";
1128         pinctrl-0 = <&i2c0_bus>;
1129 };
1130
1131 &i2c_1 {
1132         clocks = <&clock CLK_I2C1>;
1133         clock-names = "i2c";
1134         pinctrl-names = "default";
1135         pinctrl-0 = <&i2c1_bus>;
1136 };
1137
1138 &i2c_2 {
1139         clocks = <&clock CLK_I2C2>;
1140         clock-names = "i2c";
1141         pinctrl-names = "default";
1142         pinctrl-0 = <&i2c2_bus>;
1143 };
1144
1145 &i2c_3 {
1146         clocks = <&clock CLK_I2C3>;
1147         clock-names = "i2c";
1148         pinctrl-names = "default";
1149         pinctrl-0 = <&i2c3_bus>;
1150 };
1151
1152 &prng {
1153         clocks = <&clock CLK_SSS>;
1154         clock-names = "secss";
1155 };
1156
1157 &pwm {
1158         clocks = <&clock CLK_PWM>;
1159         clock-names = "timers";
1160 };
1161
1162 &rtc {
1163         clocks = <&clock CLK_RTC>;
1164         clock-names = "rtc";
1165         interrupt-parent = <&pmu_system_controller>;
1166         status = "disabled";
1167 };
1168
1169 &serial_0 {
1170         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1171         clock-names = "uart", "clk_uart_baud0";
1172         dmas = <&pdma0 13>, <&pdma0 14>;
1173         dma-names = "rx", "tx";
1174 };
1175
1176 &serial_1 {
1177         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1178         clock-names = "uart", "clk_uart_baud0";
1179         dmas = <&pdma1 15>, <&pdma1 16>;
1180         dma-names = "rx", "tx";
1181 };
1182
1183 &serial_2 {
1184         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1185         clock-names = "uart", "clk_uart_baud0";
1186         dmas = <&pdma0 15>, <&pdma0 16>;
1187         dma-names = "rx", "tx";
1188 };
1189
1190 &serial_3 {
1191         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1192         clock-names = "uart", "clk_uart_baud0";
1193         dmas = <&pdma1 17>, <&pdma1 18>;
1194         dma-names = "rx", "tx";
1195 };
1196
1197 &sss {
1198         clocks = <&clock CLK_SSS>;
1199         clock-names = "secss";
1200 };
1201
1202 &trng {
1203         clocks = <&clock CLK_SSS>;
1204         clock-names = "secss";
1205 };
1206
1207 #include "exynos5250-pinctrl.dtsi"
1208 #include "exynos-syscon-restart.dtsi"