arch/arm/boot/dts/exynos5250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5250 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   9  * EXYNOS5250 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  14  * additional nodes can be added to this file.
  15  */
  16
  17 #include <dt-bindings/clock/exynos5250.h>
  18 #include "exynos5.dtsi"
  19 #include "exynos4-cpu-thermal.dtsi"
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5250", "samsung,exynos5";
  24
  25         aliases {
  26                 spi0 = &spi_0;
  27                 spi1 = &spi_1;
  28                 spi2 = &spi_2;
  29                 gsc0 = &gsc_0;
  30                 gsc1 = &gsc_1;
  31                 gsc2 = &gsc_2;
  32                 gsc3 = &gsc_3;
  33                 mshc0 = &mmc_0;
  34                 mshc1 = &mmc_1;
  35                 mshc2 = &mmc_2;
  36                 mshc3 = &mmc_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 i2c9 = &i2c_9;
  43                 pinctrl0 = &pinctrl_0;
  44                 pinctrl1 = &pinctrl_1;
  45                 pinctrl2 = &pinctrl_2;
  46                 pinctrl3 = &pinctrl_3;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a15";
  56                         reg = <0>;
  57                         clock-frequency = <1700000000>;
  58                         clocks = <&clock CLK_ARM_CLK>;
  59                         clock-names = "cpu";
  60                         clock-latency = <140000>;
  61
  62                         operating-points = <
  63                                 1700000 1300000
  64                                 1600000 1250000
  65                                 1500000 1225000
  66                                 1400000 1200000
  67                                 1300000 1150000
  68                                 1200000 1125000
  69                                 1100000 1100000
  70                                 1000000 1075000
  71                                  900000 1050000
  72                                  800000 1025000
  73                                  700000 1012500
  74                                  600000 1000000
  75                                  500000  975000
  76                                  400000  950000
  77                                  300000  937500
  78                                  200000  925000
  79                         >;
  80                         cooling-min-level = <15>;
  81                         cooling-max-level = <9>;
  82                         #cooling-cells = <2>; /* min followed by max */
  83                 };
  84                 cpu@1 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a15";
  87                         reg = <1>;
  88                         clock-frequency = <1700000000>;
  89                 };
  90         };
  91
  92         soc: soc {
  93                 sysram@2020000 {
  94                         compatible = "mmio-sram";
  95                         reg = <0x02020000 0x30000>;
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         ranges = <0 0x02020000 0x30000>;
  99
 100                         smp-sysram@0 {
 101                                 compatible = "samsung,exynos4210-sysram";
 102                                 reg = <0x0 0x1000>;
 103                         };
 104
 105                         smp-sysram@2f000 {
 106                                 compatible = "samsung,exynos4210-sysram-ns";
 107                                 reg = <0x2f000 0x1000>;
 108                         };
 109                 };
 110
 111                 pd_gsc: power-domain@10044000 {
 112                         compatible = "samsung,exynos4210-pd";
 113                         reg = <0x10044000 0x20>;
 114                         #power-domain-cells = <0>;
 115                         label = "GSC";
 116                 };
 117
 118                 pd_mfc: power-domain@10044040 {
 119                         compatible = "samsung,exynos4210-pd";
 120                         reg = <0x10044040 0x20>;
 121                         #power-domain-cells = <0>;
 122                         label = "MFC";
 123                 };
 124
 125                 pd_g3d: power-domain@10044060 {
 126                         compatible = "samsung,exynos4210-pd";
 127                         reg = <0x10044060 0x20>;
 128                         #power-domain-cells = <0>;
 129                         label = "G3D";
 130                 };
 131
 132                 pd_disp1: power-domain@100440a0 {
 133                         compatible = "samsung,exynos4210-pd";
 134                         reg = <0x100440A0 0x20>;
 135                         #power-domain-cells = <0>;
 136                         label = "DISP1";
 137                         clocks = <&clock CLK_FIN_PLL>,
 138                                  <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
 139                                  <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
 140                         clock-names = "oscclk", "clk0", "clk1";
 141                 };
 142
 143                 pd_mau: power-domain@100440c0 {
 144                         compatible = "samsung,exynos4210-pd";
 145                         reg = <0x100440C0 0x20>;
 146                         #power-domain-cells = <0>;
 147                         label = "MAU";
 148                 };
 149
 150                 clock: clock-controller@10010000 {
 151                         compatible = "samsung,exynos5250-clock";
 152                         reg = <0x10010000 0x30000>;
 153                         #clock-cells = <1>;
 154                 };
 155
 156                 clock_audss: audss-clock-controller@3810000 {
 157                         compatible = "samsung,exynos5250-audss-clock";
 158                         reg = <0x03810000 0x0C>;
 159                         #clock-cells = <1>;
 160                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 161                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 162                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 163                         power-domains = <&pd_mau>;
 164                 };
 165
 166                 timer {
 167                         compatible = "arm,armv7-timer";
 168                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 170                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 171                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 172                         /*
 173                          * Unfortunately we need this since some versions
 174                          * of U-Boot on Exynos don't set the CNTFRQ register,
 175                          * so we need the value from DT.
 176                          */
 177                         clock-frequency = <24000000>;
 178                 };
 179
 180                 mct@101c0000 {
 181                         compatible = "samsung,exynos4210-mct";
 182                         reg = <0x101C0000 0x800>;
 183                         interrupt-controller;
 184                         #interrupt-cells = <2>;
 185                         interrupt-parent = <&mct_map>;
 186                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 187                                      <4 0>, <5 0>;
 188                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 189                         clock-names = "fin_pll", "mct";
 190
 191                         mct_map: mct-map {
 192                                 #interrupt-cells = <2>;
 193                                 #address-cells = <0>;
 194                                 #size-cells = <0>;
 195                                 interrupt-map = <0x0 0 &combiner 23 3>,
 196                                                 <0x1 0 &combiner 23 4>,
 197                                                 <0x2 0 &combiner 25 2>,
 198                                                 <0x3 0 &combiner 25 3>,
 199                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 200                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
 201                         };
 202                 };
 203
 204                 pmu {
 205                         compatible = "arm,cortex-a15-pmu";
 206                         interrupt-parent = <&combiner>;
 207                         interrupts = <1 2>, <22 4>;
 208                 };
 209
 210                 pinctrl_0: pinctrl@11400000 {
 211                         compatible = "samsung,exynos5250-pinctrl";
 212                         reg = <0x11400000 0x1000>;
 213                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 214
 215                         wakup_eint: wakeup-interrupt-controller {
 216                                 compatible = "samsung,exynos4210-wakeup-eint";
 217                                 interrupt-parent = <&gic>;
 218                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 219                         };
 220                 };
 221
 222                 pinctrl_1: pinctrl@13400000 {
 223                         compatible = "samsung,exynos5250-pinctrl";
 224                         reg = <0x13400000 0x1000>;
 225                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 226                 };
 227
 228                 pinctrl_2: pinctrl@10d10000 {
 229                         compatible = "samsung,exynos5250-pinctrl";
 230                         reg = <0x10d10000 0x1000>;
 231                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 232                 };
 233
 234                 pinctrl_3: pinctrl@3860000 {
 235                         compatible = "samsung,exynos5250-pinctrl";
 236                         reg = <0x03860000 0x1000>;
 237                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 238                         power-domains = <&pd_mau>;
 239                 };
 240
 241                 pmu_system_controller: system-controller@10040000 {
 242                         compatible = "samsung,exynos5250-pmu", "syscon";
 243                         reg = <0x10040000 0x5000>;
 244                         clock-names = "clkout16";
 245                         clocks = <&clock CLK_FIN_PLL>;
 246                         #clock-cells = <1>;
 247                         interrupt-controller;
 248                         #interrupt-cells = <3>;
 249                         interrupt-parent = <&gic>;
 250                 };
 251
 252                 watchdog@101d0000 {
 253                         compatible = "samsung,exynos5250-wdt";
 254                         reg = <0x101D0000 0x100>;
 255                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&clock CLK_WDT>;
 257                         clock-names = "watchdog";
 258                         samsung,syscon-phandle = <&pmu_system_controller>;
 259                 };
 260
 261                 mfc: codec@11000000 {
 262                         compatible = "samsung,mfc-v6";
 263                         reg = <0x11000000 0x10000>;
 264                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 265                         power-domains = <&pd_mfc>;
 266                         clocks = <&clock CLK_MFC>;
 267                         clock-names = "mfc";
 268                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 269                         iommu-names = "left", "right";
 270                 };
 271
 272                 rotator: rotator@11c00000 {
 273                         compatible = "samsung,exynos5250-rotator";
 274                         reg = <0x11C00000 0x64>;
 275                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&clock CLK_ROTATOR>;
 277                         clock-names = "rotator";
 278                         iommus = <&sysmmu_rotator>;
 279                 };
 280
 281                 tmu: tmu@10060000 {
 282                         compatible = "samsung,exynos5250-tmu";
 283                         reg = <0x10060000 0x100>;
 284                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&clock CLK_TMU>;
 286                         clock-names = "tmu_apbif";
 287                         #include "exynos4412-tmu-sensor-conf.dtsi"
 288                 };
 289
 290                 sata: sata@122f0000 {
 291                         compatible = "snps,dwc-ahci";
 292                         samsung,sata-freq = <66>;
 293                         reg = <0x122F0000 0x1ff>;
 294                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 296                         clock-names = "sata", "sclk_sata";
 297                         phys = <&sata_phy>;
 298                         phy-names = "sata-phy";
 299                         status = "disabled";
 300                 };
 301
 302                 sata_phy: sata-phy@12170000 {
 303                         compatible = "samsung,exynos5250-sata-phy";
 304                         reg = <0x12170000 0x1ff>;
 305                         clocks = <&clock CLK_SATA_PHYCTRL>;
 306                         clock-names = "sata_phyctrl";
 307                         #phy-cells = <0>;
 308                         samsung,syscon-phandle = <&pmu_system_controller>;
 309                         status = "disabled";
 310                 };
 311
 312                 /* i2c_0-3 are defined in exynos5.dtsi */
 313                 i2c_4: i2c@12ca0000 {
 314                         compatible = "samsung,s3c2440-i2c";
 315                         reg = <0x12CA0000 0x100>;
 316                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         clocks = <&clock CLK_I2C4>;
 320                         clock-names = "i2c";
 321                         pinctrl-names = "default";
 322                         pinctrl-0 = <&i2c4_bus>;
 323                         status = "disabled";
 324                 };
 325
 326                 i2c_5: i2c@12cb0000 {
 327                         compatible = "samsung,s3c2440-i2c";
 328                         reg = <0x12CB0000 0x100>;
 329                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         clocks = <&clock CLK_I2C5>;
 333                         clock-names = "i2c";
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&i2c5_bus>;
 336                         status = "disabled";
 337                 };
 338
 339                 i2c_6: i2c@12cc0000 {
 340                         compatible = "samsung,s3c2440-i2c";
 341                         reg = <0x12CC0000 0x100>;
 342                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         clocks = <&clock CLK_I2C6>;
 346                         clock-names = "i2c";
 347                         pinctrl-names = "default";
 348                         pinctrl-0 = <&i2c6_bus>;
 349                         status = "disabled";
 350                 };
 351
 352                 i2c_7: i2c@12cd0000 {
 353                         compatible = "samsung,s3c2440-i2c";
 354                         reg = <0x12CD0000 0x100>;
 355                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         clocks = <&clock CLK_I2C7>;
 359                         clock-names = "i2c";
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&i2c7_bus>;
 362                         status = "disabled";
 363                 };
 364
 365                 i2c_8: i2c@12ce0000 {
 366                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 367                         reg = <0x12CE0000 0x1000>;
 368                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         clocks = <&clock CLK_I2C_HDMI>;
 372                         clock-names = "i2c";
 373                         status = "disabled";
 374
 375                         hdmiphy: hdmiphy@38 {
 376                                 compatible = "samsung,exynos4212-hdmiphy";
 377                                 reg = <0x38>;
 378                         };
 379                 };
 380
 381                 i2c_9: i2c@121d0000 {
 382                         compatible = "samsung,exynos5-sata-phy-i2c";
 383                         reg = <0x121D0000 0x100>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         clocks = <&clock CLK_SATA_PHYI2C>;
 387                         clock-names = "i2c";
 388                         status = "disabled";
 389                 };
 390
 391                 spi_0: spi@12d20000 {
 392                         compatible = "samsung,exynos4210-spi";
 393                         status = "disabled";
 394                         reg = <0x12d20000 0x100>;
 395                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 396                         dmas = <&pdma0 5
 397                                 &pdma0 4>;
 398                         dma-names = "tx", "rx";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 402                         clock-names = "spi", "spi_busclk0";
 403                         pinctrl-names = "default";
 404                         pinctrl-0 = <&spi0_bus>;
 405                 };
 406
 407                 spi_1: spi@12d30000 {
 408                         compatible = "samsung,exynos4210-spi";
 409                         status = "disabled";
 410                         reg = <0x12d30000 0x100>;
 411                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 412                         dmas = <&pdma1 5
 413                                 &pdma1 4>;
 414                         dma-names = "tx", "rx";
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 418                         clock-names = "spi", "spi_busclk0";
 419                         pinctrl-names = "default";
 420                         pinctrl-0 = <&spi1_bus>;
 421                 };
 422
 423                 spi_2: spi@12d40000 {
 424                         compatible = "samsung,exynos4210-spi";
 425                         status = "disabled";
 426                         reg = <0x12d40000 0x100>;
 427                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 428                         dmas = <&pdma0 7
 429                                 &pdma0 6>;
 430                         dma-names = "tx", "rx";
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 434                         clock-names = "spi", "spi_busclk0";
 435                         pinctrl-names = "default";
 436                         pinctrl-0 = <&spi2_bus>;
 437                 };
 438
 439                 mmc_0: mmc@12200000 {
 440                         compatible = "samsung,exynos5250-dw-mshc";
 441                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         reg = <0x12200000 0x1000>;
 445                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 446                         clock-names = "biu", "ciu";
 447                         fifo-depth = <0x80>;
 448                         status = "disabled";
 449                 };
 450
 451                 mmc_1: mmc@12210000 {
 452                         compatible = "samsung,exynos5250-dw-mshc";
 453                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         reg = <0x12210000 0x1000>;
 457                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 458                         clock-names = "biu", "ciu";
 459                         fifo-depth = <0x80>;
 460                         status = "disabled";
 461                 };
 462
 463                 mmc_2: mmc@12220000 {
 464                         compatible = "samsung,exynos5250-dw-mshc";
 465                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         reg = <0x12220000 0x1000>;
 469                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 470                         clock-names = "biu", "ciu";
 471                         fifo-depth = <0x80>;
 472                         status = "disabled";
 473                 };
 474
 475                 mmc_3: mmc@12230000 {
 476                         compatible = "samsung,exynos5250-dw-mshc";
 477                         reg = <0x12230000 0x1000>;
 478                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 482                         clock-names = "biu", "ciu";
 483                         fifo-depth = <0x80>;
 484                         status = "disabled";
 485                 };
 486
 487                 i2s0: i2s@3830000 {
 488                         compatible = "samsung,s5pv210-i2s";
 489                         status = "disabled";
 490                         reg = <0x03830000 0x100>;
 491                         dmas = <&pdma0 10
 492                                 &pdma0 9
 493                                 &pdma0 8>;
 494                         dma-names = "tx", "rx", "tx-sec";
 495                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 496                                 <&clock_audss EXYNOS_I2S_BUS>,
 497                                 <&clock_audss EXYNOS_SCLK_I2S>;
 498                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 499                         samsung,idma-addr = <0x03000000>;
 500                         pinctrl-names = "default";
 501                         pinctrl-0 = <&i2s0_bus>;
 502                         power-domains = <&pd_mau>;
 503                 };
 504
 505                 i2s1: i2s@12d60000 {
 506                         compatible = "samsung,s3c6410-i2s";
 507                         status = "disabled";
 508                         reg = <0x12D60000 0x100>;
 509                         dmas = <&pdma1 12
 510                                 &pdma1 11>;
 511                         dma-names = "tx", "rx";
 512                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 513                         clock-names = "iis", "i2s_opclk0";
 514                         pinctrl-names = "default";
 515                         pinctrl-0 = <&i2s1_bus>;
 516                         power-domains = <&pd_mau>;
 517                 };
 518
 519                 i2s2: i2s@12d70000 {
 520                         compatible = "samsung,s3c6410-i2s";
 521                         status = "disabled";
 522                         reg = <0x12D70000 0x100>;
 523                         dmas = <&pdma0 12
 524                                 &pdma0 11>;
 525                         dma-names = "tx", "rx";
 526                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 527                         clock-names = "iis", "i2s_opclk0";
 528                         pinctrl-names = "default";
 529                         pinctrl-0 = <&i2s2_bus>;
 530                         power-domains = <&pd_mau>;
 531                 };
 532
 533                 usb_dwc3 {
 534                         compatible = "samsung,exynos5250-dwusb3";
 535                         clocks = <&clock CLK_USB3>;
 536                         clock-names = "usbdrd30";
 537                         #address-cells = <1>;
 538                         #size-cells = <1>;
 539                         ranges;
 540
 541                         usbdrd_dwc3: dwc3@12000000 {
 542                                 compatible = "synopsys,dwc3";
 543                                 reg = <0x12000000 0x10000>;
 544                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 545                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 546                                 phy-names = "usb2-phy", "usb3-phy";
 547                         };
 548                 };
 549
 550                 usbdrd_phy: phy@12100000 {
 551                         compatible = "samsung,exynos5250-usbdrd-phy";
 552                         reg = <0x12100000 0x100>;
 553                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 554                         clock-names = "phy", "ref";
 555                         samsung,pmu-syscon = <&pmu_system_controller>;
 556                         #phy-cells = <1>;
 557                 };
 558
 559                 ehci: usb@12110000 {
 560                         compatible = "samsung,exynos4210-ehci";
 561                         reg = <0x12110000 0x100>;
 562                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 563
 564                         clocks = <&clock CLK_USB2>;
 565                         clock-names = "usbhost";
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         port@0 {
 569                                 reg = <0>;
 570                                 phys = <&usb2_phy_gen 1>;
 571                         };
 572                 };
 573
 574                 ohci: usb@12120000 {
 575                         compatible = "samsung,exynos4210-ohci";
 576                         reg = <0x12120000 0x100>;
 577                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 578
 579                         clocks = <&clock CLK_USB2>;
 580                         clock-names = "usbhost";
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         port@0 {
 584                                 reg = <0>;
 585                                 phys = <&usb2_phy_gen 1>;
 586                         };
 587                 };
 588
 589                 usb2_phy_gen: phy@12130000 {
 590                         compatible = "samsung,exynos5250-usb2-phy";
 591                         reg = <0x12130000 0x100>;
 592                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 593                         clock-names = "phy", "ref";
 594                         #phy-cells = <1>;
 595                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 596                         samsung,pmureg-phandle = <&pmu_system_controller>;
 597                 };
 598
 599                 amba {
 600                         #address-cells = <1>;
 601                         #size-cells = <1>;
 602                         compatible = "simple-bus";
 603                         interrupt-parent = <&gic>;
 604                         ranges;
 605
 606                         pdma0: pdma@121a0000 {
 607                                 compatible = "arm,pl330", "arm,primecell";
 608                                 reg = <0x121A0000 0x1000>;
 609                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clock CLK_PDMA0>;
 611                                 clock-names = "apb_pclk";
 612                                 #dma-cells = <1>;
 613                                 #dma-channels = <8>;
 614                                 #dma-requests = <32>;
 615                         };
 616
 617                         pdma1: pdma@121b0000 {
 618                                 compatible = "arm,pl330", "arm,primecell";
 619                                 reg = <0x121B0000 0x1000>;
 620                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 621                                 clocks = <&clock CLK_PDMA1>;
 622                                 clock-names = "apb_pclk";
 623                                 #dma-cells = <1>;
 624                                 #dma-channels = <8>;
 625                                 #dma-requests = <32>;
 626                         };
 627
 628                         mdma0: mdma@10800000 {
 629                                 compatible = "arm,pl330", "arm,primecell";
 630                                 reg = <0x10800000 0x1000>;
 631                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 632                                 clocks = <&clock CLK_MDMA0>;
 633                                 clock-names = "apb_pclk";
 634                                 #dma-cells = <1>;
 635                                 #dma-channels = <8>;
 636                                 #dma-requests = <1>;
 637                         };
 638
 639                         mdma1: mdma@11c10000 {
 640                                 compatible = "arm,pl330", "arm,primecell";
 641                                 reg = <0x11C10000 0x1000>;
 642                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 643                                 clocks = <&clock CLK_MDMA1>;
 644                                 clock-names = "apb_pclk";
 645                                 #dma-cells = <1>;
 646                                 #dma-channels = <8>;
 647                                 #dma-requests = <1>;
 648                         };
 649                 };
 650
 651                 gsc_0:  gsc@13e00000 {
 652                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 653                         reg = <0x13e00000 0x1000>;
 654                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 655                         power-domains = <&pd_gsc>;
 656                         clocks = <&clock CLK_GSCL0>;
 657                         clock-names = "gscl";
 658                         iommu = <&sysmmu_gsc0>;
 659                 };
 660
 661                 gsc_1:  gsc@13e10000 {
 662                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 663                         reg = <0x13e10000 0x1000>;
 664                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 665                         power-domains = <&pd_gsc>;
 666                         clocks = <&clock CLK_GSCL1>;
 667                         clock-names = "gscl";
 668                         iommu = <&sysmmu_gsc1>;
 669                 };
 670
 671                 gsc_2:  gsc@13e20000 {
 672                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 673                         reg = <0x13e20000 0x1000>;
 674                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 675                         power-domains = <&pd_gsc>;
 676                         clocks = <&clock CLK_GSCL2>;
 677                         clock-names = "gscl";
 678                         iommu = <&sysmmu_gsc2>;
 679                 };
 680
 681                 gsc_3:  gsc@13e30000 {
 682                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 683                         reg = <0x13e30000 0x1000>;
 684                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 685                         power-domains = <&pd_gsc>;
 686                         clocks = <&clock CLK_GSCL3>;
 687                         clock-names = "gscl";
 688                         iommu = <&sysmmu_gsc3>;
 689                 };
 690
 691                 hdmi: hdmi@14530000 {
 692                         compatible = "samsung,exynos4212-hdmi";
 693                         reg = <0x14530000 0x70000>;
 694                         power-domains = <&pd_disp1>;
 695                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 697                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 698                                  <&clock CLK_MOUT_HDMI>;
 699                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 700                                         "sclk_hdmiphy", "mout_hdmi";
 701                         samsung,syscon-phandle = <&pmu_system_controller>;
 702                         phy = <&hdmiphy>;
 703                         status = "disabled";
 704                 };
 705
 706                 hdmicec: cec@101b0000 {
 707                         compatible = "samsung,s5p-cec";
 708                         reg = <0x101B0000 0x200>;
 709                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 710                         clocks = <&clock CLK_HDMI_CEC>;
 711                         clock-names = "hdmicec";
 712                         samsung,syscon-phandle = <&pmu_system_controller>;
 713                         hdmi-phandle = <&hdmi>;
 714                         pinctrl-names = "default";
 715                         pinctrl-0 = <&hdmi_cec>;
 716                         status = "disabled";
 717                 };
 718
 719                 mixer: mixer@14450000 {
 720                         compatible = "samsung,exynos5250-mixer";
 721                         reg = <0x14450000 0x10000>;
 722                         power-domains = <&pd_disp1>;
 723                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 725                                  <&clock CLK_SCLK_HDMI>;
 726                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 727                         iommus = <&sysmmu_tv>;
 728                         status = "disabled";
 729                 };
 730
 731                 dp_phy: video-phy {
 732                         compatible = "samsung,exynos5250-dp-video-phy";
 733                         samsung,pmu-syscon = <&pmu_system_controller>;
 734                         #phy-cells = <0>;
 735                 };
 736
 737                 adc: adc@12d10000 {
 738                         compatible = "samsung,exynos-adc-v1";
 739                         reg = <0x12D10000 0x100>;
 740                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 741                         clocks = <&clock CLK_ADC>;
 742                         clock-names = "adc";
 743                         #io-channel-cells = <1>;
 744                         io-channel-ranges;
 745                         samsung,syscon-phandle = <&pmu_system_controller>;
 746                         status = "disabled";
 747                 };
 748
 749                 sysmmu_g2d: sysmmu@10a60000 {
 750                         compatible = "samsung,exynos-sysmmu";
 751                         reg = <0x10A60000 0x1000>;
 752                         interrupt-parent = <&combiner>;
 753                         interrupts = <24 5>;
 754                         clock-names = "sysmmu", "master";
 755                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 756                         #iommu-cells = <0>;
 757                 };
 758
 759                 sysmmu_mfc_r: sysmmu@11200000 {
 760                         compatible = "samsung,exynos-sysmmu";
 761                         reg = <0x11200000 0x1000>;
 762                         interrupt-parent = <&combiner>;
 763                         interrupts = <6 2>;
 764                         power-domains = <&pd_mfc>;
 765                         clock-names = "sysmmu", "master";
 766                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 767                         #iommu-cells = <0>;
 768                 };
 769
 770                 sysmmu_mfc_l: sysmmu@11210000 {
 771                         compatible = "samsung,exynos-sysmmu";
 772                         reg = <0x11210000 0x1000>;
 773                         interrupt-parent = <&combiner>;
 774                         interrupts = <8 5>;
 775                         power-domains = <&pd_mfc>;
 776                         clock-names = "sysmmu", "master";
 777                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 778                         #iommu-cells = <0>;
 779                 };
 780
 781                 sysmmu_rotator: sysmmu@11d40000 {
 782                         compatible = "samsung,exynos-sysmmu";
 783                         reg = <0x11D40000 0x1000>;
 784                         interrupt-parent = <&combiner>;
 785                         interrupts = <4 0>;
 786                         clock-names = "sysmmu", "master";
 787                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 788                         #iommu-cells = <0>;
 789                 };
 790
 791                 sysmmu_jpeg: sysmmu@11f20000 {
 792                         compatible = "samsung,exynos-sysmmu";
 793                         reg = <0x11F20000 0x1000>;
 794                         interrupt-parent = <&combiner>;
 795                         interrupts = <4 2>;
 796                         power-domains = <&pd_gsc>;
 797                         clock-names = "sysmmu", "master";
 798                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 799                         #iommu-cells = <0>;
 800                 };
 801
 802                 sysmmu_fimc_isp: sysmmu@13260000 {
 803                         compatible = "samsung,exynos-sysmmu";
 804                         reg = <0x13260000 0x1000>;
 805                         interrupt-parent = <&combiner>;
 806                         interrupts = <10 6>;
 807                         clock-names = "sysmmu";
 808                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 809                         #iommu-cells = <0>;
 810                 };
 811
 812                 sysmmu_fimc_drc: sysmmu@13270000 {
 813                         compatible = "samsung,exynos-sysmmu";
 814                         reg = <0x13270000 0x1000>;
 815                         interrupt-parent = <&combiner>;
 816                         interrupts = <11 6>;
 817                         clock-names = "sysmmu";
 818                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 819                         #iommu-cells = <0>;
 820                 };
 821
 822                 sysmmu_fimc_fd: sysmmu@132a0000 {
 823                         compatible = "samsung,exynos-sysmmu";
 824                         reg = <0x132A0000 0x1000>;
 825                         interrupt-parent = <&combiner>;
 826                         interrupts = <5 0>;
 827                         clock-names = "sysmmu";
 828                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 829                         #iommu-cells = <0>;
 830                 };
 831
 832                 sysmmu_fimc_scc: sysmmu@13280000 {
 833                         compatible = "samsung,exynos-sysmmu";
 834                         reg = <0x13280000 0x1000>;
 835                         interrupt-parent = <&combiner>;
 836                         interrupts = <5 2>;
 837                         clock-names = "sysmmu";
 838                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 839                         #iommu-cells = <0>;
 840                 };
 841
 842                 sysmmu_fimc_scp: sysmmu@13290000 {
 843                         compatible = "samsung,exynos-sysmmu";
 844                         reg = <0x13290000 0x1000>;
 845                         interrupt-parent = <&combiner>;
 846                         interrupts = <3 6>;
 847                         clock-names = "sysmmu";
 848                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 849                         #iommu-cells = <0>;
 850                 };
 851
 852                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
 853                         compatible = "samsung,exynos-sysmmu";
 854                         reg = <0x132B0000 0x1000>;
 855                         interrupt-parent = <&combiner>;
 856                         interrupts = <5 4>;
 857                         clock-names = "sysmmu";
 858                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 859                         #iommu-cells = <0>;
 860                 };
 861
 862                 sysmmu_fimc_odc: sysmmu@132c0000 {
 863                         compatible = "samsung,exynos-sysmmu";
 864                         reg = <0x132C0000 0x1000>;
 865                         interrupt-parent = <&combiner>;
 866                         interrupts = <11 0>;
 867                         clock-names = "sysmmu";
 868                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 869                         #iommu-cells = <0>;
 870                 };
 871
 872                 sysmmu_fimc_dis0: sysmmu@132d0000 {
 873                         compatible = "samsung,exynos-sysmmu";
 874                         reg = <0x132D0000 0x1000>;
 875                         interrupt-parent = <&combiner>;
 876                         interrupts = <10 4>;
 877                         clock-names = "sysmmu";
 878                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 879                         #iommu-cells = <0>;
 880                 };
 881
 882                 sysmmu_fimc_dis1: sysmmu@132E0000{
 883                         compatible = "samsung,exynos-sysmmu";
 884                         reg = <0x132E0000 0x1000>;
 885                         interrupt-parent = <&combiner>;
 886                         interrupts = <9 4>;
 887                         clock-names = "sysmmu";
 888                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 889                         #iommu-cells = <0>;
 890                 };
 891
 892                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
 893                         compatible = "samsung,exynos-sysmmu";
 894                         reg = <0x132F0000 0x1000>;
 895                         interrupt-parent = <&combiner>;
 896                         interrupts = <5 6>;
 897                         clock-names = "sysmmu";
 898                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 899                         #iommu-cells = <0>;
 900                 };
 901
 902                 sysmmu_fimc_lite0: sysmmu@13c40000 {
 903                         compatible = "samsung,exynos-sysmmu";
 904                         reg = <0x13C40000 0x1000>;
 905                         interrupt-parent = <&combiner>;
 906                         interrupts = <3 4>;
 907                         power-domains = <&pd_gsc>;
 908                         clock-names = "sysmmu", "master";
 909                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 910                         #iommu-cells = <0>;
 911                 };
 912
 913                 sysmmu_fimc_lite1: sysmmu@13c50000 {
 914                         compatible = "samsung,exynos-sysmmu";
 915                         reg = <0x13C50000 0x1000>;
 916                         interrupt-parent = <&combiner>;
 917                         interrupts = <24 1>;
 918                         power-domains = <&pd_gsc>;
 919                         clock-names = "sysmmu", "master";
 920                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 921                         #iommu-cells = <0>;
 922                 };
 923
 924                 sysmmu_gsc0: sysmmu@13e80000 {
 925                         compatible = "samsung,exynos-sysmmu";
 926                         reg = <0x13E80000 0x1000>;
 927                         interrupt-parent = <&combiner>;
 928                         interrupts = <2 0>;
 929                         power-domains = <&pd_gsc>;
 930                         clock-names = "sysmmu", "master";
 931                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 932                         #iommu-cells = <0>;
 933                 };
 934
 935                 sysmmu_gsc1: sysmmu@13e90000 {
 936                         compatible = "samsung,exynos-sysmmu";
 937                         reg = <0x13E90000 0x1000>;
 938                         interrupt-parent = <&combiner>;
 939                         interrupts = <2 2>;
 940                         power-domains = <&pd_gsc>;
 941                         clock-names = "sysmmu", "master";
 942                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 943                         #iommu-cells = <0>;
 944                 };
 945
 946                 sysmmu_gsc2: sysmmu@13ea0000 {
 947                         compatible = "samsung,exynos-sysmmu";
 948                         reg = <0x13EA0000 0x1000>;
 949                         interrupt-parent = <&combiner>;
 950                         interrupts = <2 4>;
 951                         power-domains = <&pd_gsc>;
 952                         clock-names = "sysmmu", "master";
 953                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 954                         #iommu-cells = <0>;
 955                 };
 956
 957                 sysmmu_gsc3: sysmmu@13eb0000 {
 958                         compatible = "samsung,exynos-sysmmu";
 959                         reg = <0x13EB0000 0x1000>;
 960                         interrupt-parent = <&combiner>;
 961                         interrupts = <2 6>;
 962                         power-domains = <&pd_gsc>;
 963                         clock-names = "sysmmu", "master";
 964                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 965                         #iommu-cells = <0>;
 966                 };
 967
 968                 sysmmu_fimd1: sysmmu@14640000 {
 969                         compatible = "samsung,exynos-sysmmu";
 970                         reg = <0x14640000 0x1000>;
 971                         interrupt-parent = <&combiner>;
 972                         interrupts = <3 2>;
 973                         power-domains = <&pd_disp1>;
 974                         clock-names = "sysmmu", "master";
 975                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 976                         #iommu-cells = <0>;
 977                 };
 978
 979                 sysmmu_tv: sysmmu@14650000 {
 980                         compatible = "samsung,exynos-sysmmu";
 981                         reg = <0x14650000 0x1000>;
 982                         interrupt-parent = <&combiner>;
 983                         interrupts = <7 4>;
 984                         power-domains = <&pd_disp1>;
 985                         clock-names = "sysmmu", "master";
 986                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 987                         #iommu-cells = <0>;
 988                 };
 989         };
 990
 991         thermal-zones {
 992                 cpu_thermal: cpu-thermal {
 993                         polling-delay-passive = <0>;
 994                         polling-delay = <0>;
 995                         thermal-sensors = <&tmu 0>;
 996
 997                         cooling-maps {
 998                                 map0 {
 999                                      /* Corresponds to 800MHz at freq_table */
1000                                      cooling-device = <&cpu0 9 9>;
1001                                 };
1002                                 map1 {
1003                                      /* Corresponds to 200MHz at freq_table */
1004                                      cooling-device = <&cpu0 15 15>;
1005                                };
1006                        };
1007                 };
1008         };
1009 };
1010
1011 &dp {
1012         power-domains = <&pd_disp1>;
1013         clocks = <&clock CLK_DP>;
1014         clock-names = "dp";
1015         phys = <&dp_phy>;
1016         phy-names = "dp";
1017 };
1018
1019 &fimd {
1020         power-domains = <&pd_disp1>;
1021         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1022         clock-names = "sclk_fimd", "fimd";
1023         iommus = <&sysmmu_fimd1>;
1024 };
1025
1026 &g2d {
1027         iommus = <&sysmmu_g2d>;
1028         clocks = <&clock CLK_G2D>;
1029         clock-names = "fimg2d";
1030         status = "okay";
1031 };
1032
1033 &i2c_0 {
1034         clocks = <&clock CLK_I2C0>;
1035         clock-names = "i2c";
1036         pinctrl-names = "default";
1037         pinctrl-0 = <&i2c0_bus>;
1038 };
1039
1040 &i2c_1 {
1041         clocks = <&clock CLK_I2C1>;
1042         clock-names = "i2c";
1043         pinctrl-names = "default";
1044         pinctrl-0 = <&i2c1_bus>;
1045 };
1046
1047 &i2c_2 {
1048         clocks = <&clock CLK_I2C2>;
1049         clock-names = "i2c";
1050         pinctrl-names = "default";
1051         pinctrl-0 = <&i2c2_bus>;
1052 };
1053
1054 &i2c_3 {
1055         clocks = <&clock CLK_I2C3>;
1056         clock-names = "i2c";
1057         pinctrl-names = "default";
1058         pinctrl-0 = <&i2c3_bus>;
1059 };
1060
1061 &prng {
1062         clocks = <&clock CLK_SSS>;
1063         clock-names = "secss";
1064 };
1065
1066 &pwm {
1067         clocks = <&clock CLK_PWM>;
1068         clock-names = "timers";
1069 };
1070
1071 &rtc {
1072         clocks = <&clock CLK_RTC>;
1073         clock-names = "rtc";
1074         interrupt-parent = <&pmu_system_controller>;
1075         status = "disabled";
1076 };
1077
1078 &serial_0 {
1079         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1080         clock-names = "uart", "clk_uart_baud0";
1081         dmas = <&pdma0 13>, <&pdma0 14>;
1082         dma-names = "rx", "tx";
1083 };
1084
1085 &serial_1 {
1086         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1087         clock-names = "uart", "clk_uart_baud0";
1088         dmas = <&pdma1 15>, <&pdma1 16>;
1089         dma-names = "rx", "tx";
1090 };
1091
1092 &serial_2 {
1093         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1094         clock-names = "uart", "clk_uart_baud0";
1095         dmas = <&pdma0 15>, <&pdma0 16>;
1096         dma-names = "rx", "tx";
1097 };
1098
1099 &serial_3 {
1100         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1101         clock-names = "uart", "clk_uart_baud0";
1102         dmas = <&pdma1 17>, <&pdma1 18>;
1103         dma-names = "rx", "tx";
1104 };
1105
1106 &sss {
1107         clocks = <&clock CLK_SSS>;
1108         clock-names = "secss";
1109 };
1110
1111 &trng {
1112         clocks = <&clock CLK_SSS>;
1113         clock-names = "secss";
1114 };
1115
1116 #include "exynos5250-pinctrl.dtsi"